CN114400256A - A MOSFET device with integrated junction barrier Schottky - Google Patents

Abstract

The invention discloses an MOSFET device integrated with junction barrier Schottky, belongs to the field of semiconductor manufacturing, and is used for solving the technical problem that the proportion of the Schottky in the MOSFET device cannot be flexibly controlled by an embedded MOSFET cell integrated with the junction barrier Schottky. The MOSFET device includes: the junction barrier Schottky JBS unit cell comprises an epitaxial layer, a plurality of MOSFET unit cells and a plurality of junction barrier JBS unit cells, wherein the MOSFET unit cells and the junction barrier JBS unit cells are distributed on the surface of the epitaxial layer; the MOSFET cells and the JBS cells are arranged according to a preset proportion; each MOSFET unit cell at least comprises a well region, a source electrode region and a high-doped P-type region; each JBS unit cell comprises a plurality of layers of annular high-doped P-type regions and Schottky regions formed between the annular high-doped P-type regions; the ion doping concentration of the JFET area is larger than or equal to that of the epitaxial layer, the width of the JFET area and the distance between the annular high-doping P-type areas of each layer take values in a preset interval, and therefore the MOSFET device has small conduction voltage drop and strong electric field shielding capacity.

Description

A MOSFET device with integrated junction barrier Schottky

technical field

The present application relates to the field of power diodes, and in particular, to a MOSFET device with an integrated junction barrier Schottky.

Background technique

There are basal plane dislocations in silicon carbide crystals, and under certain conditions, basal plane dislocations can be converted into stacking faults. When the body diode in the SiC power MOSFET device is turned on, under bipolar operation, the recombination of electrons and holes will cause the stacking fault to continue to expand, resulting in bipolar degradation. This phenomenon increases the on-voltage resistance of the SiC power MOSFET device, increases the leakage current in blocking mode, and increases the on-voltage drop of the body diode in the SiC power MOSFET device, thereby reducing the power of the SiC power MOSFET. device reliability.

In practical circuit applications, in order to avoid bipolar degradation, external anti-parallel Schottky diodes are generally used to suppress body diodes in power MOSFET devices. However, this method will increase the size of the chip, and the unit price of the Schottky diode is high, so the product of this structure will increase the cost of the power MOSFET device. Junction-barrier Schottky diodes can be embedded into each cell in a power MOSFET device, thereby reducing overall chip size and cost. However, this embedded structure cannot flexibly control the proportion of Schottky in the MOSFET device, and the design flexibility is low.

SUMMARY OF THE INVENTION

An embodiment of the present application provides a MOSFET device with an integrated junction barrier Schottky, which is used to solve the following technical problem: an embedded MOSFET cell with an integrated junction barrier Schottky cannot flexibly control the Schottky in the MOSFET device. Proportion, low design flexibility.

The embodiment of the present application adopts the following technical solutions:

An embodiment of the present application provides a MOSFET device with an integrated junction barrier Schottky. The MOSFET device includes: an epitaxial layer, and several MOSFET cells and junction barrier Schottky JBS cells arranged on the surface of the epitaxial layer ; the epitaxial layer is an N-type semiconductor; the MOSFET cells and the JBS cells are arranged according to a preset ratio; each of the MOSFET cells includes a well region, a source region and a highly doped P-type region, the well region is a P-type semiconductor, and the source region is an N-type semiconductor; the source region is located inside the well region, and the source region surrounds the highly doped P-type region; wherein, The ion implantation depth of the source region is smaller than the ion implantation depth of the well region, the highly doped P-type region is in contact with the well region; the well region and the epitaxial layer form a first PN junction, The well region and the source region form a second PN junction; each of the JBS cells includes a multi-layer annular highly doped P-type region, and each layer of the annular highly doped P-type region. The Schottky region formed between them; the ring-shaped highly doped P-type region and the epitaxial layer form a third PN junction; the well region of the MOSFET cell and the outer ring-shaped height of the adjacent JBS cell A first junction field effect transistor JFET region is formed between the doped P-type regions; a second JFET region is formed between the well region of the MOSFET cell and the well region of an adjacent MOSFET cell; the first JFET region and the ion doping concentration of the second JFET region is greater than or equal to the ion doping concentration of the epitaxial layer, the width of the first JFET region and the second JFET region and the spacing of the annular highly doped P-type region of each layer All take values within the same preset interval.

In the embodiment of the present application, a Schottky (JBS) cell is embedded in a MOSFET cell, and the JBS cell and the MOSFET cell are arranged in a certain proportion to form a composite structure, so that the Schottky diode and the MOSFET device are shared A structure, so that the MOSFET device does not need an external parallel Schottky diode, reducing the size of the integrated chip. And the design of the composite structure can flexibly control the arrangement ratio of the two cells, so as to flexibly control the Schottky ratio in the MOSFET device and improve the design flexibility.

In a feasible implementation manner, the shape of the MOSFET cell and the JBS cell is the same, and the shape is a regular polygon or a circle; a plurality of MOSFET cells are arranged around a JBS cell; A MOSFET cells are arranged between two adjacent JBS cells; wherein, 1≤a≤100.

In a feasible implementation manner, the MOSFET device further includes a first contact metal; the first contact metal covers the surface of the highly doped P-type region in the well region, and is different from the surface of the highly doped P-type region in the well region. The highly doped P-type region forms an ohmic contact; a portion of the first contact metal is in contact with the source region to suppress parasitic bipolar transistor effects inside the MOSFET device.

In a feasible implementation manner, the MOSFET device further includes a second contact metal; the second contact metal covers the surface of the JBS cell and is connected to several Schottky regions in the JBS cell A Schottky contact is formed; a preset distance is maintained between the first contact metal and the second contact metal, so that through different processes, the first contact metal and the second contact metal are respectively designed as Ohmic and Schottky contacts.

In the embodiment of the present application, by designing the two contact metals into separate structures, it is more convenient to perform different process treatments on the two contact metals, and there is no interference between the two, thereby reducing the manufacturing difficulty of the MOSFET device and improving the device performance. The success rate of processing reduces the number of failed devices.

In a feasible implementation manner, the MOSFET device further comprises an insulating gate oxide layer; the insulating gate oxide layer covers the source region, the well region and the JFET region; the insulating gate oxide layer covers the source region, the well region and the JFET region; The width of the gate oxide layer covering the JFET region is greater than or equal to 0.1 μm and smaller than the width of the JFET region.

In a feasible implementation manner, the gate insulating oxide layer is covered with gate conductive polysilicon.

In a feasible implementation manner, the insulating gate oxide layer and the gate conductive polysilicon are coated with an insulating dielectric layer.

In a feasible implementation manner, the insulating medium layer, the first contact metal and the second contact metal are covered with a source electrode; the source electrode and the first contact metal and all the second contact metal is in contact; the insulating dielectric layer separates the insulating gate oxide layer and the gate conductive polysilicon from the source electrode.

In a feasible implementation manner, the MOSFET device further includes: a silicon carbide substrate, the silicon carbide substrate is located on the surface of the epitaxial layer away from the cell side; the silicon carbide substrate is N-type semiconductor; the ion doping concentration in the silicon carbide substrate is higher than the ion doping concentration in the epitaxial layer; the side of the silicon carbide substrate facing away from the epitaxial layer is covered with the drain electrode of the MOSFET device .

In a feasible implementation manner, the preset interval is [0.8 μm˜5 μm].

A MOSFET device with an integrated junction barrier Schottky provided by the embodiment of the present application has a polygonal or circular composite cell design, which can achieve better design flexibility and a higher total area of the JFET region, thereby making the MOSFET The device has a lower specific on-resistance.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort. In the attached image:

1 is a cross-sectional view of an active region of a MOSFET device with an integrated junction barrier Schottky provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a compound structure of a regular hexagonal cell provided in an embodiment of the present application;

3 is a schematic diagram of a circular cell composite structure provided in an embodiment of the present application;

4 is a schematic diagram of a square cell composite structure provided by an embodiment of the present application;

5 is a cross-sectional view of the active region of another MOSFET device with an integrated junction barrier Schottky provided in an embodiment of the present application;

6 is a schematic diagram of another regular hexagonal cell composite structure provided by the embodiment of the present application;

Description of reference numbers:

10. MOSFET device active region; 101, silicon carbide substrate; 102, epitaxial layer; 103, well region; 104, source region; 105, highly doped P-type region; 106, insulating gate oxide layer; 107, gate conductive polysilicon; 108, insulating dielectric layer; 109, first contact metal; 110, second contact metal; 111, source electrode; 112, drain electrode; 113, JFET region; 114, junction barrier Schottky region; 115, first PN junction; 116: second PN junction; 117, annular highly doped P-type region; 118, third PN junction.

Detailed ways

In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described The embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments of the present specification, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

The embodiment of the present application provides a MOSFET device with an integrated junction barrier Schottky. In the cell design, a composite structure in which the junction barrier Schottky cells and the MOSFET cells are arranged alternately is used, which is integrated in a MOSFET device, Therefore, it is not necessary to connect a Schottky diode in parallel outside the common MOSFET diode, which can reduce the size of the integrated chip and reduce the cost.

1 is a cross-sectional view of an active region of a MOSFET device with an integrated junction barrier Schottky provided by an embodiment of the present application. As shown in FIG. 1 , the MOSFET device 10 specifically includes: an epitaxial layer 102 , and a surface row of the epitaxial layer 102 Several MOSFET cells and junction barrier Schottky (Junction Barrier Schottky, JBS) cells of the cloth. The epitaxial layer 102 is an N-type semiconductor.

After extensive experiments, it has been found that MOSFET devices with circular and polygonal cell designs can achieve higher channel widths and higher Junction Field-Effect Transistor (JFET) area totals compared to strip-shaped cells. area, which in turn has a lower specific on-resistance. Therefore, the cell shape in this application can be designed as a regular polygon or a circle.

Taking a regular hexagon as an example, FIG. 2 is a schematic diagram of a regular hexagonal cell composite structure provided by an embodiment of the present application. As shown in FIG. 2 , the structure shown in cell 1 is a JBS cell, such as cell 2 The structure shown is a MOSFET cell. MOSFET cells and JBS cells are arranged in a certain proportion. MOSFET cells have the same shape as JBS cells, both are regular polygons or circles.

In one embodiment, the arrangement ratio of the MOSFET cells to the JBS cells is: a (1≤a≤100) MOSFET cells are arranged between every two adjacent JBS cells. The arrangement of cells shown in Figure 2 is a=1. As shown in Figure 2, a MOSFET cell is spaced between every two adjacent JBS cells. Therefore, a JBS cell is surrounded by around a circle of MOSFET cells.

As shown in FIG. 2 , each MOSFET cell includes a well region 103 , a source region 104 and a highly doped P-type region 105 , wherein the well region 103 is a P-type semiconductor, and the source region 104 is an N-type semiconductor. The shapes of the well region 103 , the source region 104 and the highly doped P-type region 105 are all regular hexagons, and the center points are coincident.

Further, the source region 104 is located inside the well region 103 , and the source region 104 surrounds the highly doped P-type region 105 . Fig. 1 is a cross-sectional view corresponding to the dotted line AA' in Fig. 2, and Fig. 5 is a cross-sectional view corresponding to the dotted line BB' in Fig. 2. It can be seen from FIG. 1 that the ion implantation depth of the source region 104 in the MOSFET cell is smaller than that of the well region 103 , and the lower half of the highly doped P-type region 105 is in contact with the well region 103 .

Further, a first PN junction 115 is formed at the interface between the well region 103 and the epitaxial layer 102 , and a second PN junction 116 is formed at the interface between the well region 103 and the source region 104 .

Further, each JBS cell is a junction barrier Schottky region 114 . Each junction barrier Schottky region 114 includes a multi-layer annular highly doped P-type region 117, and a Schottky region formed between each layer of the annular highly doped P-type region 117, the annular highly doped P-type region 117 The P-type region 117 and the epitaxial layer 102 form a third PN junction 118 .

A first JFET region is formed between the well region 103 of the MOSFET cell and the outer annular highly doped P-type region 117 of the adjacent JBS cell. A second JFET region is formed between the well region 103 of the MOSFET cell and the well region 103 of the adjacent MOSFET cells. The ion doping concentration of the first JFET region and the second JFET region is the same, which can be regarded as the same structure, as follows This is represented by the JFET region 113 .

In one embodiment, as shown in FIG. 2 , the JBS cell includes two layers of annular highly doped P-type regions 117 , and two layers of Schottky regions are formed between the two layers of annular highly doped P-type regions. The ion doping concentration of the well region 103 ranges from 5E15cm ^-3 to 5E18cm ^-3 . The ion doping concentration range of the source region 104 is 1E18cm ^-3 to 1E22cm ^-3 . The ion doping concentration range of the highly doped P-type region 105 and the annular highly doped P-type region 117 is 1E18 cm ⁻³ to 1E22 cm ⁻³ .

Further, the width n of the JFET region 113 and the ion implantation concentration need to ensure that the MOSFET has a small on-voltage drop, and in the blocking mode, the adjacent well regions can play an effective electric field shielding effect to ensure that the device reliability. Similarly, the ion implantation concentration of the Schottky regions between the various layers of annular highly doped P-type regions 117 in the junction barrier Schottky region 114, and the spacing s of the annular highly doped P-type regions 117 of each layer, It is necessary to ensure that the junction barrier Schottky diode has sufficient current conduction capability, and in the blocking mode, the adjacent well regions can play an effective electric field shielding effect to ensure the reliability of the MOSFET device. Therefore, in the design of the present application, the ion doping concentration of the Schottky region formed between the annular highly doped P-type regions 117 in the junction barrier Schottky region 114 and the JFET region 113 is greater than or equal to that of the epitaxial layer 102 . Ion doping concentration. The width n of the JFET region 113 and the spacing s of each ring-shaped highly doped P-type region 117 are both within the preset range. Experiments show that this design can make the MOSFET device have a smaller on-voltage drop, and the In blocking mode, adjacent well regions can effectively shield the electric field.

In one embodiment, the preset interval is specifically [0.8 μm˜5 μm]. The ion doping concentration range of the Schottky region formed between the annular highly doped P-type region 117 in the JFET region 113 and the junction barrier Schottky region 114 is 1E15cm ^-3 -5E17cm ^-3 .

Further, the MOSFET device 10 further includes a first contact metal 109 and a second contact metal 110 . As shown in FIG. 1 , the first contact metal covers the surface of the highly doped P-type region 105 to form an ohmic contact with the highly doped P-type region 105 . To suppress parasitic bipolar transistor effects inside the MOSFET device 10 , a portion of the first contact metal 109 is in contact with the source region 104 . The second contact metal covers the surface of the junction barrier Schottky region 114 and forms Schottky contact with several Schottky regions in the junction barrier Schottky region 114 .

If two pieces of contact metal are connected together, through appropriate contact metal design and high temperature annealing temperature, the two pieces of metal can form ohmic contact and Schottky contact at the same time, which can simplify the process flow, but the disadvantage is that in actual device production, It is not easy to form good ohmic and Schottky contacts at the same time, which may lead to increased failure rate and sacrifice of device yield. Therefore, as shown in FIG. 1 , a certain distance is maintained between the first contact metal 109 and the second contact metal 110 in this application, so that the two pieces of contact metal can be designed as ohmic contact and Schottky respectively through different processes Contact, reduce the manufacturing difficulty and failure rate of MOSFET devices.

Further, as shown in FIG. 1 , the source region 104 , the well region 103 and the JFET region 113 of the MOSFET cell are covered with an insulating gate oxide layer 106 , and the insulating gate oxide layer 106 starts from the source region 104 and terminates in the JFET region 113 . And the width of the insulating gate oxide layer 106 covering the JFET region 113 is greater than or equal to 0.1 μm, and smaller than the width of the JFET region 113 .

For example, if the width of the JFET region 113 is 3 μm, the value range of the width of the insulating gate oxide layer 106 covering the JFET region 113 is [0.1 μm˜3 μm].

Further, the gate insulating oxide layer 106 is covered with gate conductive polysilicon 107 . The insulating gate oxide layer 106 and the gate conductive polysilicon 107 are covered with an insulating dielectric layer 108. The insulating dielectric layer 108 insulates the gate oxide layer 106 and the gate conductive polysilicon 107 with the adjacent first contact metal 109 and second contact metal 108. Contact metal 110 is spaced apart.

Further, a source electrode 111 is covered on the insulating dielectric layer 108, the first contact metal 109 and the second contact metal 110, and the source electrode 111 is in contact with the first contact metal 109 and the second contact metal 110 of each cell. contact, and the insulating dielectric layer 108 completely separates the insulating gate oxide layer 106 and the gate conductive polysilicon 107 from the source electrode 111 .

Further, the side of the epitaxial layer 102 away from the cell side is covered with a silicon carbide substrate 101 . The side of the silicon carbide substrate 101 facing away from the epitaxial layer 102 is covered with the drain electrode 112 of the MOSFET device 10 .

In one embodiment, the ion doping concentration range of the silicon carbide substrate 101 is: 1E18 cm ^-3 -1E20 cm ^-3 , and the ion doping concentration range of the epitaxial layer 102 is: 1E14 cm ^-3 -5E16 cm ^-3 .

As a feasible implementation manner, in addition to regular hexagons, the cells in this application can also be designed as circles, squares, regular octagons, and the like. FIG. 3 is a schematic diagram of a circular cell composite structure provided by an embodiment of the present application. As shown in FIG. 3 , the shapes of the source region 104 and the highly doped P-type region 105 are both circular, and the centers of the circles coincide. The cross-sectional view corresponding to the dotted line AA' is shown in Fig. 1 , and the cross-sectional view corresponding to the dotted line BB' is shown in Fig. 5 . FIG. 4 is a schematic diagram of a compound structure of regular quadrilateral cells provided by an embodiment of the present application. As shown in FIG. 4 , each row of quadrilateral cells is aligned and arranged. The cross-sectional view corresponding to the dotted line AA' is shown in FIG. The cross-sectional view is shown in Figure 5.

As a feasible implementation manner, FIG. 6 is a schematic diagram of another regular hexagonal cell composite structure provided in the embodiment of the present application, and FIG. 6 shows the arrangement of cells in the case of a=2. The cross-sectional view corresponding to the dotted line AA' is shown in Fig. 1 , and the cross-sectional view corresponding to the dotted line BB' is shown in Fig. 5 .

A MOSFET device with an integrated junction barrier Schottky provided by the embodiment of the present application has a composite design of a polygonal or circular MOSFET cell and a JBS cell. The advantage of this composite structure is that the design flexibility is good, and the two The arrangement ratio of the seed cells is used to adjust the performance of the MOSFET device with the integrated junction barrier Schottky diode, which can better control the Schottky ratio, and at the same time, the MOSFET device does not need to be connected in parallel with an external Schottky diode. to reduce the size of the integrated chip.

Each embodiment in this application is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments.

The foregoing describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve desirable results. Additionally, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

The above descriptions are merely examples of the present application, and are not intended to limit the present application. For those skilled in the art, various modifications and variations can be made to the embodiments of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present application shall be included within the scope of the claims of the present application.

Claims (10)

1. a MOSFET device of integrated junction barrier Schottky, is characterized in that, described MOSFET device comprises: epitaxial layer, and several MOSFET cells and junction barrier Schottky JBS arranged on the surface of described epitaxial layer cell; the epitaxial layer is an N-type semiconductor; the MOSFET cell and the JBS cell are arranged according to a preset ratio; Each of the MOSFET cells includes a well region, a source region and a highly doped P-type region, the well region is a P-type semiconductor, and the source region is an N-type semiconductor; The source region is located inside the well region, and the source region surrounds the highly doped P-type region; wherein, the ion implantation depth of the source region is smaller than the ion implantation depth of the well region, the a highly doped P-type region is in contact with the well region; the well region and the epitaxial layer form a first PN junction, and the well region and the source region form a second PN junction; Each of the JBS cells includes multiple layers of annular highly doped P-type regions, and a Schottky region formed between each of the annular highly doped P-type regions; the annular highly doped P-type regions forming a third PN junction with the epitaxial layer; A first JFET region is formed between the well region of the MOSFET cell and the outer annular highly doped P-type region of the adjacent JBS cell; the well region of the MOSFET cell and the adjacent MOSFET cell forming a second JFET region between the well regions; The ion doping concentration of the first JFET region and the second JFET region is greater than or equal to the ion doping concentration of the epitaxial layer, the width of the first JFET region and the second JFET region and the ring-shaped high doping concentration of each layer The pitches of the hetero P-type regions are all within the same preset interval. 2 . The MOSFET device with integrated junction barrier Schottky according to claim 1 , wherein the MOSFET cell has the same shape as the JBS cell, and the shape is a regular polygon or a circle. 3 . ; Multiple MOSFET cells are arranged around a JBS cell; A MOSFET cells are arranged between two adjacent JBS cells; wherein, 1≤a≤100. 3. The MOSFET device with an integrated junction barrier Schottky according to claim 1, wherein the MOSFET device further comprises a first contact metal; The first contact metal covers the surface of the highly doped P-type region in the well region, and forms an ohmic contact with the highly doped P-type region in the well region; A portion of the first contact metal is in contact with the source region to suppress parasitic bipolar transistor effects inside the MOSFET device. 4. The MOSFET device with an integrated junction barrier Schottky according to claim 3, wherein the MOSFET device further comprises a second contact metal; The second contact metal covers the surface of the JBS cell, and forms Schottky contact with several Schottky regions in the JBS cell; A preset distance is maintained between the first contact metal and the second contact metal, so that through different processes, the first contact metal and the second contact metal are designed as ohmic contact and Schottky respectively touch. 5. The MOSFET device of an integrated junction barrier Schottky according to claim 1, wherein the MOSFET device further comprises an insulating gate oxide layer; the insulating gate oxide layer covers the source region, the well region and the JFET region; The width of the insulating gate oxide layer covering the JFET region is greater than or equal to 0.1 μm, and smaller than the width of the JFET region. 6 . The MOSFET device with integrated junction barrier Schottky according to claim 5 , wherein the gate insulating oxide layer is covered with gate conductive polysilicon. 7 . 7 . The MOSFET device with integrated junction barrier Schottky according to claim 6 , wherein the insulating gate oxide layer and the gate conductive polysilicon are covered with an insulating dielectric layer. 8 . 8 . The MOSFET device with integrated junction barrier Schottky according to claim 7 , wherein the insulating dielectric layer, the first contact metal and the second contact metal are covered with active pole electrode; the source electrode is in contact with the first contact metal and the second contact metal; The insulating dielectric layer separates the insulating gate oxide layer and the gate conductive polysilicon from the source electrode. 9 . The MOSFET device with integrated junction barrier Schottky according to claim 1 , wherein the MOSFET device further comprises: a silicon carbide substrate, and the silicon carbide substrate is located away from the epitaxial layer. 10 . the surface of the cell side; the silicon carbide substrate is an N-type semiconductor; The ion doping concentration in the silicon carbide substrate is higher than the ion doping concentration in the epitaxial layer; The side of the silicon carbide substrate facing away from the epitaxial layer is covered with the drain electrode of the MOSFET device. 10 . The MOSFET device with integrated junction barrier Schottky according to claim 1 , wherein the preset interval is [0.8 μm˜5 μm]. 11 .

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