CN114389574A - Frequency response masking filter system and method of generation - Google Patents

Abstract

The present application provides a frequency response shielded FRM filter system and a generation method, the system includes: a controller, a storage array and an FRM filter assembly; wherein one end of the controller is connected to the signal input end, and the other end is connected to the control of the storage array The configuration end of the FRM filter assembly is connected to the output end of the storage array, the input end of the FRM filter assembly is connected to the signal input end, and the output end of the FRM filter assembly is used to output the signal processed by the FRM; the controller , which is configured to retrieve target parameters corresponding to the current working bandwidth from the storage array, and send them to the FRM filter component, so as to generate an FRM filter matching the current working bandwidth according to the target parameters. Therefore, through this FRM filter system, FRM filter chain multiplexing of multi-bandwidth cells is realized, and resource occupation is reduced.

Description

Frequency response shielding filter system and generating method

technical field

The present application relates to the field of mobile communication technologies, and in particular, to a frequency-response-masking (Frequency-Response-Masking, FRM for short) filter system and a generation method.

Background technique

The Active Antenna Unit (AAU) is different from the RRU and antenna separation scheme in the 4G era. AAU integrates the antenna with the RRU and is a key device for 5G.

In the related art, under the condition that a cell needs multiple bandwidth configurations, AAU products need to support the working modes of the carrier under different bandwidth configurations. However, under different bandwidth configurations, the carrier needs to switch FRM filters with different coefficients, and the resource occupation is high. .

SUMMARY OF THE INVENTION

The FRM filter system and generation method proposed in the present application are used to solve the problem in the related art that under the condition that a cell requires multiple bandwidth configurations, the AAU needs to switch FRM filters with different coefficients under different bandwidth configurations of the carrier, and the resource occupation high question.

An FRM filter system proposed by an embodiment of the present application includes: a controller, a storage array, and a frequency response shielding FRM filter assembly; wherein one end of the controller is connected to a signal input end, and the other end is connected to the storage array The control end is connected; the configuration end of the FRM filter assembly is connected with the output end of the storage array, the input end of the FRM filter assembly is connected with the signal input end, the output end of the FRM filter assembly for outputting the signal processed by the FRM; the controller is configured to retrieve target parameters corresponding to the current working bandwidth from the storage array, so that the storage array sends the target parameters to the The FRM filter component; the FRM filter component is configured to generate an FRM filter matching the current operating bandwidth according to the target parameter.

Optionally, in a possible implementation manner of the embodiment of the first aspect of the present application, the FRM filter component includes: a first shift register, a first digital signal processor DSP array, a second DSP array, a first shift register Three DSP arrays, adders and subtractors;

The configuration end of the first shift register, the configuration end of the first DSP array, the configuration end of the second DSP array, and the configuration end of the third DSP array are respectively connected with each output end of the storage array;

The input end of the first DSP array and the input end of the first shift register are connected to the signal input end, and the output end of the first DSP array is respectively connected to the input end of the second DSP array, and the first input of the subtractor is connected;

The output end of the second DSP array is connected with the first input end of the adder;

The output end of the first shift register is connected to the second input end of the subtractor;

The output end of the subtractor is connected with the input end of the third DSP array;

The output end of the third DSP array is connected with the second input end of the adder;

The adder is configured to output the processed signal.

Optionally, in another possible implementation manner of the embodiment of the first aspect of the present application, the first DSP array includes M1 first DSPs connected in sequence and connected end to end, where M1 is N1/2 upward the value obtained by rounding;

The second DSP array includes M2 second DSPs connected in sequence and connected end to end, wherein M2 is a value obtained by rounding up N2/2;

The third DSP array includes M3 third DSPs connected in sequence and connected end to end, wherein M3 is a value obtained by rounding up N3/2;

Wherein, N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first mask filter in each FRM filter corresponding to the system, and N3 is the The highest order of the second mask filter in each FRM filter corresponding to the system.

Optionally, in another possible implementation manner of the embodiment of the first aspect of the present application, the system further includes: 2 (M1-1) second shift registers connected in sequence;

Wherein, the input end of the first second shift register is connected with the signal input end;

The configuration terminal of each of the second shift registers is connected to the output terminal of the memory used for storing the first delay parameter in the storage array, and the output terminal of the i-th second shift register, the The output terminals of the 2(M1-1)-(i-1) second shift registers are respectively connected to an input terminal of the i+1th first DSP, where i is greater than 0 and less than or equal to M1 A positive integer of -1.

Optionally, in another possible implementation manner of the embodiment of the first aspect of the present application, the storage array includes K memories, where K=M1+M2+M3+2, wherein M1 memories, respectively is configured to store parameters corresponding to M1 first DSPs; M2 memories are respectively configured to store parameters corresponding to M2 second DSPs; M3 memories are respectively configured to store parameters corresponding to M3 third DSPs, one The memory is configured to store the second delay parameter corresponding to the first shift register, and the other memory is configured to store the first delay parameter corresponding to the M1-1 second shift registers.

Optionally, in another possible implementation manner of the embodiment of the first aspect of the present application, the system corresponds to L types of working bandwidths, and each of the memories stores L types of working bandwidths corresponding to the L types of working bandwidths respectively. parameter.

The method for generating an FRM filter proposed by another embodiment of the present application includes: acquiring the current working bandwidth of the system; reading target parameters corresponding to the current working bandwidth from a storage array; sending the target parameters to the FRM A filter component to generate an FRM filter that matches the current operating bandwidth.

Optionally, in a possible implementation manner of the embodiment of the second aspect of the present application, the reading the target parameter corresponding to the current working bandwidth from the storage array includes:

Obtain the corresponding relationship between each parameter and bandwidth in each memory of the storage array;

Determine the target address corresponding to the current working bandwidth according to the corresponding relationship between the parameters and the bandwidth and the positions of the parameters in the memory;

The target parameter corresponding to the target address is read from the storage array.

Optionally, in another possible implementation manner of the embodiment of the second aspect of the present application, the order of the interpolation prototype filter in the FRM filter corresponding to the current working bandwidth is N1, and the The corresponding relationship between the parameters and the bandwidth and the position of each parameter in the memory, determine the target address corresponding to the current working bandwidth, including:

Determine the M1 memories corresponding to the N1-order interpolation prototype filters, wherein M1 is a value obtained by rounding up N1/2;

M1 target addresses corresponding to the current working bandwidth are determined according to the corresponding relationship between each parameter and the bandwidth in each of the memories and the position of each parameter in the memory.

Optionally, in another possible implementation manner of the embodiment of the second aspect of the present application, the FRM filter component includes a first DSP array, a first shift register, a second DSP array, and a third DSP array, The target parameters include filter parameters, second delay parameters, first mask parameters and second mask parameters, and the sending of the target parameters to the FRM filter component includes:

sending the filtering parameters to the first DSP array;

sending the second delay parameter to the first shift register;

sending the first mask parameter to the second DSP array;

The second mask parameter is sent to the third DSP array.

Optionally, in another possible implementation manner of the embodiment of the second aspect of the present application, the FRM filter component further includes 2 (M1-1) second shift registers connected in sequence, and the target parameter Also includes a first delay parameter, and the described target parameter is sent to the FRM filter component, including:

Send the first delay parameter to the 2 (M1-1) second shift registers respectively, where M1 is the value obtained by rounding up N1/2, and N1 is the corresponding value of the FRM filter component The highest order of the interpolated prototype filter in each FRM filter of .

In the FRM filter system and generation method provided by the embodiments of the present application, target parameters corresponding to each working bandwidth are stored in a storage array, and target parameters corresponding to the current working bandwidth are retrieved from the storage array through a controller, and sent to the FRM A filter component, so that the FRM filter component generates an FRM filter matching the current operating bandwidth according to the target parameter. Therefore, by storing the target parameters corresponding to each working bandwidth in the storage array in advance, the FRM filter assembly can be adjusted by retrieving the target parameters from the storage assembly according to the actual working bandwidth. By switching between filter modules, only one FRM filter module can support working modes corresponding to multiple working bandwidths, which realizes FRM filter chain multiplexing in multi-bandwidth cells and reduces resource occupancy.

Additional aspects and advantages of the present application will be set forth, in part, in the following description, and in part will be apparent from the following description, or learned by practice of the present application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

1 is a schematic structural diagram of a FRM filter system provided by an embodiment of the application;

2 is a schematic structural diagram of another FRM filter system provided by an embodiment of the application;

3 is a schematic structural diagram of yet another FRM filter system provided by an embodiment of the application;

4 is a schematic structural diagram of another FRM filter system provided by an embodiment of the application;

5 is a schematic flowchart of a method for generating an FRM filter provided by an embodiment of the present application;

FIG. 6 is a schematic flowchart of another method for generating an FRM filter provided by an embodiment of the present application.

Detailed ways

The term "and/or" in the embodiments of the present application describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and/or B can indicate that A exists alone, A and B exist simultaneously, and B exists alone these three situations. The character "/" generally indicates that the associated objects are an "or" relationship.

In the embodiments of the present application, the term "plurality" refers to two or more than two, and other quantifiers are similar.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

The embodiments of the present application provide an FRM filter system and a generation method, which are used in the related art, under the condition that a cell needs multiple bandwidth configurations, the AAU needs to switch FRM filters with different coefficients under different bandwidth configurations of the carrier, The problem of high resource usage.

The method and the device are conceived based on the same application. Since the principles of the method and the device for solving the problem are similar, the implementation of the device and the method can be referred to each other, and repeated descriptions will not be repeated here.

In the FRM filter system provided by the embodiments of the present application, the target parameters corresponding to each working bandwidth are stored in the storage array, and the target parameters corresponding to the current working bandwidth are retrieved from the storage array through the controller, and sent to the FRM filter component , so that the FRM filter component generates an FRM filter that matches the current operating bandwidth according to the target parameters. Therefore, by storing the target parameters corresponding to each working bandwidth in the storage array in advance, the FRM filter assembly can be adjusted by retrieving the target parameters from the storage assembly according to the actual working bandwidth. By switching between filter modules, only one FRM filter module can support working modes corresponding to multiple working bandwidths, which realizes FRM filter chain multiplexing in multi-bandwidth cells and reduces resource occupancy.

The FRM filter system and generation method provided by the present application will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of an FRM filter system provided by an embodiment of the present application.

As shown in FIG. 1 , the FRM filter system 100 includes: a controller 110 , a storage array 120 and an FRM filter component 130 .

One end of the controller 110 is connected to the signal input end, and the other end is connected to the control end of the storage array 120;

The configuration end of the FRM filter assembly 130 is connected with the output end of the storage array 120, the input end of the FRM filter assembly 130 is connected with the signal input end, and the output end of the FRM filter assembly 130 is used to output the signal processed by the FRM;

The controller 110 is configured to retrieve the target parameter corresponding to the current working bandwidth from the storage array 120, so that the storage array 120 sends the target parameter to the FRM filter component 130;

The FRM filter component 130 is configured to generate an FRM filter matching the current operating bandwidth according to the target parameter.

The controller 110 refers to a component that can instruct each component in the system to work in coordination according to the functional requirements of the instruction. For example, the controller 110 may be a CPU, GPU, or other processor with a relatively complex structure and strong computing capability, or may be an MCU with a relatively simple structure and a lower computing capability, etc., which is not limited in this embodiment of the present application.

The storage array 120 may be any storage medium composed of a large number of storage units and having functions of writing and reading. For example, memory array 120 may be a ROM.

The FRM filter component 130 refers to a filter module with FRM filtering function, and may be composed of multiple filters. In actual use, an appropriate FRM filter assembly 130 may be designed according to actual needs, which is not limited in this embodiment of the present application.

In the embodiment of the present application, the FRM filter system 100 in the embodiment of the present application may perform filtering processing on the input signal to generate a filtered signal. However, since the performance and parameters of the filters required by input signals of different bandwidths are different, the filter parameters corresponding to each working bandwidth can be determined according to all possible working bandwidths in the actual application scenario, and stored in the storage array 120 respectively. .

In this embodiment of the present application, one end of the controller 110 is connected to the signal input end, so that when the controller 110 obtains the signal input from the signal input end, it can determine the current working bandwidth according to the obtained signal; after that, the controller 110 may retrieve the target parameter corresponding to the current working bandwidth from the storage array 120 according to the corresponding relationship between the working bandwidth and the filter parameter. After the target parameters are determined, the target parameters can be sent to the FRM filter component 130 through the storage array 120, so that the FRM filter component 130 can switch the internal parameters to the target parameters to generate an FRM filter matching the current operating bandwidth and use the generated FRM filter that matches the current working bandwidth to filter the signal input to the FRM filter component 130 to output the FRM-processed signal.

As a possible implementation manner, the filter parameters corresponding to the respective working bandwidths may be determined first according to the specific characteristics of the respective working bandwidths, and the corresponding relationship between the bandwidths and the filter parameters may be stored in the storage array 120 . Therefore, after determining the current working bandwidth, the controller 110 can obtain the corresponding relationship between the parameters and the bandwidth in each memory of the storage array 120 from the storage array 120, and then can determine the current working bandwidth according to the corresponding relationship between the parameters and the bandwidth. The target parameter corresponding to the working bandwidth, and then determine the position of the target parameter in the memory according to the position of each parameter in the memory, and determine the position of the target parameter in the memory as the target address corresponding to the current working bandwidth, from the storage array 120 Read the target parameter corresponding to the target address.

In the FRM filter system provided by the embodiments of the present application, the target parameters corresponding to each working bandwidth are stored in the storage array, and the target parameters corresponding to the current working bandwidth are retrieved from the storage array through the controller, and sent to the FRM filter component , so that the FRM filter component generates an FRM filter that matches the current operating bandwidth according to the target parameters. Therefore, by storing the target parameters corresponding to each working bandwidth in the storage array in advance, the FRM filter assembly can be adjusted by retrieving the target parameters from the storage assembly according to the actual working bandwidth. By switching between filter modules, only one FRM filter module can support working modes corresponding to multiple working bandwidths, which realizes FRM filter chain multiplexing in multi-bandwidth cells and reduces resource occupancy.

In a possible implementation form of the present application, the FRM filter assembly may be designed by complementary filters and shielding filters, so as to further reduce the computational complexity of the design of the FRM filter assembly.

The FRM filter system provided by the embodiment of the present application will be further described below with reference to FIG. 2 .

FIG. 2 is a schematic structural diagram of another FRM filter system provided by an embodiment of the present application.

As shown in FIG. 2, based on the embodiment shown in FIG. 1, the FRM filter component 130 may include: a first shift register 131, a first digital signal processor (Digital Signal Processor, DSP for short) array 132, The second DSP array 133, the third DSP array 134, the adder 135 and the subtractor 136;

Wherein, the configuration end of the first shift register 131, the configuration end of the first DSP array 132, the configuration end of the second DSP array 133 and the configuration end of the third DSP array 134 are respectively connected to the respective output ends of the storage array 120;

The input end of the first DSP array 132 and the input end of the first shift register 131 are connected to the signal input end, the output end of the first DSP array 132 is respectively connected to the input end of the second DSP array 133 and the first end of the subtractor 136 input connection;

The output end of the second DSP array 133 is connected to the first input end of the adder 135;

The output end of the first shift register 131 is connected to the second input end of the subtractor 136;

The output end of the subtractor 136 is connected with the input end of the third DSP array 134;

The output end of the third DSP array 134 is connected to the second input end of the adder 135;

The adder 135 is configured to output the processed signal.

In this embodiment of the present application, the first DSP array 132 may be an interpolation prototype filter, and the second DSP array 133 and the third DSP array 134 may be masking filters. The first shift register 131 and the subtractor 136 can be used to determine the interpolation complementary prototype filter corresponding to the interpolation prototype filter according to the signal input at the signal input terminal and the output of the first DSP array 132 (ie, the interpolation prototype filter). output of the device.

It should be noted that the FRM filter assembly 130 may be implemented by a pair of complementary filters, so as to reduce the number of DSPs in the FRM filter assembly 130 and reduce the hardware complexity of the FRM filter assembly 130 . Among them, if the frequency responses of the two linear phase filters _{Ha and H c satisfy} |H _a (e ^jw )+H _c (e ^jw )|=1, they are called complementary filters, where H _a (e ^jw ) is the frequency response of the linear phase filter Ha, and H _c (e ^jw _{) is the frequency response of the linear phase filter H c .} The frequency response is transferred to the Z domain, |H _a (z)+H _c (z)|=z ^-(N-1)*M/2 , where N is the length of the linear phase filter and M is the interpolation factor. It can be seen that, for a pair of complementary filters, the output of the linear phase filter H _c can be obtained by subtracting the output of the linear phase filter H _a from the delayed form of the input signal.

Therefore, in this embodiment of the present application, the first shift register 131 and the subtractor 136 may be introduced into the FRM filter assembly 130, the input end of the first shift register 131 is connected to the signal input end, and the first shift register 131 is connected to the signal input end. The output end of the shift register 131 is connected to the second input end of the subtractor 136, so that the input signal can be delayed by the first shift register 131 to generate a delayed form of the input signal and input to the subtractor 136; The output end of a DSP array 132 is connected to the first input end of the subtractor 136 , and the subtractor 136 performs a subtraction operation on the delayed form of the output of the first DSP array 132 and the input signal to generate the first DSP array 132 The output of the corresponding interpolated complementary prototype filter.

In the embodiment of the present application, as shown in FIG. 2 , the FRM filter assembly 130 includes two branches, and the upper branch consists of a first DSP array 132 (ie, the interpolation prototype filter) and a second DSP array 133 (ie, the first DSP array 133 ). The lower branch is composed of the first shift register 131 and the subtractor (ie, the interpolation complementary prototype filter) and the third DSP array 134 (the second mask filter). The function of the second DSP array 133 is to select the required frequency components from the output of the first DSP array 132 (ie, the interpolation prototype filter); the function of the third DSP array 134 is to select the required frequency components from the output of the subtractor 136 (ie Interpolate the complementary prototype filter) to select the desired frequency components. Then, the output of the second DSP array 133 and the output of the third DSP array 134 are added by the adder 135 to generate an output-processed signal.

It should be noted that the second DSP array 133 and the third DSP array 134 need to have the same group delay, so that when the outputs of the two are added by the adder 135, the two can be properly supplemented within the passband. When the parameters of the second DSP array 133 and the third DSP array 134 are inconsistent, a little delay needs to be added before and after to equalize their group delay characteristics.

In this embodiment of the present application, since the first shift register 131 , the first DSP array 132 , the second DSP array 133 and the third DSP array 134 all have their own parameters, the first shift register 131 , the first The configuration terminals of the DSP array 132 , the second DSP array 133 and the third DSP array 134 are all connected to the output terminal of the storage array 120 , so that the storage array 120 converts the first shift register 131 and the first DSP array included in the target parameter 132. The parameters corresponding to the second DSP array 133 and the third DSP array 134 are respectively passed to the first shift register 131, the first DSP array 132, the second DSP array 133 and the third DSP array 134, so that the first shift The bit register 131, the first DSP array 132, the second DSP array 133 and the third DSP array 134 adjust the internal parameters according to their respective parameters to generate an FRM filter matching the current working bandwidth, and then pass the generated FRM filter. The signal input to the system at the signal input terminal is processed to generate a processed signal.

Further, since both the interpolation prototype filter and the mask filter can be composed of multiple DSPs, and the DSPs in symmetrical positions can be reused, the number of DSPs can be reduced, and the hardware complexity of the FRM filter component can be further reduced. That is, in a possible implementation form of the embodiment of the present application, as shown in FIG. 3 , on the basis of the embodiment shown in FIG. 2 , the above-mentioned first DSP array 132 may include M1 sequentially connected and end-to-end connected A DSP (1321), wherein M1 is a value obtained by rounding up N1/2; the second DSP array 133 includes M2 second DSPs (not shown in the figure) that are connected in sequence and end-to-end, wherein M2 is the value obtained by rounding up N2/2; the third DSP array 134 includes M3 third DSPs (not shown in the figure) that are sequentially connected and connected end to end, wherein M3 is obtained by rounding up N3/2 value; wherein, N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first mask filter in each FRM filter corresponding to the system, and N3 is each corresponding to the system. The highest order of the second mask filter in the FRM filter.

It should be noted that when the cells work in different bandwidths, the order of each FRM filter in the system may be different, so the maximum order of the FRM filter under different bandwidths can be determined as the highest value of the FRM filter. Order. For example, for a cell that can work in three bandwidths of 60M, 80M and 100M, when the cell operates in three bandwidths of 60M, 80M and 100M, the corresponding orders of the interpolation prototype filter are 29, 39, and 39 respectively, so that the Determine the highest order N1=39 of the interpolation prototype filter.

In the embodiment of the present application, since the parameters of each first DSP (1321) in the first DSP array 132 are set symmetrically, and the symmetrical parameters can be multiplexed with the same DSP, the highest order of the filter prototype can be interpolated according to the highest order. 1/2 to determine the number of first DSPs ( 1321 ) included in the first DSP array 132 . For example, if the highest order of the interpolation prototype filter is N1=39, then M1=19, that is, the first DSP array 132 includes 19 first DSPs (1321) connected in sequence and end-to-end. Correspondingly, the values of M2 and M3 can also be determined in the same manner as described above, which will not be repeated here; The connection mode of the three DSPs is the same as the connection mode of the first DSP ( 1321 ) in the first DSP array 132 , so it is not shown in FIG. 3 .

Further, because the interpolation factor M is different, the delays between the DSPs in the interpolation prototype filter are also different, so the delay parameters can be transferred to the first DSPs through different delay registers, so as to adjust the first DSP. DSP array 132 performs group delay processing. That is, in a possible implementation form of the embodiment of the present application, as shown in FIG. 4 , on the basis of the embodiment shown in FIG. 3 , the above-mentioned FRM filter system 100 may further include: 2 (M1-1 ) a second shift register 140;

Wherein, the input end of the first second shift register is connected with the signal input end;

The configuration end of each second shift register 140 is connected to the output end of the memory for storing the first delay parameter in the storage array 120, and the output end of the i-th second shift register 140, the second (M1) The outputs of the -1)-(i-1) second shift registers 140 are respectively connected to one input of the i+1-th first DSP (1321), where i is greater than 0 and less than or equal to M1- A positive integer of 1.

As a possible implementation manner, since symmetrical delay parameters can reuse the same DSP to reduce the number of DSPs, the outputs of the two second shift registers 140 with symmetrical delay parameters can be combined with the same first The input end of a DSP (1321) is connected to realize the multiplexing of the DSP.

For example, if N1=39, then M1=19, and the number of the second shift registers 140 is 36. Since the first first DSP (1321) does not need to perform delay, the first and second shift registers can be The output terminals of the 36 second shift registers 140 are connected to an input terminal of the second first DSP (1321); the output terminals of the second and 35th second shift registers 140 are connected to the third first One input of the DSP (1321) is connected; the outputs of the 3rd and 34th second shift registers 140 are connected to one input of the 4th first DSP (1321), and so on.

In this embodiment of the present application, the delay parameters between the first DSPs (1321) in the first DSP array 132 can be determined according to the interpolation factor of the interpolation prototype filter, and stored in the memory of the storage array 120, Therefore, when the controller 110 obtains the signal input from the signal input terminal, it can retrieve the delay parameters from the memory storing the delay parameters, and send them to the second shift registers 140 through the storage array 120 respectively, and then pass the delay parameters to the second shift registers 140 respectively. The second shift register 140 performs delay processing on the signal input from the signal input terminal, and then each second shift register 140 sends the delayed processed signal to the first DSP (1321) connected to it.

It should be noted that the method of retrieving the delay parameter from the storage array 120 is the same as the method of retrieving the target parameter from the storage array 120 . The specific implementation process and principle can refer to the detailed description of the above embodiment, which is not repeated here. Repeat.

Further, different memories in the storage array 120 can be used to store parameters of different DSPs, so as to improve the reading speed of data. That is, in a possible implementation manner of the embodiment of the present application, the storage array 120 may include K memories, where K=M1+M2+M3+2, wherein the M1 memories are respectively configured to store M1 th memories Parameters corresponding to one DSP; M2 memories, respectively configured to store parameters corresponding to M2 second DSPs; M3 memories, respectively configured to store parameters corresponding to M3 third DSPs, and one memory configured to store the first The second delay parameter corresponding to the shift register, and the other memory is configured to store the first delay parameter corresponding to the M1-1 second shift registers.

In this embodiment of the present application, a memory in the storage array 120 can store parameters corresponding to one DSP, so that the parameters corresponding to each DSP can be directly read from the memory according to the location or address information of the memory, thereby improving the data reading speed. Therefore, assuming that the first DSP ( 1321 ), the second DSP and the third DSP are all 19, that is, M1=M2=M3=19, it can be determined that the memory array 120 can contain 59 memories. Among them, 19 memories are used to store the parameters corresponding to the 19 first DSPs (1321) respectively, 19 memories are used to store the parameters corresponding to the 19 second DSPs respectively, and 19 memories are used to store the corresponding parameters of the 19 third DSPs respectively. In addition, for the remaining two memories, one memory is used to store the second delay parameter corresponding to the first shift register 131, and the other memory is used to store the first delay corresponding to each second shift register 140. parameter.

Further, since the parameters corresponding to each DSP may be different when there are multiple working bandwidths of a cell, multiple parameters corresponding to one DSP can be stored in one memory. That is, in a possible implementation form of the embodiment of the present application, the above-mentioned FRM filter system 100 corresponds to L kinds of working bandwidths, and each memory stores L kinds of parameters corresponding to the L kinds of working bandwidths respectively.

For example, if the FRM filter system 100 is applied in a cell that can operate in three bandwidths of 60M, 80M and 100M, the FRM filter system 100 corresponds to three operating bandwidths, so it can be pre-calculated that under the three operating bandwidths, The three parameters corresponding to each DSP in the FRM filter component 130 are further stored in the same memory.

In the FRM filter system provided by the embodiments of the present application, the target parameters corresponding to each working bandwidth are stored in the storage array, and the target parameters corresponding to the current working bandwidth are retrieved from the storage array through the controller, and sent to the FRM filter component , so that the FRM filter assembly generates an FRM filter matching the current working bandwidth according to the target parameters; and, design the FRM filter assembly through complementary filters and shielding filters, and multiplex DSP through symmetrical parameters, and then utilize the storage array. One memory in the DSP stores the parameters corresponding to a DSP, which not only realizes the multiplexing of FRM filter links in multi-bandwidth cells, reduces the resource occupation, but also further reduces the number of DSPs and reduces the hardware complexity of the FRM filter. , which improves the data reading speed.

In order to realize the above embodiments, the present application also proposes a method for generating an FRM filter.

FIG. 5 is a schematic flowchart of a method for generating an FRM filter provided by an embodiment of the present application.

As shown in Figure 5, the FRM filter generation method includes the following steps:

Step 101: Obtain the current working bandwidth of the system.

It should be noted that the system may be the FRM filter system in the above embodiment, and the FRM filter system in the embodiment of the present application may perform filtering processing on an input signal to generate a filtered signal. However, due to the different performances and parameters of the filters required by input signals of different bandwidths, the filter parameters corresponding to each operating bandwidth can be determined according to all possible operating bandwidths in the actual application scenario, and stored in the FRM filter system respectively. in the storage array.

In the embodiment of the present application, one end of the controller of the FRM filter system may be connected to the signal input end, so that when the controller obtains the signal input from the signal input end, the current operating bandwidth can be determined according to the obtained signal.

Step 102: Read target parameters corresponding to the current working bandwidth from the storage array.

In the embodiment of the present application, after the current working bandwidth is determined by the controller, the target parameters corresponding to the current working bandwidth can be retrieved from the storage array according to the corresponding relationship between the working bandwidth and the filter parameters.

As a possible implementation manner, the above step 102 may include:

Obtain the corresponding relationship between each parameter and bandwidth in each memory of the storage array;

Determine the target address corresponding to the current working bandwidth according to the corresponding relationship between each parameter and the bandwidth and the position of each parameter in the memory;

Read the target parameter corresponding to the target address from the storage array.

As a possible implementation manner, the filter parameters corresponding to the respective working bandwidths may be determined first according to the specific characteristics of the respective working bandwidths, and the corresponding relationship between the bandwidths and the filter parameters may be stored in the storage array. Therefore, after the current working bandwidth is determined, the corresponding relationship between the parameters and the bandwidth in each memory of the storage array can be obtained from the storage array, and then the target corresponding to the current working bandwidth can be determined according to the corresponding relationship between the parameters and the bandwidth. parameters, and then determine the position of the target parameter in the memory according to the position of each parameter in the memory, and determine the position of the target parameter in the memory as the target address corresponding to the current working bandwidth, so as to read the target address from the storage array. The target parameter corresponding to the address.

Further, since each FRM filter in the FRM filter system can include multiple DSPs, and the parameters corresponding to each DSP can be stored in a memory, the memory corresponding to each FRM filter can be determined first, The specific address of each parameter corresponding to the FRM filter is further determined. That is, in a possible implementation form of the embodiment of the present application, the order of the interpolation prototype filter in the FRM filter corresponding to the above-mentioned current working bandwidth is N1. The location of the parameter in the memory determines the target address corresponding to the current working bandwidth, which can include:

Determine the M1 memories corresponding to the N1-order interpolation prototype filters, where M1 is the value obtained by rounding up N1/2;

M target addresses corresponding to the current working bandwidth are determined according to the corresponding relationship between each parameter and the bandwidth in each memory and the position of each parameter in the memory.

In this embodiment of the present application, since the FRM filter system may include an interpolation prototype filter and two masking filters, and both the interpolation prototype filter and the two masking filters may include multiple DSPs, the storage array A memory can be used to store the parameters corresponding to a DSP to improve the data reading speed. Therefore, each memory corresponding to each filter can be sequentially determined, and then each address corresponding to the MiG filter can be determined from the position of the memory corresponding to each filter in the storage array. The interpolation prototype filter will be described in detail below.

In this embodiment of the present application, the order of the interpolation prototype filter may determine the number of parameters and the number of DSPs corresponding to the interpolation prototype filter. For example, the number of DSPs corresponding to the N-order interpolation prototype filter can be M1, and correspondingly, the number of parameters is also M1. Therefore, it can be first determined that the M1 memories corresponding to the N-order interpolation prototype filter are stored in the storage array. Then, according to the corresponding relationship between the parameters and the working bandwidth, determine the M1 target parameters corresponding to the current working bandwidth; and then according to the position of each parameter in the M1 memory in the memory, determine the M1 target parameters are respectively in M1 locations in the memory, that is, M1 target addresses corresponding to the current working bandwidth.

It should be noted that the method of determining the target address of the parameters corresponding to other filters in the system is the same as the above method, and will not be repeated here.

Step 103: Send the target parameters to the FRM filter component to generate an FRM filter matching the current working bandwidth.

In this embodiment of the present application, after the target parameter is determined by the controller, the target parameter can be sent to the FRM filter component in the system through the storage array, so that the FRM filter component can switch the internal parameter to the target parameter to generate an FRM filter matching the current working bandwidth; and using the generated FRM filter matching the current working bandwidth to filter the signal input to the FRM filter component to output the FRM-processed signal.

In the method for generating an FRM filter provided by the embodiment of the present application, target parameters corresponding to each working bandwidth are stored in a storage array, and target parameters corresponding to the current working bandwidth are retrieved from the storage array through a controller, and sent to the FRM filter component, so that the FRM filter component generates an FRM filter that matches the current operating bandwidth according to the target parameters. Therefore, by storing the target parameters corresponding to each working bandwidth in the storage array in advance, the FRM filter assembly can be adjusted by retrieving the target parameters from the storage assembly according to the actual working bandwidth. By switching between filter modules, only one FRM filter module can support working modes corresponding to multiple working bandwidths, which realizes FRM filter chain multiplexing in multi-bandwidth cells and reduces resource occupancy.

In a possible implementation form of the present application, since the FRM filter component may include multiple filters, parameters corresponding to each filter may be sent to each filter respectively, so as to improve the efficiency and accuracy of parameter transfer.

The method for generating the FRM filter provided by the embodiment of the present application will be further described below with reference to FIG. 6 .

FIG. 6 is a schematic flowchart of another method for generating an FRM filter provided by an embodiment of the present application.

As shown in Figure 6, the FRM filter generation method includes the following steps:

Step 201: Obtain the current working bandwidth of the system.

For the specific implementation process and principle of the foregoing step 201, reference may be made to the detailed description of the foregoing embodiment, and details are not described herein again.

Step 202: Read target parameters corresponding to the current working bandwidth from the storage array, wherein the target parameters include filter parameters, second delay parameters, first mask parameters and second mask parameters.

In this embodiment of the present application, the FRM filter component may include a first DSP array, a first shift register, a second DSP array, and a third DSP array, so the target parameters may include filter parameters corresponding to the first DSP array, The second delay parameter corresponding to the first shift register, the first mask parameter corresponding to the second DSP array, and the second mask parameter corresponding to the third DSP array.

For other specific implementation processes and principles of the foregoing step 202, reference may be made to the detailed descriptions of the foregoing embodiments, and details are not described herein again.

Step 203: Send the filtering parameters to the first DSP array.

In this embodiment of the present application, since the first shift register, the first DSP array, the second DSP array and the third DSP array all have their own parameters, the first shift register, the first DSP array, the second DSP array and the second The configuration terminals of the DSP array and the third DSP array are both connected to the output terminal of the storage array, so that the storage array transmits the filtering parameters, the second delay parameters, the first masking parameters and the second masking parameters included in the target parameters, respectively. for the first DSP array, the first shift register, the second DSP array and the third DSP array, so that the first DSP array, the first shift register, the second DSP array and the third DSP array are adjusted according to their respective parameters Internal parameters are used to generate an FRM filter that matches the current working bandwidth, and then the generated FRM filter is used to process the signal input to the system at the signal input end to generate a processed signal.

Further, since both the interpolation prototype filter and the mask filter can be composed of multiple DSPs, and the DSPs in symmetrical positions can be reused, the number of DSPs can be reduced, and the hardware complexity of the FRM filter component can be further reduced. That is, in a possible implementation form of the embodiment of the present application, the above-mentioned FRM filter assembly may further include 2 (M1-1) second shift registers connected in sequence, and the target parameter may further include a first delay parameter ; Correspondingly, the above step 203 may include:

Send the first delay parameter to 2 (M1-1) second shift registers respectively, where M1 is the value obtained by rounding up N1/2, and N1 is the value of each FRM filter corresponding to the FRM filter component. The highest order of the interpolation prototype filter.

In the embodiment of the present application, because the interpolation factor M is different, the delays between the DSPs in the interpolation prototype filter are also different, so that the delay parameters can be transferred to the first DSPs through different delay registers, respectively. To perform group delay processing on the first DSP array 132 .

As a possible implementation, since the symmetrical delay parameters can reuse the same DSP to reduce the number of DSPs, the outputs of the two second shift registers with symmetrical delay parameters can be combined with the first DSP array. The input end of the same first DSP is connected to realize the multiplexing of the DSP.

For example, if N1=39, then M1=19, and the number of second shift registers is 36. Since the first first DSP does not need to delay, the first and 36th second shift registers can be shifted The output end of the bit register is connected to an input end of the second first DSP; the output end of the second and 35th second shift registers is connected to an input end of the third first DSP; the third The output of the 34th second shift register is connected to one input of the 4th first DSP, and so on.

In this embodiment of the present application, the delay parameters between the first DSPs in the first DSP array may be determined according to the interpolation factor of the interpolation prototype filter, and stored in the memory of the storage array, so that the When the signal input from the signal input terminal is obtained, the delay parameter is retrieved from the memory storing the delay parameter, and sent to each second shift register through the storage array, and then the signal input terminal is connected to the signal input terminal through each second shift register. The input signal is subjected to delay processing, and then each second shift register sends the delayed processed signal to the first DSP connected to it.

It should be noted that the method of retrieving the delay parameter from the storage array is the same as the method of retrieving the target parameter from the storage array. The specific implementation process and principle can refer to the detailed description of the above embodiment, which will not be repeated here.

Step 204, sending the second delay parameter to the first shift register.

Step 205: Send the first mask parameter to the second DSP array.

Step 206, sending the second mask parameter to the third DSP array to generate an FRM filter matching the current working bandwidth.

In the embodiment of the present application, since the configuration terminals of the first shift register, the first DSP array, the second DSP array and the third DSP array are all connected to the output terminal of the storage array, after the target parameters are acquired, the The configuration terminals of the first shift register, the second DSP array and the third DSP array respectively transmit the second delay parameter, the first mask parameter and the second mask parameter included in the target parameter to the first shift register, the first Two DSP arrays and a third DSP array, so that the first shift register, the second DSP array and the third DSP array adjust their internal parameters according to their respective parameters, so as to generate an FRM filter matching the current working bandwidth, and then pass The resulting FRM filter processes the signal input to the system at the signal input to generate a processed signal.

In the method for generating an FRM filter provided by the embodiment of the present application, target parameters corresponding to each working bandwidth are stored in a storage array, and target parameters corresponding to the current working bandwidth are retrieved from the storage array through a controller, and sent to the FRM filter components, so that the FRM filter component generates an FRM filter matching the current working bandwidth according to the target parameters; and, the FRM filter component is designed through complementary filters and shielding filters, and the DSP is multiplexed by symmetric parameters, and then the memory is used. One memory in the array stores the parameters corresponding to one DSP, which not only realizes the multiplexing of FRM filter chains in multi-bandwidth cells, reduces the resource occupancy, but also further reduces the number of DSPs and reduces the hardware complexity of the FRM filter. to improve the data reading speed.

It should be noted here that the above-mentioned methods provided in the embodiments of the present application can realize all the functions realized by the above-mentioned system embodiments, and can achieve the same technical effects, and the same technical effects as those of the system embodiments in this embodiment will not be discussed here. Parts and beneficial effects are described in detail.

As will be appreciated by those skilled in the art, the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, optical storage, and the like.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block in the flowcharts and/or block diagrams, and combinations of flows and/or blocks in the flowcharts and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These processor-executable instructions may also be stored in a processor-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory result in the manufacture of means comprising the instructions product, the instruction means implements the functions specified in the flow or flow of the flowchart and/or the block or blocks of the block diagram.

These processor-executable instructions can also be loaded onto a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process that The executed instructions provide steps for implementing the functions specified in the flow diagram flow or flow diagrams and/or the block diagram block or blocks.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (11)

1. a frequency response shielding filter system, is characterized in that, comprises: controller, storage array and frequency response shielding FRM filter assembly; Wherein, one end of the controller is connected to the signal input end, and the other end is connected to the control end of the storage array; The configuration end of the FRM filter assembly is connected to the output end of the storage array, the input end of the FRM filter assembly is connected to the signal input end, and the output end of the FRM filter assembly is used for outputting through the FRM the processed signal; The controller is configured to retrieve target parameters corresponding to the current working bandwidth from the storage array, so that the storage array sends the target parameters to the FRM filter component; The FRM filter component is configured to generate an FRM filter matching the current operating bandwidth according to the target parameter. 2. The system of claim 1, wherein the FRM filter assembly comprises: a first shift register, a first digital signal processor DSP array, a second DSP array, a third DSP array, an addition and subtractor; The configuration end of the first shift register, the configuration end of the first DSP array, the configuration end of the second DSP array, and the configuration end of the third DSP array are respectively connected with each output end of the storage array; The input end of the first DSP array and the input end of the first shift register are connected to the signal input end, and the output end of the first DSP array is respectively connected to the input end of the second DSP array, and the first input of the subtractor is connected; The output end of the second DSP array is connected with the first input end of the adder; The output end of the first shift register is connected to the second input end of the subtractor; The output end of the subtractor is connected with the input end of the third DSP array; The output end of the third DSP array is connected with the second input end of the adder; The adder is configured to output the processed signal. 3. The system of claim 2, wherein The first DSP array includes M1 first DSPs connected in sequence and connected end to end, wherein M1 is a value obtained by rounding up N1/2; The second DSP array includes M2 second DSPs connected in sequence and connected end to end, wherein M2 is a value obtained by rounding up N2/2; The third DSP array includes M3 third DSPs connected in sequence and connected end to end, wherein M3 is a value obtained by rounding up N3/2; Wherein, N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first mask filter in each FRM filter corresponding to the system, and N3 is the The highest order of the second mask filter in each FRM filter corresponding to the system. 4. The system of claim 3, further comprising: 2 (M1-1) second shift registers connected in sequence; Wherein, the input end of the first second shift register is connected with the signal input end; The configuration terminal of each of the second shift registers is connected to the output terminal of the memory used for storing the first delay parameter in the storage array, and the output terminal of the i-th second shift register, the The output terminals of the 2(M1-1)-(i-1) second shift registers are respectively connected to an input terminal of the i+1th first DSP, where i is greater than 0 and less than or equal to M1 A positive integer of -1. 5. The system of claim 4, wherein the storage array comprises K memories, wherein K=M1+M2+M3+2, wherein the M1 memories are respectively configured to store M1 memories Parameters corresponding to the first DSP; M2 memories, which are respectively configured to store parameters corresponding to M2 second DSPs; M3 memories, which are respectively configured to store parameters corresponding to M3 third DSPs, and one memory is configured to store all the parameters. The second delay parameter corresponding to the first shift register, and another memory is configured to store the first delay parameter corresponding to the M1-1 second shift registers. 6 . The system according to claim 5 , wherein the system corresponds to L kinds of working bandwidths, and each of the memories stores L kinds of parameters corresponding to the L kinds of working bandwidths respectively. 7 . 7. A method for generating a frequency response shielding filter, comprising: Get the current working bandwidth of the system; Read target parameters corresponding to the current working bandwidth from the storage array; The target parameters are sent to an FRM filter component to generate an FRM filter that matches the current operating bandwidth. 8. The method according to claim 7, wherein the reading the target parameter corresponding to the current working bandwidth from the storage array comprises: Obtain the corresponding relationship between each parameter and bandwidth in each memory of the storage array; Determine the target address corresponding to the current working bandwidth according to the corresponding relationship between the parameters and the bandwidth and the positions of the parameters in the memory; The target parameter corresponding to the target address is read from the storage array. 9. The method according to claim 8, wherein the order of the interpolation prototype filter in the FRM filter corresponding to the current working bandwidth is N1, and the order of the interpolation prototype filter according to the parameters and the bandwidth is N1. The corresponding relationship and the position of each parameter in the memory determine the target address corresponding to the current working bandwidth, including: Determine the M1 memories corresponding to the N1-order interpolation prototype filters, wherein M1 is a value obtained by rounding up N1/2; M1 target addresses corresponding to the current working bandwidth are determined according to the corresponding relationship between each parameter and the bandwidth in each of the memories and the position of each parameter in the memory. 10. The method of claim 7, wherein the FRM filter component comprises a first DSP array, a first shift register, a second DSP array and a third DSP array, and the target parameters include Filtering parameters, second delay parameters, first masking parameters, and second masking parameters, and the sending of the target parameters to the FRM filter component includes: sending the filtering parameters to the first DSP array; sending the second delay parameter to the first shift register; sending the first mask parameter to the second DSP array; The second mask parameter is sent to the third DSP array. 11. The method of claim 10, wherein the FRM filter assembly further comprises 2 (M1-1) second shift registers connected in sequence, and the target parameter further comprises a first delay register. time parameters, and the sending of the target parameters to the FRM filter component includes: Send the first delay parameter to the 2 (M1-1) second shift registers respectively, where M1 is the value obtained by rounding up N1/2, and N1 is the corresponding value of the FRM filter component The highest order of the interpolated prototype filter in each FRM filter of .

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