CN114387935A

CN114387935A - LCD driving method, controller and medium

Info

Publication number: CN114387935A
Application number: CN202210109085.1A
Authority: CN
Inventors: 朱县雄; 范春荣; 雷德刚
Original assignee: Shenzhen Kejinming Electronic Co Ltd
Current assignee: Shenzhen Kejinming Electronic Co Ltd
Priority date: 2022-01-28
Filing date: 2022-01-28
Publication date: 2022-04-22

Abstract

The invention discloses a driving method, a controller and a storage medium of an LCD (liquid crystal display) to solve the technical problem of high cost. Receiving input signals, wherein the input signals comprise input control clock signals, input field synchronizing signals, input line synchronizing signals, input data effective signals and input image signals, and the input image signals comprise red data signals, green data signals and blue data signals of all pixel points of each frame of image; output signals are correspondingly generated and transmitted to the LCD according to the timing sequence of the received input signals, wherein the output signals comprise an output control clock signal, an output field synchronous signal, an output line synchronous signal, an output data effective signal and an output monochrome image data signal, and indicating levels of the monochrome image data signal.

Description

LCD driving method, controller and medium

Technical Field

The present invention relates to the field of LCD display technologies, and in particular, to a driving method, a controller, and a storage medium for an LCD.

Background

The inventor researches and discovers that in a traditional 3LCD driving scheme, three driving circuits are generally needed to drive different color light paths, on one hand, the cost is increased due to the fact that multiple driving circuits are adopted, the three driving circuits independently drive different light path colors, the cost is increased, and most importantly, the problem that the original 3 circuits drive 3 LCDs to be asynchronous is solved.

Disclosure of Invention

The invention relates to the technical field of projection, and provides a driving method, a controller and a storage medium of an LCD (liquid crystal display), so as to solve the technical problem of overhigh cost.

A driving method of an LCD, the driving method comprising:

receiving input signals, wherein the input signals comprise input control clock signals, input field synchronizing signals, input line synchronizing signals, input data effective signals and input image signals, and the input image signals comprise red data signals, green data signals and blue data signals of all pixel points of each frame of image;

correspondingly generating and sending output signals to the LCD according to the time sequence of the received input signals, wherein the output signals comprise an output control clock signal, an output field synchronous signal, an output line synchronous signal, an output data effective signal, an output monochrome image data signal and an indication level indicating which monochrome data image signal;

wherein one cycle of the output field sync signal represents a color cycle signal, the output field sync signal includes a red frame cycle, a green frame cycle, and a blue frame cycle signal, a plurality of cycle signals of the output data valid signal, a plurality of cycle signals of the output line sync signal, and a corresponding monochrome image data signal are output in synchronization in each of the color cycles, and an indication level of the corresponding monochrome image data signal;

in the output data valid signal of the red frame period, the output line synchronization signal is used for controlling and outputting red data signals of all lines corresponding to the red frame period and a red period indication level, each output line synchronization signal in the red frame period is used for controlling and outputting one line of red data signals, and the red period indication level is used for indicating a red output image signal;

in the output data valid signal of the green frame period, the output data valid signal is used for controlling to output green data signals and green period indication levels of all rows corresponding to the green frame period, each output row synchronization signal in the green frame period is used for controlling to output one row of green data signals, and the green period indication level is used for indicating a green output image signal;

in the output data valid signal of the blue frame period, the output data valid signal is used for controlling to output blue data signals and blue period indication levels of all rows corresponding to the blue frame period, each output row synchronization signal in the blue frame period is used for controlling to output one row of blue data signals, and the blue period indication level is used for indicating a blue output image signal.

In one embodiment, the red, green and blue frame period signals each account for 1/3 of one period of the input field sync signal.

In one embodiment, a red frame period, a green frame period, and a blue frame period within one period of the input field sync signal are sequentially consecutive.

A controller for:

A computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of:

in the output data valid signal of the green frame period, the output data valid signal is used for controlling to output green data signals and green period indication levels of all rows corresponding to the green frame period, each output row synchronization signal in the blue frame period is used for controlling to output one row of green data signals, and the green period indication level is used for indicating a green output image signal;

in the output data valid signal of the blue frame period, the output data valid signal is used for controlling to output blue data signals and blue period indication levels of all rows corresponding to the blue frame period, each output row synchronization signal in the green frame period is used for controlling to output one row of blue data signals, and the blue period indication level is used for indicating a blue output image signal.

Compared with the traditional scheme, on one hand, the driving method, the control and the storage medium of the LCD utilize the regenerated output signals containing time sequence control to respectively obtain three different color periods, three monochrome image data signals and corresponding indication levels are loaded in sequence in the three different color periods, one driving circuit can be used for driving the LCD panel according to the output signals, the three driving circuits are not required to be used for respectively driving and outputting images of different light paths, the problem that signals output by different driving circuits are delayed to cause inconsistent signals when different color image data are loaded is solved, in addition, due to the adoption of the control time sequence of the output signals, the color signals of a plurality of light paths can be driven, the LCD panel is not required to be driven by three driving circuits, and the cost is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a schematic diagram of a controller in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating control timings of an input field sync signal, an input line sync signal, and an input control clock signal according to an embodiment of the present invention;

FIG. 3 is a timing diagram illustrating control of image data for a row of pixels in the input image data according to an embodiment of the present invention;

FIG. 4 is a timing diagram of an output signal generated and output according to an input signal in an embodiment of the present invention;

FIG. 5 is a timing diagram illustrating the control of the red frame period in the output field sync signal according to an embodiment of the present invention;

FIG. 6 is a timing diagram illustrating the control of an output horizontal sync signal during a red frame period according to an embodiment of the present invention;

FIG. 7 is a diagram of output red data in an output line sync signal of a red frame period according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The driving method of the LCD provided by the present invention can be applied to various application scenarios using the LCD, which are exemplary, including application to a projection device based on the LCD. It can be understood that the LCD-based projection apparatus includes a circuit system for processing image data, the circuit system performs corresponding processing on the input image data after receiving the input image data by using a video or image interface, splits and buffers the simultaneously input image data signal pairs into red (R), green (G) and blue (B) monochrome image data signals, and then sequentially transmits each processed monochrome image data signal to the LCD panel driver according to the 3 times frequency of the input signal, and outputs the indication level of the corresponding monochrome image data signal at the beginning of transmitting the monochrome image data signal, and projects the three color lights processed by the LCD panel in combination with the optical system portion of the projection apparatus through the projection lens, wherein the circuit system includes a controller, an image or video interface, and some buffer memories for splitting the monochrome image signal, the controller may be an FPGA controller, and is not particularly limited.

For the sake of understanding, the process of projection imaging is briefly introduced, and it can be understood that the continuous image corresponding to the content to be projected in projection imaging is composed of a plurality of continuous one-frame images, and one-frame image is divided into a plurality of lines of images, and depending on the resolution, one line includes a plurality of pixel points, that is, one frame of image is a pixel matrix. In the projection display process, a frame of image is divided into lines, then the lines are divided into pixels, the circuit system drives the liquid crystal molecules of the corresponding LCD pixels to change according to the display data to be projected, so that the corresponding R \ G \ B value changes, colors corresponding to the display data are generated, and the colors are projected through the optical system. However, in the conventional scheme, for each path of monochromatic light, a corresponding driving circuit needs to be configured, that is, three paths of driving circuits are used to control the optical path of one color, so on one hand, the circuit cost is increased, and on the other hand, because three paths of driving circuits control different optical paths, delay inconsistency is easy to occur, and the problem of signal inconsistency occurs, which leads to poor LCD driving effect and ultimately leads to poor projection imaging quality.

In order to facilitate understanding of the present invention, a description will first be made of a controller that provides terms for the present invention and a driving method using the LCD.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a controller according to the present invention, wherein the controller includes a plurality of input pins and a plurality of output pins, wherein the input pins are used for receiving input signals, and the output pins are used for outputting output signals, wherein the input signals include PLCK signals, DE signals, Hs signals, Vs signals, and input image signals, and the input image signals include R0-R7, G0-G7, B0-B7; and the output signals include a 3-multiplied clock PLCK3 signal, a DE3 signal, an Hs3 signal, a Vs3 signal, output monochrome image data signals O0-O7, and corresponding indicating levels S1-S0 of the output monochrome image data signals, the input signals, the output signals, and other terms to which the present invention relates are described as follows:

1Frame Time: a frame input image period;

PCLK signals: inputting a control clock signal;

a DE signal; inputting a data valid signal;

hs signal: inputting a line synchronization signal;

hsync: the initial signal interval of each periodic signal in the Hs signal represents the beginning of 1 line in the input image;

HBP (horizontal Back porch): the front shoulder of each cycle in the Hs signal;

HFP (horizontal Front Port): the back shoulder of each periodic signal in the Hs signal;

vs signal: inputting a field synchronization signal;

vsync: an initial signal interval of each periodic signal in the Vs signal, indicating the start of the input image 1 frame;

VBP (vertical Back Port): the front shoulder of each periodic signal in the Vs signal;

vfp (vertical Front port): the back shoulder of each periodic signal in the Vs signal;

vaild Date Interval: a valid data interval of the input image;

r0- -R7: inputting 8 bits of a red data signal in an image signal;

g0- -G7: inputting 8 bits of a green data signal in an image signal;

b0- -B7: inputting 8 bits of a blue data signal in the image signal;

PLCK3 signal: outputting a control clock signal;

DE3 signal: outputting a data valid signal;

hs3 signal: outputting a row synchronization signal;

hsync 3: the initial signal interval of each periodic signal in the Hs3 signal, representing the beginning of 1 line in the output image;

HBP 3: the anterior shoulder of each cycle in the Hs3 signal;

HFP 3: the back shoulder of each periodic signal in the Hs3 signal;

vs3 signal: outputting a field synchronization signal;

vsync 3: the initial signal interval of each periodic signal in the Vs3 signal, representing the beginning of a frame of the output monochrome image data signal 1;

VBP 3: the front shoulder of each periodic signal in the Vs3 signal;

VFP 3: the back shoulder of each periodic signal in the Vs3 signal;

vaild Date Interval 2: an effective data interval of the outputted monochrome image data signal;

O0-O7: 8 bits representing an output monochrome image data signal among the time-division output image signals;

s1, S0: indicating the indication level of the output monochrome image data signal, wherein: 00: indicates no signal; 01 denotes the output red data signal: 10 represents the output green data signal; 11 denotes an output blue data signal;

in one embodiment, a method of driving an LCD is provided.

In this embodiment, the following process is included:

receiving input signals, wherein the input signals comprise an input control clock signal PCLK, an input field synchronizing signal Vs, an input line synchronizing signal Hs, an input data effective signal DE and input image signals, and the input image signals comprise red data signals R, green data signals B and blue data signals B of all pixel points of each frame image;

correspondingly generating and sending output signals to the LCD according to the timing of the received input signals, wherein the output signals comprise an output control clock signal PCLK3, an output field synchronizing signal Vs3, an output row synchronizing signal Hs3, an output data valid signal DE3, time-sharing output monochrome image data signals O0-07 and indication levels S0-S1 for indicating which monochrome data image signals;

wherein, one period of the output field synchronizing signal represents a color periodic signal, the output field synchronizing signal comprises a red Frame period (R Frame Time), a green Frame period (G Frame Time) and a blue Frame period (B Frame Time), a plurality of periodic signals of an output data effective signal DE3, a plurality of periodic signals of an output line synchronizing signal Hs3 and corresponding Time-sharing output monochrome image data signals O0-07 in each output color period are synchronously output, and corresponding indicating levels S0-S1;

in the output data valid signal DE3 of the red Frame period (R Frame Time), the output data valid signal DE3 is used to control the output of the red data signals of all rows corresponding to the red Frame period (R Frame Time) and a red period indication level, each output row synchronization signal in the red Frame period is used to control the output of one row of red data signals to start, and the red period indication level is used to indicate a red output image signal;

in an output data valid signal of a green Frame period (G Frame Time), the output data valid signal is used for controlling to output green data signals and a green period indication level of all rows corresponding to the green Frame period, each output row synchronization signal in the green Frame period is used for controlling to output one row of green data signals, and the green period indication level is used for indicating a green output image signal;

in the valid signal of the output data of the blue Frame period (B Frame Time), the blue data signals of all rows corresponding to the blue Frame period are controlled to be output, each output row synchronization signal in the blue Frame period is used for controlling to output one row of the blue data signals, and the blue period indication level is used for indicating a blue output image signal.

In one embodiment, the red Frame period (R Frame Time), the green Frame period (G Frame Time), and the blue Frame period (B Frame Time) each account for 1/3 of one period of the input field sync signal Vs.

In one embodiment, a red Frame period (R Frame Time), a green Frame period (G Frame Time), and a blue Frame period (B Frame Time) within one period of the input field sync signal Vs are sequentially consecutive.

In order to facilitate understanding of the embodiments of the present invention, the embodiments of the present invention will be described in detail with reference to fig. 1 to 7. Referring to FIG. 2, FIG. 2 is a timing diagram illustrating the control of input signals according to the present invention, that is, the timing diagram of FIG. 2 is related to the timing of the input signals, and the controller is used for receiving the input signals including an input control clock signal PCLK, an input field synchronizing signal Vs, an input row synchronizing signal Hs, an input data valid signal DE, and input image signals D23-D0(R0-R7, G0-G7, B0-B7, which have 24 bits).

Referring to fig. 2, the timing diagram of fig. 2 is divided into two parts, the upper part is a timing diagram of one Frame of input image period (1Frame Time), the lower part is a timing diagram of one Frame of input line synchronizing signal Hs synchronously outputted corresponding to the one Frame of input image period, each period signal of the complete input field synchronizing signal Vs represents one Frame of input image period, taking one frame of the input image cycle as an example for description, each period signal of the input field synchronizing signal Vs corresponds to a plurality of period signals of the input line synchronizing signal Hs synchronously, each period signal of the input line synchronizing signal Hs also corresponds to a line timing chart, and when a certain period of the input line synchronizing signal Hs in one frame of the input image cycle is removed, the one frame of the input image cycle is a line timing control sequence chart of the input line synchronizing signal Hs, which is a timing chart corresponding to the lower part in fig. 2.

Referring to FIG. 3, FIG. 3 is a timing diagram illustrating the reception of the D23-D0 data during the period when the input data valid signal DE is high, and starts to receive the input image signals (D23-D0, R1-Rn, G1-Gn, B1-Bn) when the input data valid signal DE is high, wherein one input control clock signal period receives the input image signal of one pixel; the period of time from when the input horizontal synchronizing signal Hs changes from low level to high level until the input data valid signal DE is high level is the front shoulder HBP of the current period of the input horizontal synchronizing signal Hs. When an input row synchronization signal Hs is high level '1' and an input data effective signal DE is also high level '1', a row of RGB data corresponding to a current display frame in an input image signal is synchronously received, taking the row of RGB data as an example that the row of RGB data comprises N pixels, and outputting a group of RGB data (R1\ G1\ B1) of one Pixel per input control clock signal period, then the row of data comprises Pixel points Pixel1,. and Pixel, each Pixel comprises respective 8-Bit R \ G \ B data, taking Pixel point Pixel1 as an example and comprising R1\ G1\ B1, R1\ G1\ B1 and 8-Bit data, the Pixel points are respectively represented by Bit 1-Bit 1, the R1G 1B 1 constitutes the Pixel point 1, the Pixel points comprise Pixel values of the Pixel points R1\ G1, the Pixel values of the Pixel points are respectively represented by Bit 1-Bit 1, and the color values of the Pixel points are respectively represented by Bit 1\ 1, the Pixel points 1, 1 and the color values of the Pixel points are respectively represented by Bit 1, 1 includes the color values of the Pixel points are also represented by Bit 1, 1, taking Pixel point Pixel3 as an example, including R3\ G3\ B3, R3\ G3\ B3 all include 8-Bit data, and also expressed by bits 0-Bit 7, where R3\ G3\ B3 constitutes a color value of the Pixel point Pixel3, taking Pixel point Pixel as an example, including Rn \ Gn \ Bn, where Rn \ Gn \ Bn includes 8-Bit data, and also expressed by bits 0-Bit 7, where Rn \ Gn \ Bn constitutes a color value of the Pixel point Pixel, and the rest is analogized, and this is not illustrated here.

Meanwhile, as shown in fig. 3, after the input image signal of one line is received, when the input data valid signal DE changes from high level to low level, the input image signal is stopped from being received, and the arrival of the input line synchronizing signal Hs of the next period is waited, wherein the period from the beginning of the change of the input data valid signal DE from high level to low level to the beginning of the change of the input line synchronizing signal Hs from high level to low level is the back shoulder HFP of the input line synchronizing signal Hs of the current period, and the time passing through the back shoulder HFP of the input line synchronizing signal Hs of the current period is the input line synchronizing signal Hs of the next period, it can be seen that the Interval occupied by receiving the input image signal during the period when the input data valid signal DE is high level is the valid data Interval Vaild Date Interval of the input image data, in the timing chart of the whole input signal is calculated by the minimum unit of the PCLK signal, as shown in fig. 3, Hsync + HBP + Vaild Date Interval + HFP is a period of the input line synchronizing signal Hs, and one input field synchronizing signal Vs receives a complete frame of the input image signal synchronously.

By analogy, in the period of the next input line synchronizing signal Hs, the next input image signal is also received, so that the input image signal of a complete Frame is received, and similarly, when the next Frame, namely 2Frame Time, is received, the input image signals of a line and a line can be sequentially received according to the received input signals according to the relevant Time sequence, and the input image signal of a Frame can be received along with the Time. That is, the input image signal includes red, green, and blue data signals of all the pixel points of each frame image.

In the embodiment of the present invention, unlike the conventional scheme, the present invention generates and outputs the output signal according to the new driving manner according to the input image signal by the controller according to the timing of the input signal.

The embodiment of the invention correspondingly generates and sends output signals to the LCD according to the time sequence of the received input signals, wherein the output signals comprise an output control clock signal PCLK3, an output field synchronizing signal Vs3, an output line synchronizing signal Hs3, an output data valid signal DE3, monochrome image data signals O0-O7 which are output in a time-sharing mode, and indication levels S0-S1 of the corresponding monochrome image data signals.

Referring to fig. 4, fig. 4 is a timing diagram of output signals output by the controller according to the control timing of the input signals, wherein the output signals include an output control clock signal PCLK3, an output data valid signal DE3, an output line synchronization signal Hs3, an output field synchronization signal Vs3, and a monochrome image data signal output in a time-sharing manner, the monochrome image data signal indicates the indication level of the monochrome image data signal by O0-O7 and S0-S1, and O0-O7 indicate 8-bit data of a red data signal, a green data signal or a blue data signal for loading to the LCD panel when different frames of each pixel point are indicated.

Continuing to refer to fig. 4, in one Frame of the input image period, generating and outputting a field sync signal Vs3 synchronized with the input field sync signal Vs, wherein the output field sync signal Vs3 is divided into different color periods, one period of the output field sync signal Vs3 represents a color period signal including a red Frame period (R Frame Time), a green Frame period (G Frame Time), and a blue Frame period (B Frame Time), in one embodiment, the red Frame period, the green Frame period, and the blue Frame period are each 1/3 of the input field sync signal Vs, a plurality of period signals of the output data valid signal DE3, a plurality of period signals of the output line sync signal, and the output image signal are synchronously output in each color period, a plurality of line sync signals Hs3 are synchronously output in each red Frame period (R Frame Time), a plurality of line synchronizing signals Hs3 are synchronously output in a green Frame period (G Frame Time), and a plurality of line synchronizing signals Hs3 are synchronously output in a blue Frame period (B Frame Time).

Referring to fig. 5, taking the red Frame period (R Frame Time) as an example, the red Frame period (R Frame Time) occupies one period of the output field synchronization signal Vs3, the one period of the output field synchronization signal Vs3 also includes a Vsync3 signal period, a VBP3 signal period, and a VFP3 signal period, and the output line synchronization signal Hs3 of multiple periods is synchronously output in the red Frame period (R Frame Time).

Referring to fig. 6, continuing with the red Frame period (R Frame Time) as an example, the duration of each output row synchronization signal Hs3 period within the red Frame period (R Frame Time) is configured with Hsync3+ Vaild Date Interval3+ HFP 3.

Referring to fig. 7, taking one output row synchronizing signal Hs3 cycle as an example of a red Frame cycle (R Frame Time) as an example to illustrate the process of outputting red image signals, in the output row synchronizing signal Hs3, when the output data valid signal DE3 (DE3 is high), when the output data valid signal DE3 is high, the output row synchronizing signal is used to control the output of red data signals and red period indication levels of all rows corresponding to the red Frame cycle (R Frame Time), as shown in fig. 7, when the output data valid signal DE3 is high, one output control clock signal PCLK3 cycle outputs one set of red data signals in one row simultaneously, one output data valid signal DE3 cycle includes output control clock signals PCLK3 of multiple cycles, and thus the red data signals of all rows in the red data signals are output, so that in the red Frame cycle (R Frame Time), the output red data signals are R1-Rn, the red period indicating level S-S1 is output as 01 (red), i.e., the output data includes all the input red data signals (R1-Rn) for the current frame, and the output of S0-S1 is 01.

By analogy, when the output data valid signal DE3 of the green Frame Time is at a high level, the green data signals (G1-Gn) and the green period levels S0-S1 of all rows corresponding to the green Frame Time (G Frame Time) are synchronously output, wherein the green period level is 01, that is, the output of S0-S1 is 10 (green); similarly, when the output data valid signal DE3 of the blue Frame Time is at a high level, the blue data signals (B1-Bn) and the blue period levels S0-S1 of all rows corresponding to the blue Frame Time (B Frame Time) are simultaneously output, that is, the output levels S0-S1 are changed to 11 (blue), wherein the timing control of the green data signals and the blue data signals can refer to the description of the output red data signals, and in addition, the schematic diagrams for outputting the green Frame and the blue Frame are completely similar to the red Frame signals, which are not described herein, and when the output data valid signal DE3 is at a low level, the output image data signals are not valid, and the change indication levels S0-S1 are changed to 00.

By analogy, when the field synchronization signal Vs3 is output next, in the red frame period, the green frame period and the blue frame period which are output synchronously, corresponding colors are output according to the corresponding output control clock signal PCLK3 and the output data valid signal DE3, so that the LCD is driven to render a complete image through the complete field synchronization signal Vs 3.

Thus, after receiving the output signal, the LCD can load and display the image on the output signal, and when the LCD is applied to the LCD projection device, the driving process of the LCD is similar and will not be described herein.

It can be seen that, by using the driving method of the LCD provided by the embodiment of the present invention, for each path of monochromatic light, three driving circuits are not required to be used to respectively control the light path of one color, on one hand, the circuit cost is not increased, on the other hand, because the three driving circuits do not control different light paths to load different color signals, but the controller provides a new time-sharing driving red, green and blue data signal to drive a single LCD to display according to the control timing sequence of the output signal, and because of the different delay problems of different circuits and different LCD screens, the driving effect of the LCD is not deteriorated, and when the driving method is applied to an LCD projection device, the projection imaging quality is not deteriorated, and it is seen that the driving method has a better application scene in both LCD projection scene and other scenes in which the LCD is applied.

In one embodiment, a controller is provided, which may be an FPGA controller, and when executed, implements a driving method of an LCD provided by the above embodiments.

In one embodiment, there is provided a computer-readable storage medium having a computer program stored thereon, the computer program implementing a driving method of an LCD provided by the above-described embodiments when executed by a controller.

For more details of the controller and the implementation scheme of the computer readable storage medium, reference may be made to the foregoing method embodiments, and the description will not be repeated here.

In some embodiments, the present invention further provides a projection apparatus, which includes a controller provided by the present invention, and the controller is used for implementing the driving method of the LCD, which will not be described herein.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A driving method of an LCD, comprising:

2. The method of driving an LCD of claim 1, wherein the red, green and blue frame period signals each account for 1/3 of one period of the input field sync signal.

3. The method of driving an LCD of claim 1, wherein a red frame period, a green frame period, and a blue frame period within one period of the input field sync signal are sequentially consecutive.

4. A controller, characterized in that the controller is configured to:

5. The controller of claim 4, wherein said red, green and blue frame period signals each account for 1/3 of one period of said input field sync signal.

6. The controller according to claim 4, wherein a red frame period, a green frame period, and a blue frame period within one period of the input field sync signal are sequentially consecutive.

7. A computer-readable storage medium storing a computer program, the computer program when executed by a processor implementing the steps of:

8. The computer-readable storage medium of claim 7 wherein the red, green and blue frame period signals each account for 1/3 of one period of the input field sync signal.

9. The computer-readable storage medium of claim 7, wherein a red frame period, a green frame period, and a blue frame period within one period of the input field sync signal are sequentially consecutive.