CN114384391B - Method for estimating junction temperature of main chip of domain controller - Google Patents
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- 239000003292 glue Substances 0.000 claims description 29
- 238000009792 diffusion process Methods 0.000 claims description 17
- 238000010438 heat treatment Methods 0.000 claims description 15
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- 238000009826 distribution Methods 0.000 claims description 7
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- 239000000758 substrate Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
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- 230000008859 change Effects 0.000 description 1
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- 230000017525 heat dissipation Effects 0.000 description 1
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Abstract
The invention relates to the technical field of hardware of an automatic driving domain controller, in particular to a method for estimating the junction temperature of a main chip of a domain controller. The junction temperature of the chip and the temperature of each part can be obtained to be used as the reference of the early design; the thermal resistance of each part and the proportion displayed in the pie chart can be obtained, so that designers can conveniently find an easy improvement point; only parameters need to be input, results are given quickly, and DOE experiment prediction is convenient to carry out; the invention can analyze the thermal resistance of the whole product, considers three forms of heat conduction, convection and radiation, and greatly improves the evaluation speed of the scheme.
Description
Technical Field
The invention relates to the technical field of hardware of an automatic driving domain controller, in particular to a method for estimating junction temperature of a main chip of the domain controller.
Background
A domain controller is increasingly adopted by new energy automobiles, particularly the domain controller related to automatic driving is taken as an SOC chip which is the key of the domain controller, the chip computing power requirement is higher and higher, the temperature control of the SOC chip is the key of the safe operation of a system, and reasonable thermal design is required for guaranteeing. The simulation needs model building and grid processing, and the thermal test needs sample piece manufacturing, so that the design period can be greatly shortened by rapidly evaluating the chip junction temperature of the technical scheme at the initial stage of design, and the clear and rapid calculation of the chip junction temperature has important significance for the initial design and scheme change.
The existing estimation of the junction temperature of a chip of a domain controller is mainly realized by commercial electronic thermal simulation software, except the collection of early-stage parameters, model simplification, grid processing and the like are needed, certain process time is needed, new calculation tasks can be brought by replacing one material or size, the proportion of each part of thermal resistance can not be analyzed quickly, and scheme optimization can be carried out, so that the aim of saving the cost is fulfilled. In addition, engineers cannot judge the chip surface temperature, and the error of artificially estimating the chip junction temperature is too large, so that an appropriate method for estimating the systematic chip junction temperature is urgently needed.
To solve the above problems, the present application proposes a method for estimating the junction temperature of the main chip of the domain controller.
Disclosure of Invention
In order to solve the technical problems existing in the background technology, the invention provides a method for estimating the main chip junction temperature of a domain controller, which utilizes theoretical calculation and measurement experience to approximately estimate the chip junction temperature.
The invention provides a method for estimating the junction temperature of a main chip of a domain controller, which comprises the following steps:
distributing the thermal resistance of the chip radiator according to the thermal resistance of the upper and lower shells to form an upper and lower radiating paths and determine the total power consumption of the upper and lower paths;
setting initial values including an upper shell initial convective heat transfer coefficient and a radiant heat transfer coefficient, and a lower shell initial convective heat transfer coefficient and a radiant heat transfer system;
according to the environment temperature, the heating power of the initial single-path total power consumption and the heat resistance of the radiator, the real convective heat transfer coefficient, the real radiant heat transfer coefficient and the surface temperature of the radiator are calculated through iteration, and the correct distribution proportion of the heat resistance of the radiator and the total power consumption of the upper shell and the lower shell is calculated;
calculating the thermal resistance of each component according to the thermal resistances of the upper path and the lower path;
distributing the power consumption of the upper path chip and the lower path chip according to the thermal resistance;
calculating the temperature of the boss according to the surface temperature of the radiator, the heating power of the single-path chip power consumption, the thermal resistance of the radiator and the thermal diffusion resistance of the radiator;
calculating the temperature of the heat-conducting glue according to the temperature of the boss, the heating power of the power consumption of the single-path chip and the thermal resistance of the boss;
calculating the surface temperature of the chip package according to the temperature of the heat-conducting glue, the heating power of the single-path chip power consumption and the heat resistance of the heat-conducting glue;
and obtaining the junction temperature of the chip according to the surface temperature of the chip package, the heating power of the single-path chip power consumption and the thermal resistance of the chip package.
Preferably, the proportion of each component is calculated according to the thermal resistance of each component to form a thermal resistance distribution diagram.
Preferably, the thermal resistance profile may be a pie chart or a bar chart or a line chart.
Preferably, the upper path thermal resistance is a thermal resistance from a chip node to the upper shell in a direction vertical to the surface of the chip, the lower path thermal resistance is a thermal resistance from the chip node to the lower shell in a direction vertical to the surface of the chip, and a heat transfer path on the side edge of the chip is ignored to form heat transfer with the upper path and the lower path connected in parallel, and the formula is as follows:
wherein,
representing the total thermal resistance of the chip.
Preferably, the upper path thermal resistance comprises a junction-shell thermal resistance, a thermal conductive adhesive thermal resistance, a boss thermal resistance, a diffusion thermal resistance and a radiator upper shell thermal resistance, and the lower path thermal resistance comprises a junction-plate thermal resistance, a PCB thermal resistance, a thermal conductive adhesive thermal resistance, a boss thermal resistance, a diffusion thermal resistance and a radiator lower shell thermal resistance, and comprises the following formulas:
the internal thermal resistances of the upper path thermal resistance and the lower path thermal resistance are connected in series; the heat-conducting glue thermal resistance and diffusion thermal resistance calculation formula is as follows:
wherein,
the heat transfer thickness of the heat-conducting glue is adopted, k is the heat conductivity coefficient of the heat-conducting glue, and A is the cross sectional area of the heat transfer path; the calculation formula of the boss thermal resistance is the same as that of the heat-conducting glue;
wherein, the thermal diffusion resistance is estimated by adopting a Lee formula:
wherein k is the heat conductivity of the heat sink, r is the radius of the heat source,
、
is a computable dimensionless constant.
Preferably, the heat sink thermal resistance includes a heat sink thermal conduction thermal resistance and a heat sink convection thermal radiation thermal resistance, wherein the heat sink thermal conduction thermal resistance includes two parts of a heat conduction thermal resistance of the substrate and a heat conduction thermal resistance of the fin, and a calculation formula is as follows:
wherein k is the heat conductivity of the heat sink,
is the sectional area of the base of the heat sink, and t is the thickness of the base of the heat sink; h is the length of the fin,
is the cross-sectional area of the fin, N isThe number of teeth of the fins; the radiator base and the fins are connected in series, and the fins are connected in parallel;
in the formula, h is the total heat exchange coefficient of the surface of the radiator, and A is the total external surface area of the radiator.
Preferably, the thermal convection resistance of the heat sink comprises a thermal convection resistance of the heat sink and a thermal radiation resistance of the heat sink, and the two are in a parallel relation, and the formula is as follows:
in the formula,
in order to obtain a convective heat transfer coefficient,
in order to be the heat transfer coefficient of the radiation,
is a constant of boltzmann's constant,
in order to be an emissivity value,
is the temperature of the surface of the heat sink,
is the air temperature.
Preferably, the method further comprises the steps of preliminarily estimating various size parameters of the upper and lower shells as the heat radiator, and determining the material, emissivity and heat conductivity coefficient of the heat radiator upper and lower shells and the heat conducting glue.
Preferably, the method further comprises extracting junction-to-case thermal resistance and junction-to-plate thermal resistance and allowed maximum junction temperature according to the selected chip specification.
The technical scheme of the invention has the following beneficial technical effects:
the invention systematically analyzes the thermal resistance of each part, greatly improves the junction temperature evaluation speed, and is beneficial to the design for DOE experiment comparison to achieve the purposes of cost reduction and efficiency improvement. The junction temperature of the chip and the temperature of each part can be obtained to be used as the reference of the early design; the thermal resistance of each part and the proportion displayed in the pie chart can be obtained, so that designers can conveniently find an easy improvement point; only parameters need to be input, results are given quickly, and DOE experiment prediction is convenient to carry out; the invention can analyze the thermal resistance of the whole product, considers three forms of heat conduction, convection and radiation, and greatly improves the evaluation speed of the scheme.
Drawings
FIG. 1 is a flow chart of one embodiment of a method of the present invention;
FIG. 2 is a cross-sectional view of a heat sink and chip structure according to the present invention;
FIG. 3 is a schematic view of the heat transfer between the upper and lower paths in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the accompanying drawings in combination with the embodiments. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Refer to fig. 1-3.
For the L2 level and L2+ level automatic driving range controllers, a natural heat dissipation manner is generally adopted, as shown in fig. 2, in fig. 2: a represents the upper case of the heat sink, B represents the lower case of the heat sink, A1 represents the fins, A2 represents the teeth formed by the fins, A3 represents the boss of the upper case, A4 represents the heat-conducting glue between the boss of the upper case and the upper surface of the chip, B1 represents the boss of the lower case, B2 represents the heat-conducting glue between the PCB and the boss of the lower case, C represents the PCB, and D represents the junction temperature of the chip.
The method comprises the steps of preliminarily estimating various size parameters of the upper and lower shells as the radiator, such as the number of teeth, the height of teeth, the thickness of a substrate and the length and the width of the radiator, determining the material of the shell, the emissivity and the heat conductivity coefficient of heat-conducting glue, and extracting junction-to-shell thermal resistance, junction-to-plate thermal resistance and allowable maximum junction temperature according to a selected chip specification.
Because the convective radiation thermal resistance (surface heat exchange thermal resistance of the radiator) and the diffusion thermal resistance of the radiator are associated with the temperature, initial values are required to be set for iterative solution, and the initial values comprise the convective heat exchange coefficient of the upper shell, the radiative heat exchange coefficient, the initial convective heat exchange coefficient of the lower shell and the radiative heat exchange coefficient.
Distributing the thermal resistance of the chip radiator according to the thermal resistance of the upper and lower shells to form an upper and lower radiating paths and determine the total power consumption of the upper and lower paths; setting initial values including an upper shell initial convective heat transfer coefficient, a radiant heat transfer coefficient, a lower shell initial convective heat transfer coefficient and a radiant heat transfer system; according to the environment temperature, the heating power of the initial single-path total power consumption and the heat resistance of the radiator, the real convective heat transfer coefficient, the real radiant heat transfer coefficient and the surface temperature of the radiator are calculated through iteration, and the correct distribution proportion of the heat resistance of the radiator and the total power consumption of the upper shell and the lower shell is calculated; calculating the thermal resistance of each component according to the thermal resistances of the upper path and the lower path; distributing the power consumption of the upper path chip and the lower path chip according to the thermal resistance; calculating the temperature of a boss (the junction with the inner surface of the radiator, namely the junction of the upper shell and the inner surface of the lower shell of the radiator) according to the surface temperature of the radiator, the heating power of the single-path chip power consumption, the thermal resistance of the radiator and the thermal diffusion resistance; calculating the temperature of the heat-conducting glue (interface with the boss) according to the temperature of the boss, the heating power of the single-path chip power consumption and the thermal resistance of the boss; calculating the surface temperature of the chip package (if the lower path is the PCB bottom temperature) according to the temperature of the heat-conducting glue, the heating power of the single-path chip power consumption and the heat resistance of the heat-conducting glue; and obtaining the junction temperature of the chip according to the surface temperature of the chip package, the heating power of the single-path chip power consumption and the thermal resistance of the chip package.
Referring to fig. 3, the chip transfers heat through two paths, i.e., upper and lower paths, and the thermal influence in the horizontal direction of the chip is ignored. The purpose of introducing the diffusion thermal resistance is to consider the influence of different sizes of a heat source and a contact surface, and the power consumption of a single chip of an upper path and a lower path is distributed according to the thermal resistance, because only one chip exists between an upper shell and a lower shell of a radiator, only one chip is shown in the figure 2 of the application and is only used for reference to understand the invention.
For a better understanding of the present invention, the total thermal resistance of the domain control chip can be expressed as:
the upper path thermal resistance is the thermal resistance from the chip node to the upper shell in the direction vertical to the surface of the chip, the lower path thermal resistance is the thermal resistance from the chip node to the lower shell in the direction vertical to the surface of the chip, and the heat transfer path on the side edge of the chip is ignored to form the heat transfer with the upper path and the lower path connected in parallel, and the formula is as follows:
wherein,
representing the total thermal resistance of the chip.
The upper path thermal resistance comprises crust thermal resistance, heat-conducting glue thermal resistance, boss thermal resistance, diffusion thermal resistance and heat radiator upper shell thermal resistance, and the lower path thermal resistance comprises junction plate thermal resistance, PCB thermal resistance, heat-conducting glue thermal resistance, boss thermal resistance, diffusion thermal resistance and heat radiator lower shell thermal resistance, and comprises the following formulas:
wherein, each internal thermal resistance of the upper path thermal resistance and the lower path thermal resistance is connected in series; the heat-conducting glue thermal resistance and diffusion thermal resistance calculation formula is as follows:
wherein,
the heat transfer thickness of the heat-conducting glue is adopted, k is the heat conductivity coefficient of the heat-conducting glue, and A is the cross sectional area of the heat transfer path; the calculation formula of the boss thermal resistance is the same as that of the heat-conducting glue;
wherein, the thermal diffusion resistance is estimated by adopting a Lee formula:
wherein k is the heat conductivity of the heat sink, r is the radius of the heat source,
、
is a computable dimensionless constant.
The upper and lower housings need to be simplified to standard finned horizontal heat sinks for thermal resistance calculations.
The heat resistance of the radiator comprises heat conduction resistance of the radiator and convection radiation resistance of the radiator, wherein the heat conduction resistance of the radiator comprises two parts of heat conduction resistance of a substrate and heat conduction resistance of fins, and the calculation formula is as follows:
wherein k is the heat conductivity of the heat sink,
is the sectional area of the base of the heat sink, and t is the thickness of the base of the heat sink; h is the length of the fin,
the cross section area of the fin is shown, and N is the tooth number of the fin; the radiator base and the fins are connected in series, and the fins are connected in parallel;
in the formula, h is the total heat exchange coefficient of the surface of the radiator, and A is the total external surface area of the radiator.
Because the natural convection heat transfer of the radiator can have two important ways of radiation and convection heat transfer, the radiation and the convection heat transfer are parallel connection, and the natural convection radiation cannot be ignored. The radiator convective radiation thermal resistance comprises a radiator convective thermal resistance and a radiator radiation thermal resistance which are in parallel connection, and the formula is as follows:
in the formula,
in order to obtain a convective heat transfer coefficient,
in order to be the heat transfer coefficient of the radiation,
is the boltzmann constant, and is,
in order to be an emissivity value,
is the temperature of the surface of the heat sink,
is the air temperature.
It should be noted that, in the invention, the thermal resistance distribution diagram formed by the proportion of each component can be calculated according to the thermal resistance of each component, and the thermal resistance distribution diagram can be a pie chart or a bar chart or a line chart, so that a designer can conveniently find an easy-to-improve point.
The foregoing shows and describes the general principles, principal features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and the preferred embodiments of the present invention are described in the above embodiments and the description, and are not intended to limit the present invention.
Claims (7)
1. A method for domain controller primary chip junction temperature estimation, comprising:
distributing the thermal resistance of the chip radiator according to the thermal resistance of the upper and lower shells to form an upper and lower radiating paths and determine the total power consumption of the upper and lower paths;
setting initial values including an upper shell initial convective heat transfer coefficient and a radiant heat transfer coefficient, and a lower shell initial convective heat transfer coefficient and a radiant heat transfer coefficient;
according to the environment temperature, the heating power of the initial single-path total power consumption and the heat resistance of the radiator, the real convective heat transfer coefficient, the real radiant heat transfer coefficient and the surface temperature of the radiator are calculated through iteration, and the correct distribution proportion of the heat resistance of the radiator and the total power consumption of the upper shell and the lower shell is calculated;
calculating the thermal resistance of each component according to the thermal resistances of the upper path and the lower path;
distributing the power consumption of the upper path chip and the lower path chip according to the thermal resistance;
calculating the temperature of the boss according to the surface temperature of the radiator, the heating power of the single-path chip power consumption, the thermal resistance of the radiator and the thermal diffusion resistance;
calculating the temperature of the heat-conducting glue according to the temperature of the boss, the heating power of the power consumption of the single-path chip and the thermal resistance of the boss;
calculating the surface temperature of the chip package according to the temperature of the heat-conducting glue, the heating power of the single-path chip power consumption and the heat resistance of the heat-conducting glue;
obtaining the junction temperature of the chip according to the surface temperature of the chip package, the heating power of the single-path chip power consumption and the thermal resistance of the chip package;
the upper path thermal resistance is the thermal resistance from the chip node to the upper shell in the direction vertical to the surface of the chip, the lower path thermal resistance is the thermal resistance from the chip node to the lower shell in the direction vertical to the surface of the chip, and the heat transfer path on the side edge of the chip is ignored to form the heat transfer with the upper path and the lower path connected in parallel, and the formula is as follows:
wherein,
represents the total thermal resistance of the chip;
the upper path thermal resistance comprises a crust thermal resistance, a heat-conducting glue thermal resistance, a boss thermal resistance, a diffusion thermal resistance and a radiator upper shell thermal resistance, and the lower path thermal resistance comprises a panel thermal resistance, a PCB thermal resistance, a heat-conducting glue thermal resistance, a boss thermal resistance, a diffusion thermal resistance and a radiator lower shell thermal resistance, and comprises the following formulas:
wherein, each internal thermal resistance of the upper path thermal resistance and the lower path thermal resistance is connected in series; the heat-conducting glue thermal resistance and diffusion thermal resistance calculation formula is as follows:
wherein,
the thickness of the heat transfer of the heat-conducting glue,
is the heat conductivity coefficient of the heat-conducting glue,
the cross-sectional area of the heat transfer path; the calculation formula of the boss thermal resistance is the same as that of the heat-conducting glue;
wherein, the thermal diffusion resistance is estimated by adopting a Lee formula:
in the formula,
is the heat conductivity of the heat sink, r is the radius of the heat source,
、
is a computable dimensionless constant.
2. The method of claim 1, wherein a thermal resistance profile is formed by calculating proportions of each component based on thermal resistance of each component.
3. A domain controller master chip junction temperature estimation method according to claim 2, wherein the thermal resistance distribution graph can be a pie chart or a bar chart or a line graph.
4. The method of claim 1, wherein the heat sink thermal resistance comprises a heat sink thermal conduction resistance and a heat sink convective radiation thermal resistance, wherein the heat sink thermal conduction resistance comprises two parts, namely a base thermal conduction resistance and a fin thermal conduction resistance, and the calculation formula is as follows:
in the formula,
in order to be the heat conductivity of the heat sink,
is the sectional area of the base of the heat sink, and t is the thickness of the base of the heat sink; h is the length of the fin,
the cross section area of the fin is shown, and N is the tooth number of the fin; the base and the fins of the radiator are connected in series, and the fins are connected in parallel;
in the formula, h is the total heat exchange coefficient of the surface of the radiator,
is the total external surface area of the radiator.
5. The method of claim 4, wherein the thermal radiator convective and radiative resistances comprise a thermal radiator convective resistance and a thermal radiator radiative resistance, which are in parallel relationship, and the following formula is given:
in the formula,
in order to obtain a convective heat transfer coefficient,
in order to be the heat transfer coefficient of the radiation,
is the boltzmann constant, and is,
in order to be an emissivity value,
is the temperature of the surface of the heat sink,
is the air temperature.
6. The method of claim 1, further comprising performing a preliminary estimation of dimensional parameters of the upper and lower cases as heat sinks, and determining the material, emissivity, and thermal conductivity of the heat sink upper and lower cases and the thermal conductivity of the thermal conductive paste.
7. The method of claim 1, further comprising extracting junction-to-case thermal resistance and junction-to-plate thermal resistance, and allowed maximum junction temperature from the selected chip specification.
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