CN114363717A - Method, device, equipment and medium for improving reliability of ultra-high definition signal transmission - Google Patents
Method, device, equipment and medium for improving reliability of ultra-high definition signal transmission Download PDFInfo
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- CN114363717A CN114363717A CN202111609284.0A CN202111609284A CN114363717A CN 114363717 A CN114363717 A CN 114363717A CN 202111609284 A CN202111609284 A CN 202111609284A CN 114363717 A CN114363717 A CN 114363717A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client
- H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
- H04N21/647—Control signaling between network components and server or clients; Network processes for video distribution between server and clients, e.g. controlling the quality of the video stream, by dropping packets, protecting content from unauthorised alteration within the network, monitoring of network load, bridging between two different networks, e.g. between IP and wireless
- H04N21/64723—Monitoring of network processes or resources, e.g. monitoring of network load
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
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- Computer Security & Cryptography (AREA)
- Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
Abstract
The invention discloses a method, a device, equipment and a medium for improving the transmission reliability of an ultra-high definition signal, wherein the method comprises the following steps: acquiring a time sequence signal received by a video transmission interface of a display driving chip in a preset state; judging whether the time sequence signal is abnormal or not; when the time sequence signal is judged to be abnormal, jumping to enter a reset state; the connection is reset in a reset state to improve the signal quality of the received ultra high definition video data. According to the invention, whether the received time sequence signal is abnormal or not is judged, if the received time sequence signal is abnormal, the CDR training state is jumped to improve the signal quality, so that the reliability of the VbyOne interface is greatly improved by increasing the automatic abnormal recovery mechanism, and the user experience can be greatly improved.
Description
Technical Field
The invention relates to the field of televisions, in particular to a method, a device, equipment and a medium for improving the transmission reliability of an ultra-high definition signal.
Background
Ultra-high-definition display screens such as 4K screens and 8K screens can bring on-site extremely strong and shocking visual experience to audiences, and are therefore more and more favored by consumers.
The 4K screen and the 8K screen are both internally driven by 4K/8K display chips, and video transmission interfaces of the chips may be VbyOne, HDMI, DisplayPort, MIPI, LVDS or the like. The SoC transmits the video to a display chip of a 4K or 8K screen through the video transmission interface.
Taking the VbyOne interface as an example, there are 4 operating states, which are respectively, Shut down, CDR tracing, ALN tracing and Normal state. These 4 states are defined as follows:
shut down: in a power-down state, the receiving end does not work;
CDR training: a clock recovery Training state, wherein the receiving terminal enters the state after being electrified, a CDR circuit of the receiving terminal recovers the clock frequency for receiving data (namely CDR locking) through the received Training data in the state, and the receiving terminal enters the next state ALN Training after the CDR locking;
ALN tracing: an alignment training state, in which a receiving end aligns received bytes and pixels through received specific data, and enters a next state Normal after the state is finished;
normal: and after entering the Normal state, starting to receive the video data, entering a CDR tracking state when the receiving end finds that the CDR loses the lock, otherwise, keeping the receiving end in the Normal state all the time.
The conventional VbyOne receiving end only checks whether the CDR is out of lock after entering the Normal state, and only enters the CDR tracking state when the CDR is out of lock (as shown in fig. 1). However, in practical applications, in some extreme cases or after a long time operation, the CDR may be in a locked state, but the received video timing signal has a problem, and at this time, the screen display picture is abnormal, but because the CDR is in the locked state, the CDR training is not entered to improve the signal quality, and at this time, the picture is in an abnormal state for a long time, which results in poor user experience.
Disclosure of Invention
In view of the foregoing problems, an object of the embodiments of the present invention is to provide a method, an apparatus, a device, and a medium for improving reliability of ultra high definition signal transmission, so as to improve the foregoing problems.
The embodiment of the invention provides a method for improving the transmission reliability of an ultra-high definition signal, which comprises the following steps:
acquiring a time sequence signal received by a video transmission interface of a display driving chip in a preset state;
judging whether the time sequence signal is abnormal or not;
when the time sequence signal is judged to be abnormal, jumping to enter a reset state;
the connection is reset in a reset state to improve the signal quality of the received ultra high definition video data.
Preferably, the video transmission interface is a VbyOne interface; the preset state is a Normal state, and the reset state is a CDR tracking state.
Preferably, the determining whether the timing signal is abnormal specifically includes:
counting and monitoring the time sequence signals received by the Vbyone interface, and counting the length of each effective data signal DE, the number of DE rising edges of each frame of picture and the number of VS rising edges in one second;
and when any one of the length of each data effective signal DE, the number of the DE rising edges of each frame of picture and the number of the VS rising edges in one second is abnormal, judging that the time sequence signal is abnormal.
The embodiment of the invention also provides a device for improving the transmission reliability of the ultra-high definition signal, which comprises:
the time sequence signal acquisition unit is used for acquiring a time sequence signal received by a video transmission interface of the display driving chip in a preset state;
the time sequence detection unit is used for judging whether the time sequence signal is abnormal or not;
the skipping unit is used for skipping to enter a reset state when the time sequence signal is judged to be abnormal;
a reset unit for resetting the connection in a reset state to improve signal quality of the received ultra high definition video data.
Preferably, the video transmission interface is a VbyOne interface; the preset state is a Normal state, and the reset state is a CDR tracking state.
Preferably, the timing detection unit is specifically configured to:
counting and monitoring the time sequence signals received by the Vbyone interface, and counting the length of each effective data signal DE, the number of rising edges of the effective signals DE of each frame of picture and the number of rising edges of the frame synchronization signals VS within one second;
and when any one of the length of each data effective signal DE, the number of rising edges of the effective signals DE of each frame of picture and the number of rising edges of the frame synchronizing signals VS within one second is abnormal, judging that the time sequence signal is abnormal.
The embodiment of the present invention further provides an apparatus for improving reliability of ultra high definition signal transmission, which includes a processor and a memory storing a computer program, where the computer program can be executed by the processor to implement the method for improving reliability of ultra high definition signal transmission as described above.
The embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, where the computer program can be executed by a processor of a device where the computer-readable storage medium is located, so as to implement the method for improving reliability of ultra high definition signal transmission as described above.
In summary, the embodiment of the present invention determines whether the received timing signal is abnormal, and if there is an abnormality, the CDR tracing state is skipped to retrain to improve the signal quality, so that the reliability of the VbyOne interface is greatly improved by adding the automatic abnormality recovery mechanism, and the user experience can be greatly improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a state machine state diagram of a conventional VbyOne interface.
Fig. 2 is a schematic flow chart of a method for improving reliability of ultra high definition signal transmission according to a first embodiment of the present invention.
Fig. 3 is a schematic diagram of timing signals according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of an ultra high definition signal transmission reliability improving apparatus according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, a first embodiment of the present invention provides an ultra high definition signal transmission reliability improving method, which can be executed by an ultra high definition signal transmission reliability improving device (hereinafter referred to as an improving device), and in particular, executed by one or more processors in the improving device, to implement the following steps:
s101, in a preset state, acquiring a time sequence signal received by a video transmission interface of a display driving chip.
In this embodiment, the improvement device may be a television, in particular, an ultra high definition television.
In this embodiment, the video transmission interface may be VbyOne, HDMI, DisplayPort, MIPI, LVDS, or the like, and the present invention is not limited specifically. For the convenience of the description of the present invention, the following description will be given by taking the VbyOne interface as an example, but the present invention is not limited thereto.
In this embodiment, for the VbyOne interface, the preset state is a Normal state, and in the Normal state, the improving apparatus may receive the video data and display the video data through the ultra-high-definition display.
S102, judging whether the time sequence signal is abnormal or not.
As shown in fig. 3, in the present embodiment, the timing signals include a frame synchronization signal VS (hereinafter referred to as a VS signal), a line synchronization signal HS (hereinafter referred to as an HS signal), and an effective signal DE (hereinafter referred to as a DE signal), wherein the frequency and the frame rate of the VS signal are the same, the DE signal indicates data effectiveness, the number of rising edges of the DE signal in each frame is equal to the number of effective lines of a picture per frame, and the length of the DE signal (the number of clocks that are successively high) indicates the width of the picture.
In this embodiment, during the anomaly detection, the length of each DE signal, the number of rising edges of the DE signal of each frame of picture, and the number of rising edges of the VS signal within one second are counted, wherein the length of the DE signal should be equal to the width of the picture, the number of rising edges of the DE signal of each frame of picture should be equal to the height of the picture, and the number of rising edges of the VS signal within one second should be equal to the frame rate.
For example, taking the 8K60Hz signal as an example, the length of the DE signal should be equal to 7680, the number of rising edges of the DE signal per frame should be equal to 4320, and the number of rising edges of the VS signal in one second should be equal to 60. When any one of the 3 signals is abnormal, the time sequence signal is considered to be abnormal.
S103, jumping to enter a reset state when the time sequence signal is judged to be abnormal.
And S104, resetting the connection in a reset state to improve the signal quality of the received ultra-high definition video data.
In this embodiment, if an anomaly is detected, the system jumps to a reset state, for example, the CDR tracking state is retrained to improve the signal quality so that the subsequent video reception is more stable, and because the time for Training the CDR tracking and the ALN tracking is very short, the system can recover from the anomaly state only in about 20us, so that the user can only see the instantaneous jitter of the picture and then recover to normal, and the anomaly recovery mechanism greatly increases the reliability of the VbyOne interface and improves the viewing experience of the user.
In summary, the embodiment of the present invention determines whether the received timing signal is abnormal, and if there is an abnormality, the CDR tracing state is skipped to retrain to improve the signal quality, so that the reliability of the VbyOne interface is greatly improved by adding the automatic abnormality recovery mechanism, and the user experience can be greatly improved.
It should be noted that the present embodiment is applicable to all chips or FPGA designs having VbyOne interfaces. The method can also be used for other video interfaces such as HDMI and DisplayPort, because all video interfaces transmit images, the receiving end receives the VS signal, the HS signal and the DE signal as shown in fig. 3, and therefore, the signals can be used to check whether the transmission is abnormal, for example, when the time sequence signal received by the HDMI or DisplayPort receiving end is detected to be abnormal, the receiving end of the HDMI or DisplayPort can be reset, and then the connection is reestablished to recover the signal transmission, so that the recovery from the abnormal state is automatic, and the user experience is improved. The embodiment of the invention can also be used for video signal transmission with resolutions below 8K, 8K and above 8K, and the video transmission interface can be Vbyone, HDMI, DisplayPort, MIPI or LVDS and other interfaces.
Referring to fig. 4, a second embodiment of the present invention further provides an apparatus for improving reliability of ultra high definition signal transmission, including:
a timing signal obtaining unit 210, configured to obtain, in a preset state, a timing signal received by a video transmission interface of a display driver chip;
a timing detection unit 220, configured to determine whether the timing signal is abnormal;
a skipping unit 230, configured to skip to enter a reset state when it is determined that the timing signal is abnormal;
a reset unit 240 for resetting the connection in a reset state to improve the signal quality of the received ultra high definition video data.
Preferably, the video transmission interface is a VbyOne interface; the Normal working state is a Normal state, and the reset state is a CDR tracking state.
Preferably, the timing signals include a frame synchronization signal VS (hereinafter referred to as VS signal) and a data valid signal DE (hereinafter referred to as DE signal); the frequency and the frame rate of the VS signals are the same, the DE signal indicates that data are valid, the number of rising edges of the DE signal in each frame is equal to the number of valid lines of each frame, and the length of the DE signal indicates the width of the frame.
Preferably, the timing detecting unit 220 is specifically configured to:
and counting and monitoring the time sequence signals received by the Vbyone interface, and counting the length of each effective data signal DE, the number of rising edges of the DE signal of each frame of picture and the number of rising edges of the VS signal in one second.
And when any one of the length of each effective data signal DE signal, the number of rising edges of the DE signal of each frame of picture and the number of rising edges of the VS signal in one second is abnormal, judging that the time sequence signal is abnormal.
The third embodiment of the present invention also provides an apparatus for improving reliability of ultra high definition signal transmission, which includes a processor and a memory storing a computer program, where the computer program can be executed by the processor to implement the method for improving reliability of ultra high definition signal transmission as described above.
The fourth embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, where the computer program can be executed by a processor of a device in which the computer-readable storage medium is located, so as to implement the method for improving reliability of ultra high definition signal transmission as described above.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus and method embodiments described above are illustrative only, as the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for improving the reliability of ultra-high definition signal transmission is characterized by comprising the following steps:
acquiring a time sequence signal received by a video transmission interface of a display driving chip in a preset state;
judging whether the time sequence signal is abnormal or not;
when the time sequence signal is judged to be abnormal, jumping to enter a reset state;
the connection is reset in a reset state to improve the signal quality of the received ultra high definition video data.
2. The method for improving the reliability of ultra high definition signal transmission according to claim 1, wherein the video transmission interface is a VbyOne interface; the preset state is a Normal state, and the reset state is a CDR tracking state.
3. The method for improving transmission reliability of ultra high definition signals according to claim 1, wherein the determining whether the timing signal is abnormal specifically includes:
counting and monitoring the time sequence signals received by the Vbyone interface, and counting the length of each effective data signal DE, the number of rising edges of the effective signals DE of each frame of picture and the number of rising edges of the frame synchronization signals VS within one second;
and when any one of the length of each data effective signal DE, the number of rising edges of the effective signals DE of each frame of picture and the number of rising edges of the frame synchronizing signals VS within one second is abnormal, judging that the time sequence signal is abnormal.
4. An apparatus for improving reliability of ultra high definition signal transmission, comprising:
the time sequence signal acquisition unit is used for acquiring a time sequence signal received by a video transmission interface of the display driving chip in a preset state;
the time sequence detection unit is used for judging whether the time sequence signal is abnormal or not;
the skipping unit is used for skipping to enter a reset state when the time sequence signal is judged to be abnormal;
a reset unit for resetting the connection in a reset state to improve signal quality of the received ultra high definition video data.
5. The ultra high definition signal transmission reliability improving apparatus according to claim 5, wherein the video transmission interface is a VbyOne interface; the preset state is a Normal state, and the reset state is a CDR tracking state.
6. The ultra high definition signal transmission reliability improving apparatus according to claim 4, wherein the timing detecting unit is specifically configured to:
counting and monitoring the time sequence signals received by the Vbyone interface, and counting the length of each effective data signal DE, the number of rising edges of the effective signals DE of each frame of picture and the number of rising edges of the frame synchronization signals VS within one second;
and when any one of the length of each data effective signal DE, the number of rising edges of the effective signals DE of each frame of picture and the number of rising edges of the frame synchronizing signals VS within one second is abnormal, judging that the time sequence signal is abnormal.
7. An apparatus for improving reliability of ultra high definition signal transmission, comprising a processor and a memory storing a computer program executable by the processor to implement the ultra high definition signal transmission reliability improving method according to any one of claims 1 to 3.
8. A computer-readable storage medium, characterized in that a computer program is stored, which can be executed by a processor of a device in which the computer-readable storage medium is located, to implement the ultra high definition signal transmission reliability improvement method according to any one of claims 1 to 3.
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| CN202111609284.0A CN114363717A (en) | 2021-12-27 | 2021-12-27 | Method, device, equipment and medium for improving reliability of ultra-high definition signal transmission |
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| CN202111609284.0A CN114363717A (en) | 2021-12-27 | 2021-12-27 | Method, device, equipment and medium for improving reliability of ultra-high definition signal transmission |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871379A (en) * | 2012-12-14 | 2014-06-18 | 乐金显示有限公司 | Apparatus and method for controlling data interface |
| CN111757023A (en) * | 2020-07-01 | 2020-10-09 | 成都傅立叶电子科技有限公司 | FPGA-based video interface diagnosis method and system |
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- 2021-12-27 CN CN202111609284.0A patent/CN114363717A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871379A (en) * | 2012-12-14 | 2014-06-18 | 乐金显示有限公司 | Apparatus and method for controlling data interface |
| CN111757023A (en) * | 2020-07-01 | 2020-10-09 | 成都傅立叶电子科技有限公司 | FPGA-based video interface diagnosis method and system |
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Application publication date: 20220415 |