CN114363108A

CN114363108A - CAN bridge communication system, method, equipment and storage medium

Info

Publication number: CN114363108A
Application number: CN202111656290.1A
Authority: CN
Inventors: 不公告发明人
Original assignee: Mornsun Guangzhou Science and Technology Ltd
Current assignee: Mornsun Guangzhou Science and Technology Ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-04-15

Abstract

The invention relates to a CAN bridge communication system, a method, equipment and a storage medium. The system comprises: two microcontrollers which are respectively provided with two CAN interfaces; the two microcontrollers communicate through two pairs of peripheral SPI interfaces which are master and slave; the microcontroller is used for identifying a target CAN interface of data when the CAN interface or the peripheral SPI interface receives the data, and directly forwarding the data to the corresponding target CAN interface when the target CAN interface of the data is identified to be the CAN interface of the same microcontroller; and when the target CAN interface of the data is identified to be the CAN interface of another microcontroller, forwarding the data to the another microcontroller through the peripheral SPI interface. The invention reduces the time that the SPI single host communication needs to interrupt the auxiliary machine notification signal additionally, and ensures the high throughput of 6000fps while meeting the number of CAN channels, thereby weakening the limitation of the multi-channel CAN bridge in the aspect of microcontroller type selection.

Description

CAN bridge communication system, method, equipment and storage medium

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a CAN bridge communication system, method, device, and storage medium.

Background

CAN is a short name for Controller Area Network (CAN), is a serial communication protocol standardized by ISO internationally, and is one of the most widely used field buses internationally. The CAN bus communication interface inherits the functions of a physical layer and a data link layer of a CAN protocol and completes framing processing on communication data; the traditional station address coding is abandoned, and a communication data block is coded instead, so that the number of nodes in the network is theoretically unlimited; the CAN bus adopts a multi-master competition type bus structure and has the characteristics of serial bus and broadcast communication of multi-master station operation and decentralized arbitration.

The CAN bus data theory transmission distance is up to 10mm, which is far beyond various common serial port buses. It is noted that the maximum transmission rate that CAN be used by CAN is limited at different transmission rates. That is, the lower the transmission rate, the further the transmission distance, 10km transmission distance, often requires the bus rate to be reduced to 5 kbps. In connection with the comprehensiveness of the CAN bus and the diversity of application scenes, 5kbps is obviously insufficient, and at the moment, the CAN bridge is generated.

As shown in fig. 1, a block diagram of a conventional CAN bridge structure is shown, the CAN bridge generally has two, four, eight, etc. paths, and a conversion chip is additionally provided outside a CAN controller of a microcontroller to implement filtering, caching and forwarding of data on a CAN bus. This also means that, for each path of CAN, there is one more CAN controller peripheral device of the microcontroller, and at most there are two CAN controller peripheral devices of the mainstream microcontroller in the market, which also brings difficulty to the design of four or more CAN bridges.

Disclosure of Invention

The invention aims to overcome at least one defect in the prior art and provides a CAN bridge communication system, a method, equipment and a storage medium.

In order to achieve the purpose, the invention adopts the following technical scheme:

in a first aspect, a CAN-bridge communication system is provided, comprising:

two microcontrollers; each microcontroller is provided with two CAN interfaces, and each CAN interface of each microcontroller is used for being connected with one CAN transceiver module;

the two microcontrollers communicate through two pairs of peripheral SPI interfaces which are master and slave;

the CAN interface is used for receiving data sent by the CAN transceiving module;

the peripheral SPI interface is used for receiving data sent by another microcontroller or sending the data to another microcontroller;

the microcontroller is used for identifying a target CAN interface of data when the CAN interface or the peripheral SPI interface receives the data, and directly forwarding the data to the corresponding target CAN interface when the target CAN interface of the data is identified to be the CAN interface of the same microcontroller; and when the target CAN interface of the data is identified to be the CAN interface of another microcontroller, forwarding the data to the another microcontroller through the peripheral SPI interface.

Preferably, the microcontroller is further configured to store the received data into a corresponding array circular queue FIFO;

when the microcontroller is in a data receiving gap, the microcontroller is also used for circularly judging whether all array annular queue FIFOs of the microcontroller are not empty according to a preset judgment sequence;

if the array annular queue FIFO is judged to be not empty, the target CAN interface of the current data of the array annular queue FIFO is identified, the current data is directly forwarded to the corresponding target CAN interface, or the current data is forwarded to another microcontroller through an external SPI interface, and whether the array annular queue FIFO in the next judgment sequence is not empty is judged.

Preferably, the target CAN interface used by the microcontroller to identify the received data specifically is:

sequentially matching the target CAN interface of the current data with the CAN interfaces of the two microcontrollers according to a preset matching sequence;

and if the matching is successful, directly forwarding the current data to the corresponding target CAN interface, or forwarding the current data to another microcontroller through an external SPI interface and matching with the CAN interface in the next matching sequence until the matching with all CAN interfaces is finished.

Preferably, the two microcontrollers are a microcontroller MCU1 and a microcontroller MCU2, the microcontroller MCU1 is provided with a peripheral SPI1 interface and a peripheral SPI2 interface, and the microcontroller MCU2 is provided with a peripheral SPI3 interface and a peripheral SPI4 interface; two the microcontroller communicates through two pairs of peripheral SPI interfaces that are master and slave each other, specifically is: a clock pin SCK of the SPI1 interface is connected with a clock pin SCK of the SPI3 interface, and a data pin MOSI of the SPI1 interface is connected with a clock pin MOSI of the SPI3 interface; a clock pin SCK of the SPI2 interface is connected with a clock pin SCK of the SPI4 interface, and a data pin MOSI of the SPI2 interface is connected with a clock pin MOSI of the SPI4 interface; the SPI1 interface is used for forwarding data to the SPI3 interface, and the SPI2 interface is used for receiving data sent by the SPI4 interface.

In a second aspect, a CAN bridge communication method is provided, which is applied to a CAN bridge communication system, where the CAN bridge communication system includes:

the CAN bridge communication method comprises the following steps:

when the CAN interface or the peripheral SPI interface receives data, identifying a target CAN interface of the data;

when the target CAN interface of the data is identified to be the CAN interface of the same microcontroller, the data is directly forwarded to the corresponding target CAN interface;

and when the target CAN interface of the data is identified to be the CAN interface of another microcontroller, forwarding the data to the another microcontroller through the peripheral SPI interface.

Preferably, when the CAN interface or the peripheral SPI interface receives data, the method further includes:

storing the received data into a corresponding array circular queue FIFO;

when the microcontroller is in a data receiving gap, circularly judging whether all array circular queue FIFO of the microcontroller is not empty according to a preset judgment sequence;

Preferably, the identifying the target CAN interface of the received data specifically includes:

In a third aspect, a computer device is provided, comprising a memory storing a computer program and a processor implementing the steps of the CAN-bridge communication method as described above when the processor executes the computer program.

In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, realizes the steps of the CAN-bridge communication method as described above.

Compared with the prior art, the beneficial effect of this scheme does:

the product of the invention adopts double master control microcontrollers, and two pairs of high-speed serial peripheral SPI interfaces which are master and slave are adopted between the double master control microcontrollers, thereby reducing the time for the communication of a single SPI host computer to additionally interrupt the notification signals of slave computers, widening the selectable microcontroller type of a multi-channel CAN bridge and weakening the restriction of the peripheral quantity of the CAN interfaces on master control type selection; because of the time required by data transmission in the data receiving and sending processes, the invention introduces the special treatment of the array circular queue FIFO to ensure that the data transmitted on the bus can not conflict at the same time, and the reliable storage and forwarding of the data can be satisfied under the conditions of high throughput or high-speed receiving and low-speed forwarding.

Drawings

FIG. 1 is a block diagram of a conventional CAN bridge architecture of the prior art;

fig. 2 is a connection block diagram of a CAN bridge communication system according to a first embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a data processing flow of the microprocessor MCU1 according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating a data processing flow of the microprocessor MCU2 according to the second embodiment of the present invention.

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention:

first embodiment

In order to expand the CAN communication channel, a master controller is usually connected with a plurality of slave controllers in the prior art, so that the expansion of the CAN communication channel is realized, however, because the plurality of slave controllers are not connected, when data received by a certain slave controller needs to be sent to other slave controllers, the data needs to be sent to the master controller for processing and then sent to the corresponding slave controllers, the master-slave mode means that all data processing needs to pass through the master controller, so that the master controller is equivalent to an intermediate processing module, and the data conversion complexity and the conversion transmission time are increased; furthermore, the main controller may fail, which may cause the entire communication system to crash.

In addition, because there are only two CAN interfaces of the mainstream microcontroller in the market, the difficulty is brought to the design of four or more CAN bridges and the selection of products is limited.

Referring to fig. 2, fig. 2 is a connection block diagram of the CAN bridge communication system according to the present embodiment, and in order to solve the above problem, in the present embodiment, a CAN bridge communication system is provided, including:

Specifically, due to the comprehensiveness of the CAN bus and the diversity of application scenarios, the application requirements of four or more CAN bridges are obvious, while microcontrollers with 4 or more CAN controllers are rare, few existing models are available, but the price is high. The CAN bridge communication system of the embodiment comprises two microcontrollers, each microcontroller only needs to be provided with two CAN interfaces, and each CAN interface is externally connected with a CAN transceiver module, so that the design difficulty and the limitation of model selection of four or more CAN bridges CAN be avoided, and the product CAN be widely applied; after the product is electrified, the two microcontrollers work simultaneously, and the CAN interface of each path is the same as the program, so that the reusability and the maintainability of the system are improved; when the microcontroller receives data from the CAN interface or the peripheral SPI interface, the target CAN interface of the data is identified, wherein the target CAN interface is the CAN interface to which the data needs to be forwarded; when the target CAN interface of the data is identified to be the CAN interface of the same microcontroller, the data is directly forwarded to the corresponding target CAN interface; when the target CAN interface of the data is identified to be a CAN interface of another microcontroller, the data is forwarded to the other microcontroller through a peripheral SPI interface; two microcontrollers are the master and slave each other, and every microcontroller all is equipped with two high-speed serial peripheral SPI interfaces, adopts two pairs of high-speed serial peripheral SPI interface communication between two microcontrollers, each other is the master and slave, and the application of high-speed serial peripheral SPI interface communication has reduced the time that SPI single host computer communication needs extra interrupt processing to follow quick-witted notice signal, and has reliably guaranteed the data interaction rate, adopts two master control peripheral SPI interfaces to communicate moreover, and its communication rate can be up to 30Mbps, has reliably guaranteed the high throughput of product.

Moreover, compared with UART communication and IIC communication, the SPI communication has higher speed, particularly for IIC communication, in point-to-point communication, an SPI interface does not need addressing operation, the protocol is simple, the communication is efficient, and the high throughput of products can be effectively ensured.

As a specific implementation of the connection between the two microcontrollers, in this embodiment, the two microcontrollers are a microcontroller MCU1 and a microcontroller MCU 2; the microcontroller MCU1 is provided with a peripheral SPI1 interface and a peripheral SPI2 interface, and the microcontroller MCU2 is provided with a peripheral SPI3 interface and a peripheral SPI4 interface; two the microcontroller communicates through two pairs of peripheral SPI interfaces that are master and slave each other, specifically is: a clock pin SCK of the SPI1 interface is connected with a clock pin SCK of the SPI3 interface, and a data pin MOSI of the SPI1 interface is connected with a clock pin MOSI of the SPI3 interface; a clock pin SCK of the SPI2 interface is connected with a clock pin SCK of the SPI4 interface, and a data pin MOSI of the SPI2 interface is connected with a clock pin MOSI of the SPI4 interface; the SPI1 interface is used for forwarding data to the SPI3 interface, the SPI2 interface is used for receiving data sent by the SPI4 interface, the SPI4 interface is used for forwarding data to the SPI2 interface, and the SPI3 interface is used for receiving data sent by the SPI1 interface.

Specifically, the SPI1 interface of the microcontroller MCU1 serves as a master, and the microcontroller SPI2 interface serves as a slave; the SPI3 interface of the MCU2 acts as a slave and the SPI4 interface acts as a master.

Because data transmission needs a certain time in the processes of receiving and sending data, if data is sent or received simultaneously, data collision is easy to happen in the transmission process, and the timeliness of data transmission cannot be guaranteed; to solve this problem, in this embodiment, the microcontroller is further configured to store the received data into the corresponding array circular queue FIFO;

Specifically, after receiving data, the microcontroller transfers the data to a corresponding array circular queue FIFO, and sends the data to a corresponding CAN interface in a first-in first-out mode or sends the data to another microcontroller through a peripheral SPI interface, thereby ensuring that the data transmitted on a bus do not conflict at the same time, and satisfying the reliable storage and forwarding of the data under the conditions of high throughput, high-speed receiving and low-speed forwarding.

In this embodiment, the target CAN interface used by the microcontroller to identify the received data specifically includes:

Specifically, the two microcontrollers are a microcontroller MCU1 and a microcontroller MCU2, the microcontroller MCU1 is provided with CAN interfaces CAN1 and CAN2, and the microcontroller MCU2 is provided with CAN interfaces CAN3 and CAN 4; FIFO1 is an array ring queue corresponding to CAN1, FIFO2 is an array ring queue corresponding to CAN2, FIFO3 is an array ring queue corresponding to SPI2 interface, and the following description takes microcontroller MCU1 as an example:

specifically, when the CAN1 receives a frame of CAN data, the FIFO1 of the microcontroller MCU1 stores the frame of CAN data; when the CAN2 receives a frame of CAN data, the FIFO2 of the microcontroller MCU1 stores the frame of data; when the SPI2 interface receives a frame of CAN data, the FIFO3 of the microcontroller MCU1 stores the frame data; when the microcontroller MCU1 is in a gap for receiving data, the main program of the microcontroller MCU1 circularly determines whether the FIFO1, the FIFO2, and the FIFO3 are non-empty according to a preset determination sequence, which can be specifically set according to requirements; specifically, the preset determination sequence may be, but is not limited to, the sequence of the FIFO1, the FIFO2, and the FIFO 3; if one of the array ring queues is determined to be non-empty, the target CAN interfaces of the current data in the non-empty array ring queue are sequentially matched with the CAN interfaces of the two microcontrollers according to a preset matching sequence, specifically, the preset matching sequence of the microcontroller MCU1 CAN be but not limited to the sequence of CAN1, CAN2, CAN3 and CAN4, and CAN be specifically set according to requirements.

Referring to fig. 3, a schematic diagram of a data processing flow of the microcontroller MCU1 is shown, where an execution main body is a main program in the microcontroller MCU1, and the main program determines matching of each array circular queue and a target CAN interface of the frame of CAN data according to a loop, including the following steps:

s100, storing the received CAN data in a corresponding array annular queue;

in the gaps where the microcontroller MCU1 receives data, the following steps are performed:

s101, judging whether the FIFO1 is not empty, if so, executing a step S201, otherwise, executing a step S102;

s102, judging whether the FIFO2 is not empty, if so, executing the step S201, otherwise, executing the step S103;

s103, judging whether the FIFO3 is not empty, if so, executing the step S201, otherwise, executing the step S101;

s201, judging whether a target CAN interface of the frame of CAN data is CAN1, if so, directly forwarding the frame of CAN data to CAN1 and executing a step S202, otherwise, executing the step S202;

s202, judging whether a target CAN interface of the frame of CAN data is CAN2, if so, directly forwarding the frame of CAN data to CAN2, executing a step S203, and if not, executing the step S203;

s203, judging whether a target CAN interface of the frame of CAN data is CAN3, if so, forwarding the frame of CAN data to a microcontroller MCU2 through an external SPI1 interface, and executing a step S204, otherwise, executing the step S204;

and S204, judging whether the target CAN interface of the frame of CAN data is CAN4, if so, forwarding the frame of CAN data to the microcontroller MCU2 through the peripheral SPI1 interface, terminating the matching of the target CAN interface and returning to the step S101, otherwise, terminating the matching of the target CAN interface and returning to the step S101.

Second embodiment

In this embodiment, a method for communicating based on a dual master CAN bridge is provided, which is applied to a CAN bridge communication system according to the first embodiment, where the CAN bridge communication system includes:

the CAN bridge communication method comprises the following steps:

In this embodiment, when the self CAN interface or the peripheral SPI interface receives data, the method further includes:

storing the received data into a corresponding array circular queue FIFO;

In this embodiment, the identifying the target CAN interface of the received data specifically includes:

sequentially matching a target CAN interface of current data with two CAN interfaces which are microcontrollers according to a preset matching sequence;

Specifically, the two microcontrollers are a microcontroller MCU1 and a microcontroller MCU2, the microcontroller MCU1 is provided with CAN interfaces CAN1 and CAN2, and the microcontroller MCU2 is provided with CAN interfaces CAN3 and CAN 4; FIFO4 is an array ring queue corresponding to CAN3, FIFO5 is an array ring queue corresponding to CAN4, FIFO6 is an array ring queue corresponding to SPI3 interface, and the following description takes microcontroller MCU2 as an example:

specifically, when the CAN3 receives a frame of CAN data, the FIFO4 of the microcontroller MCU2 stores the frame of CAN data; when the CAN4 receives a frame of CAN data, the FIFO5 of the microcontroller MCU2 stores the frame of data; when the SPI3 interface receives a frame of CAN data, the FIFO6 of the microcontroller MCU2 stores the frame data; when the microcontroller MCU2 is in a gap for receiving data, the main program of the microcontroller MCU2 circularly determines whether the FIFO4, the FIFO5, and the FIFO6 are non-empty according to a preset determination sequence, which can be specifically set according to requirements; specifically, the preset determination sequence may be, but is not limited to, the sequence of the FIFO4, the FIFO5, and the FIFO 6; if one of the array ring queues is determined to be non-empty, the target CAN interfaces of the current data in the non-empty array ring queue are sequentially matched with the CAN interfaces of the two microcontrollers according to a preset matching sequence, specifically, the preset matching sequence of the microcontroller MCU2 CAN be but not limited to the sequence of CAN1, CAN2, CAN3 and CAN4, and CAN be specifically set according to requirements.

Referring to fig. 4, fig. 4 is a data processing flow chart of the microcontroller MCU2, where the main execution body is a main program in the microcontroller MCU2, and the main program determines matching of each array ring queue and the target CAN interface of the frame of CAN data to a loop including the following steps:

D100. storing the received CAN data in only a corresponding array annular queue;

in the gaps where the microcontroller MCU2 receives data, the following steps are performed:

D101. judging whether the FIFO4 is not empty, if so, executing the step D201, otherwise, executing the step D102;

D102. judging whether the FIFO5 is not empty, if so, executing the step D201, otherwise, executing the step D103;

D103. judging whether the FIFO6 is not empty, if yes, executing the step D201, and if not, executing the step D101;

D201. judging whether the target CAN interface of the frame of CAN data is CAN1, if so, forwarding the frame of CAN data to the microcontroller MCU1 through the peripheral SPI1 interface, and executing step D202, otherwise, executing step D202;

D202. judging whether the target CAN interface of the frame of CAN data is CAN2, if so, forwarding the frame of CAN data to the microcontroller MCU1 through the peripheral SPI1 interface, and executing step D203, otherwise, executing step D203;

D203. judging whether the target CAN interface of the frame of CAN data is CAN3, if so, directly forwarding the frame of CAN data to CAN3 and executing step D204, otherwise, executing step D204;

D204. and D, judging whether the target CAN interface of the frame of CAN data is CAN4, if so, directly forwarding the frame of CAN data to CAN4, terminating the matching of the target CAN interface and returning to the step D101, and if not, terminating the matching of the target CAN interface and returning to the step D101.

Third embodiment

In this embodiment, a computer device, which may be a terminal, is provided that includes a processor, a memory, a communication interface, a display screen, and an input device connected through a system bus. Wherein the processor of the computer device is used to provide computing and control capabilities, the memory comprises an operating system in a non-volatile storage medium and an environment for the computer program to run, the communication interface is used to communicate with an external terminal in a wired or wireless manner, which may be implemented by WiFi, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a CAN-bridge communication method according to the second embodiment.

Fourth embodiment

In this embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, implements a CAN-bridge communication method according to the second embodiment.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention claims should be included in the protection scope of the present invention claims.

Claims

1. A CAN-bridge communication system, comprising: two microcontrollers; each microcontroller is provided with two CAN interfaces, and each CAN interface of each microcontroller is used for being connected with one CAN transceiver module;

2. The CAN-bridge communication system of claim 1, wherein said microcontroller is further configured to store received data in a corresponding array circular queue FIFO;

3. The CAN-bridge communication system according to any of claims 1 or 2, wherein the target CAN interface used by the microcontroller for identifying the received data is specifically:

4. The CAN bridge communication system of claim 3, wherein the two microcontrollers are microcontroller MCU1 and microcontroller MCU2, microcontroller MCU1 is provided with peripheral SPI1 interface and peripheral SPI2 interface, microcontroller MCU2 is provided with peripheral SPI3 interface and peripheral SPI4 interface; two the microcontroller communicates through two pairs of peripheral SPI interfaces that are master and slave each other, specifically is: a clock pin SCK of the SPI1 interface is connected with a clock pin SCK of the SPI3 interface, and a data pin MOSI of the SPI1 interface is connected with a clock pin MOSI of the SPI3 interface; a clock pin SCK of the SPI2 interface is connected with a clock pin SCK of the SPI4 interface, and a data pin MOSI of the SPI2 interface is connected with a clock pin MOSI of the SPI4 interface; the SPI1 interface is used for forwarding data to the SPI3 interface, and the SPI2 interface is used for receiving data sent by the SPI4 interface.

5. A CAN bridge communication method is applied to a CAN bridge communication system, and the CAN bridge communication system comprises:

the CAN bridge communication method comprises the following steps:

6. The CAN bridge communication method of claim 5, further comprising:

storing the received data into a corresponding array circular queue FIFO;

7. The CAN bridge communication method according to any of claims 5 or 6, wherein the identifying a target CAN interface of the received data specifically comprises:

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method according to any of claims 5-7 when executing the computer program.

9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 5 to 7.