CN114361202A - Phase change memory cell and manufacturing method thereof - Google Patents
Phase change memory cell and manufacturing method thereof Download PDFInfo
- Publication number
- CN114361202A CN114361202A CN202111523997.5A CN202111523997A CN114361202A CN 114361202 A CN114361202 A CN 114361202A CN 202111523997 A CN202111523997 A CN 202111523997A CN 114361202 A CN114361202 A CN 114361202A
- Authority
- CN
- China
- Prior art keywords
- phase change
- material layer
- change memory
- substrate
- change material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008859 change Effects 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000012782 phase change material Substances 0.000 claims abstract description 87
- 239000000463 material Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000011049 filling Methods 0.000 claims abstract description 30
- 238000003860 storage Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 18
- 239000007772 electrode material Substances 0.000 claims description 13
- 238000005253 cladding Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 93
- 238000010586 diagram Methods 0.000 description 15
- 238000007740 vapor deposition Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000007769 metal material Substances 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 239000000956 alloy Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 150000002736 metal compounds Chemical class 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 150000001247 metal acetylides Chemical class 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910005872 GeSb Inorganic materials 0.000 description 1
- 229910005866 GeSe Inorganic materials 0.000 description 1
- 229910005900 GeTe Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- -1 chalcogenide compound Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013065 commercial product Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
技术领域technical field
本发明涉及微电子技术领域,特别是涉及一种相变存储单元及其制作方法。The invention relates to the technical field of microelectronics, in particular to a phase-change memory cell and a manufacturing method thereof.
背景技术Background technique
相变存储器技术是基于Ovshinsky在20世纪60年代末(Phys.Rev.Lett.,21,14501453,1968)70年代初(Appl.Phys.Lett.,18,254257,1971)提出的相变薄膜可以应用于相变存储介质的构想建立起来的,是一种价格便宜、性能稳定的存储器件。相变存储器可以做在硅晶片衬底上,其关键材料是可记录的相变薄膜、加热电极材料11、绝热材料和引出电极材的研究热点也就围绕其器件工艺展开:器件的物理机制研究,包括如何减小器件料等。相变存储器的基本原理是利用电脉冲信号作用于器件单元上,使相变材料在非晶态与多晶态之间发生可逆相变,通过分辨非晶态时的高阻与多晶态时的低阻,可以实现信息的写入、擦除和读出操作。The phase change memory technology is based on the phase change thin film proposed by Ovshinsky in the late 1960s (Phys. Rev. Lett., 21, 14501453, 1968) and the early 1970s (Appl. Phys. The concept of applying the phase change storage medium is established, which is a storage device with low price and stable performance. Phase change memory can be made on silicon wafer substrate, and its key materials are recordable phase change films, heating electrode materials11, thermal insulation materials and lead-out electrode materials. , including how to reduce device material, etc. The basic principle of phase change memory is to use electrical pulse signals to act on the device unit to make the phase change material undergo a reversible phase transition between amorphous and polycrystalline states. The low resistance can realize the writing, erasing and reading operations of information.
相变存储器由于具有高速读取、高可擦写次数、非易失性、元件尺寸小、功耗低、抗强震动和抗辐射等优点,被国际半导体工业协会认为最有可能取代目前的闪存存储器而成为未来存储器主流产品和最先成为商用产品的器件。Phase change memory is considered by the International Semiconductor Industry Association as the most likely to replace the current flash memory due to its advantages of high-speed reading, high rewritable times, non-volatile, small component size, low power consumption, strong vibration resistance and radiation resistance. The memory will become the mainstream memory product in the future and the first device to become a commercial product.
相变存储器的读、写、擦操作就是在器件单元上施加不同宽度和高度的电压或电流脉冲信号:擦操作(RESET),当加一个短且强的脉冲信号使器件单元中的相变材料温度升高到熔化温度以上后,再经过快速冷却从而实现相变材料多晶态到非晶态的转换,即“1”态到“0”态的转换;写操作(SET),当施加一个长且中等强度的脉冲信号使相变材料温度升到熔化温度之下、结晶温度之上后,并保持一段时间促使晶核生长,从而实现非晶态到多晶态的转换,即“0”态到“1”态的转换;读操作,当加一个对相变材料的状态不会产生影响的很弱的脉冲信号后,通过测量器件单元的电阻值来读取它的状态。The read, write and erase operations of the phase change memory are to apply voltage or current pulse signals of different widths and heights on the device unit: erase operation (RESET), when a short and strong pulse signal is added to make the phase change material in the device unit After the temperature rises above the melting temperature, it is rapidly cooled to realize the transformation from the polycrystalline state to the amorphous state of the phase change material, that is, the transformation from the "1" state to the "0" state; the write operation (SET), when a A long and medium-intensity pulse signal raises the temperature of the phase change material below the melting temperature and above the crystallization temperature, and maintains it for a period of time to promote the growth of the crystal nucleus, thereby realizing the transformation from amorphous to polycrystalline state, that is, "0" State to "1" state conversion; read operation, after adding a very weak pulse signal that will not affect the state of the phase change material, read its state by measuring the resistance value of the device unit.
存储器的研究一直朝着高速、高密度、低功耗、高可靠性的方向发展。目前世界上从事相变存储器研发工作的机构大多数是半导体行业的大公司,他们关注的焦点之一是如何减小相变存储器的加热电极尺寸,目前比较普遍采用的是三星公司的侧壁接触型加热电极(Proc.Symp.Very Large Scale Integr.(VLSI)Technol.,2003:175-176)、环形加热电极(Jpn.J.Appl.Phys.,2006,45(4B):3233-3237)与刀片状加热电极(IEEE ConferenceProceedings ofInternational Electron Devices Meeting,2011,3.1.1-3.1.4)和意法半导体公司的μ型加热电极(Proc.Symp.Very Large Scale Integr.(VLSI)Technol.,2004,3.1:18-19),但上述结构的缺点是主要靠减小电极尺寸实现低功耗,而相变材料的尺寸都比较大,加上选通管对相变存储器的密度有重大影响,OTS(Ovonic ThresholdSwitching,奥里弗阈值转换开关)作为一种新型选通器件能极大的提升存储器的密度,提出一种新的纳米器件单元结构以解决上述技术问题实属必要。The research of memory has been developing in the direction of high speed, high density, low power consumption and high reliability. At present, most of the institutions engaged in the research and development of phase change memory in the world are large companies in the semiconductor industry. One of the focuses of their attention is how to reduce the size of the heating electrode of the phase change memory. Type heating electrode (Proc.Symp.Very Large Scale Integr.(VLSI)Technol., 2003:175-176), annular heating electrode (Jpn.J.Appl.Phys.,2006,45(4B):3233-3237) With blade-shaped heater electrode (IEEE Conference Proceedings of International Electron Devices Meeting, 2011, 3.1.1-3.1.4) and STMicroelectronics' μ-type heater electrode (Proc. Symp. Very Large Scale Integr. (VLSI) Technol., 2004 , 3.1:18-19), but the disadvantage of the above structure is that low power consumption is mainly achieved by reducing the size of the electrode, while the size of the phase change material is relatively large, and the gate tube has a significant impact on the density of the phase change memory, OTS (Ovonic Threshold Switching, Oliver Threshold Switching) as a new type of gate device can greatly improve the density of memory, it is necessary to propose a new nano-device unit structure to solve the above technical problems.
发明内容SUMMARY OF THE INVENTION
本发明所要解决的技术问题是提供一种相变存储单元及其制作方法,能够有效缩小相变存储单元的的相变区域。The technical problem to be solved by the present invention is to provide a phase-change memory cell and a manufacturing method thereof, which can effectively reduce the phase-change region of the phase-change memory cell.
本发明解决其技术问题所采用的技术方案是:提供一种相变存储单元,包括:The technical solution adopted by the present invention to solve the technical problem is to provide a phase-change storage unit, comprising:
衬底;substrate;
至少一个下电极,所述下电极设置于衬底中,所述下电极的上接触面暴露于衬底外且与衬底上表面持平;at least one lower electrode, the lower electrode is arranged in the substrate, and the upper contact surface of the lower electrode is exposed outside the substrate and is level with the upper surface of the substrate;
相变材料层,所述相变材料层水平部分与下电极连接,所述相变材料层为L形;a phase change material layer, the horizontal part of the phase change material layer is connected to the lower electrode, and the phase change material layer is L-shaped;
填充材料,所述填充材料设置于相变材料层竖直部分上方,并与相变材料层一同构成相变存储结构;a filling material, the filling material is arranged above the vertical part of the phase change material layer, and together with the phase change material layer constitutes a phase change memory structure;
上电极,所述上电极设置于相变材料层的上方。an upper electrode, the upper electrode is arranged above the phase change material layer.
所述填充材料为依次填充的隔离材料和OTS材料。The filling material is an isolation material and an OTS material that are filled in sequence.
所述填充材料为加热电极材料。The filling material is a heating electrode material.
还包括支撑结构,所述支撑结构设置于衬底上、且位于下电极的一侧,所述支撑结构与所述相变存储结构连接。A support structure is also included, the support structure is disposed on the substrate and located at one side of the lower electrode, and the support structure is connected with the phase change memory structure.
当所述下电极个数为复数时,还包括隔离槽,所述隔离槽用于将相变材料层进行分离。When the number of the lower electrodes is plural, an isolation groove is also included, and the isolation groove is used for separating the phase change material layers.
还包括绝缘层,所述绝缘层填充于隔离槽,并填充至与相变存储结构的上表面齐平。It also includes an insulating layer, the insulating layer is filled in the isolation trench and filled to be flush with the upper surface of the phase change memory structure.
还包括包覆层,所述包覆层覆盖于相变存储结构上。Also included is a cladding layer overlying the phase change memory structure.
本发明解决其技术问题所采用的技术方案是:提供一种相变存储单元制作方法,包括:The technical solution adopted by the present invention to solve the technical problem is to provide a method for manufacturing a phase-change memory cell, including:
步骤(1):在衬底中镶嵌至少一个下电极,并使下电极的上接触面暴露于衬底外且与衬底上表面持平;Step (1): at least one lower electrode is embedded in the substrate, and the upper contact surface of the lower electrode is exposed to the outside of the substrate and is level with the upper surface of the substrate;
步骤(2):在所述衬底上、且在所述下电极的一侧设置一支撑结构;Step (2): a support structure is arranged on the substrate and on one side of the lower electrode;
步骤(3):在所述下电极的上接触面、且在支撑结构的侧壁表面设置一L形的相变材料层;Step (3): disposing an L-shaped phase change material layer on the upper contact surface of the lower electrode and on the sidewall surface of the support structure;
步骤(4):在所述相变材料层沿平行于支撑结构的侧壁方向进行刻蚀,形成隔离槽,并使用绝缘层在刻蚀好的相变材料层周围空间和隔离槽周围空间进行填充;Step (4): Etch the phase change material layer along the sidewall direction parallel to the support structure to form an isolation groove, and use an insulating layer to perform etching in the space around the etched phase change material layer and the space around the isolation groove. filling;
步骤(5):对所述绝缘层进行抛光,抛光至绝缘层上表面、支撑结构上表面、相变材料层上表面持平;Step (5): polishing the insulating layer until the upper surface of the insulating layer, the upper surface of the support structure, and the upper surface of the phase change material layer are flat;
步骤(6):在抛光好的相变材料层的上方进行自对准刻蚀,形成限定型孔;Step (6): performing self-aligned etching on the top of the polished phase change material layer to form a defined hole;
步骤(7):在所述限定型孔中放置填充材料,所述填充材料与相变材料层一同构成相变存储结构;Step (7): placing a filling material in the defined hole, and the filling material and the phase change material layer together constitute a phase change memory structure;
步骤(8):在所述填充材料的上表面设置上电极。Step (8): disposing an upper electrode on the upper surface of the filling material.
所述步骤(3)和步骤(4)之间还包括:在所述相变材料层外周覆盖一包覆层。Between the step (3) and the step (4), the method further includes: covering the outer periphery of the phase change material layer with a cladding layer.
所述填充材料为依次填充的隔离材料和OTS材料或加热电极材料。The filling material is an isolation material and an OTS material or a heating electrode material filled in sequence.
有益效果beneficial effect
由于采用了上述的技术方案,本发明与现有技术相比,具有以下的优点和积极效果:本发明的相变存储单元中可以采用刀片状相变材料形成的1S1R相变单元结构(即设置隔离材料和OTS材料),由于1S1R相变单元结构的厚度尺寸非常小且容易控制,从而可实现接触面最小化,达到进一步缩小相变存储单元的相变区域的目的,从而提高相变速度、降低器件功耗以及提高相变存储器的密度;本发明的相变存储单元中还可以采用刀片状相变材料形成的限定性单元结构(即设置加热电极材料),由于限定性单元结构的厚度尺寸非常小且容易控制,从而可实现接触面最小化,达到进一步缩小相变存储单元的相变区域的目的,从而提高相变速度,并能够有效降低器件功耗。Due to the adoption of the above technical solutions, the present invention has the following advantages and positive effects compared with the prior art: the phase change memory cell of the present invention can adopt a 1S1R phase change cell structure formed by a blade-shaped phase change material (ie, set isolation material and OTS material), because the thickness of the 1S1R phase change unit structure is very small and easy to control, the contact surface can be minimized, and the purpose of further reducing the phase change area of the phase change memory cell can be achieved, thereby improving the phase change speed, Reduce the power consumption of the device and increase the density of the phase change memory; the phase change memory cell of the present invention can also use a limited cell structure formed by a blade-shaped phase change material (that is, provided with a heating electrode material), due to the thickness of the limited cell structure. It is very small and easy to control, so that the contact surface can be minimized, and the purpose of further reducing the phase change area of the phase change memory cell can be achieved, thereby increasing the phase change speed and effectively reducing the power consumption of the device.
附图说明Description of drawings
图1是本发明实施方式的在衬底中设置下电极图示意图;FIG. 1 is a schematic diagram of setting a lower electrode in a substrate according to an embodiment of the present invention;
图2是本发明实施方式的在衬底上设置支撑材料示意图;2 is a schematic diagram of setting a support material on a substrate according to an embodiment of the present invention;
图3是本发明实施方式的在衬底上设置支撑结构示意图;3 is a schematic diagram of a support structure provided on a substrate according to an embodiment of the present invention;
图4是本发明实施方式的图3所示结构的俯视图;4 is a top view of the structure shown in FIG. 3 according to an embodiment of the present invention;
图5是本发明实施方式的支撑结构侧壁表面及下电极上方设置相变材料层示意图;5 is a schematic diagram of disposing a phase change material layer on the surface of the sidewall of the support structure and above the lower electrode according to an embodiment of the present invention;
图6是本发明实施方式的在相变材料层表面涂覆包覆层的示意图;6 is a schematic diagram of coating a coating layer on the surface of a phase change material layer according to an embodiment of the present invention;
图7是本发明实施方式的在支撑结构之间开设隔离槽的示意图;7 is a schematic diagram of opening an isolation groove between support structures according to an embodiment of the present invention;
图8是本发明实施方式的在隔离槽中沉积绝缘层的示意图;8 is a schematic diagram of depositing an insulating layer in an isolation trench according to an embodiment of the present invention;
图9是本发明实施方式使隔离槽中沉积绝缘层平坦化的示意图;9 is a schematic diagram of planarizing an insulating layer deposited in an isolation trench according to an embodiment of the present invention;
图10是本发明实施方式的在在相变材料层上刻蚀出限定型孔的示意图;10 is a schematic diagram of etching a defined hole on a phase change material layer according to an embodiment of the present invention;
图11是本发明实施方式的在限定型孔中沉积填充材料(隔离材料和OTS材料)示意图;11 is a schematic diagram of depositing filling materials (isolating materials and OTS materials) in a defined hole according to an embodiment of the present invention;
图12是本发明实施方式的设置用于制成上电极的沉积金属层示意图;12 is a schematic diagram of a deposited metal layer configured to form an upper electrode according to an embodiment of the present invention;
图13是本发明实施方式的在沉积金属层上刻蚀出上电极示意图;13 is a schematic diagram of etching an upper electrode on a deposited metal layer according to an embodiment of the present invention;
图14是本发明实施方式的在限定型孔中沉积填充材料(加热电极材料)示意图;14 is a schematic diagram of depositing a filling material (heating electrode material) in a defined hole according to an embodiment of the present invention;
图15是本发明实施方式的另一个设置用于制成上电极的沉积金属层示意图;15 is a schematic diagram of another deposited metal layer configured to form an upper electrode according to an embodiment of the present invention;
图16是本发明实施方式的另一个沉积金属层上刻蚀出上电极示意图。FIG. 16 is a schematic diagram of etching an upper electrode on another deposited metal layer according to an embodiment of the present invention.
图示:1、衬底,2、下电极,3、支撑结构,4、相变材料层,5、包覆层,6、隔离槽,7、绝缘层,8、隔离材料,9、OTS材料,10、上电极,11、加热电极材料。Illustration: 1. Substrate, 2. Lower electrode, 3. Supporting structure, 4. Phase change material layer, 5. Cladding layer, 6. Isolation groove, 7. Insulation layer, 8. Isolation material, 9. OTS material , 10, the upper electrode, 11, the heating electrode material.
具体实施方式Detailed ways
下面结合具体实施例,进一步阐述本发明。应理解,这些实施例仅用于说明本发明而不用于限制本发明的范围。此外应理解,在阅读了本发明讲授的内容之后,本领域技术人员可以对本发明作各种改动或修改,这些等价形式同样落于本申请所附权利要求书所限定的范围。The present invention will be further described below in conjunction with specific embodiments. It should be understood that these examples are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.
本发明的实施方式涉及一种相变存储单元,包括:Embodiments of the present invention relate to a phase change memory cell comprising:
衬底1;
至少一个下电极2,所述下电极2设置于衬底1中,所述下电极2的上接触面暴露于衬底1外且与衬底1上表面持平;at least one
相变材料层4,所述相变材料层4水平部分与下电极2连接,所述相变材料层4为L形;The phase change material layer 4, the horizontal part of the phase change material layer 4 is connected to the
填充材料,所述填充材料设置于相变材料层4竖直部分上方,并与相变材料层4一同构成相变存储结构;Filling material, the filling material is arranged above the vertical part of the phase change material layer 4, and together with the phase change material layer 4 constitutes a phase change memory structure;
上电极10,所述上电极10设置于相变材料层4的上方。The upper electrode 10 is disposed above the phase change material layer 4 .
当所述填充材料为依次填充的隔离材料8和OTS材料9,可以构建1S1R相变单元结构;当所述填充材料为加热电极材料11,可以构建限定性单元结构。When the filling material is the isolation material 8 and the OTS material 9 filled in sequence, a 1S1R phase-change cell structure can be constructed; when the filling material is the heating electrode material 11 , a limited cell structure can be constructed.
还包括支撑结构3,所述支撑结构3设置于衬底1上、且位于下电极2的一侧,所述支撑结构3与所述相变存储结构连接。A
当所述下电极2个数为复数时,还包括隔离槽6,所述隔离槽6用于将相变材料层4进行分离。When the number of the
还包括绝缘层7,所述绝缘层7填充于隔离槽6,并填充至与相变存储结构的上表面齐平。An insulating layer 7 is also included, and the insulating layer 7 is filled in the
还包括包覆层5,所述包覆层5覆盖于相变存储结构上。It also includes a cladding layer 5 covering the phase change memory structure.
本发明的实施方式涉及一种相变存储单元制作方法,包括:Embodiments of the present invention relate to a method for fabricating a phase-change memory cell, including:
步骤(1):如图1所示,在衬底1中镶嵌至少一个下电极2,所述下电极2的上接触面均暴露于衬底1外且与衬底1上表面持平。Step (1): As shown in FIG. 1 , at least one
本实施方式中,在衬底1中形成至少四个下电极2,各下电极2之间呈至少两行及至少两列的点阵式分布。In this embodiment, at least four
具体地,所述衬底1为常规半导体衬底,可以采用如Si、Ge、GaN等材料。制备下电极2的方法可以为溅射法、蒸发法、化学气相沉积法、等离子体增强化学气相沉积法、低压化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法和原子层沉积法中的任意一种。所述下电极2的材料可以为单金属材料W、Pt、Au、Ti、Al、Ag、Cu、Ta和Ni中的任意一种,或由其中至少两种单金属材料组合成的合金材料,或是单金属材料的氮化物或氧化物。Specifically, the
作为示例,本实施方式采用化学气相沉积法(CVD)制备由单金属材料W制成的下电极2,下电极2的直径为70nm,高度为150nm。在其它实施例中,下电极2也可以采用其它尺寸。As an example, the present embodiment adopts chemical vapor deposition (CVD) to prepare the
步骤(2):在所述衬底1上设置若干支撑结构3,所述支撑结构3间隔地分布在下电极2形成的队列(即点阵式分布的列方向为队列)之间。Step (2): A number of supporting
作为示例,如图2所示,可以在衬底1上设置一整块支撑结构3,然后对其进行切割得到如图3所示的样式,在所述衬底1上,在下电极2形成队列之间间隔地设置有支撑结构3,从而每一条支撑结构3均为其两侧的下电极2所共用。图4显示为图3所示结构的俯视图。As an example, as shown in FIG. 2 , a
具体地,所述支撑结构3用于相变材料层4(即L型结构)成型。所述支撑结构3的材料可以为绝缘的氮化物、氧化物、氮氧化物、碳化物中的任意一种或两种。本实施方式中,在由W制成的下电极2上采用CVD法制备支撑结构3,该支撑结构3的材料为SiN,高度为50-100nm,宽度为5-100nm。Specifically, the
步骤(3):在所述支撑结构3侧壁表面以及衬底1上表面设置相变材料层4,其中,所述相变材料层4与所述下电极2的上接触面连接构成相变存储单元一端,并在所述相变材料层4的外周覆盖一包覆层5。Step (3): disposing a phase change material layer 4 on the sidewall surface of the
具体地,所述相变材料层4的材料为硫系化合物:可以是GeSb、SiSb、InGST、TaST、TaGST或金属氧化物或金属氧化物中的任意一种,制备所述相变材料层4的方法为溅射法、蒸发法、化学气相沉积法、等离子体增强化学气相沉积法、低压化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法和原子层沉积法中的任意一种。Specifically, the material of the phase change material layer 4 is a chalcogenide compound: it can be any one of GeSb, SiSb, InGST, TaST, TaGST or metal oxides or metal oxides, and the phase change material layer 4 is prepared. The methods are sputtering, evaporation, chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition and atomic layer deposition. any of the .
作为示例,本实施方式采用磁控溅射法在SiN制成的支撑结构3上利用CGe2Sb2Te5合金靶制备相变材料层4,工艺参数为:本底气压为1×10-5Pa,溅射时Ar气气压为0.2Pa,溅射功率为200W,衬底温度为230℃,薄膜厚度为10nm。As an example, in this embodiment, a magnetron sputtering method is used to prepare a phase change material layer 4 on a
具体地,在相变材料层4结构周围形成包覆层5(详见图6),所述包覆层5的材料可以为绝缘的氮化物、氧物、氮氧化物和碳化物中的任意一种。本实施方式中,所述包覆层5的材料优选为SiN,高度范围为50-200nm,宽度范围为5-100nm。Specifically, a cladding layer 5 is formed around the structure of the phase change material layer 4 (see FIG. 6 for details), and the material of the cladding layer 5 can be any of insulating nitrides, oxides, oxynitrides and carbides A sort of. In this embodiment, the material of the cladding layer 5 is preferably SiN, the height is in the range of 50-200 nm, and the width is in the range of 5-100 nm.
步骤(4):在未设置有支撑结构3的下电极2形成的队列之间、且沿支撑结构3侧壁方向对所述相变材料层4进行刻蚀,形成隔离槽6,隔离槽6用于使相变材料层4分开,并使用绝缘层7在刻蚀好的相变材料层4周围空间和隔离槽6周围空间进行填充。Step (4): The phase change material layer 4 is etched between the queues formed by the
具体地,如图5所示,沉积相变材料层4之后,相变材料层4覆盖于多个所述支撑结构3侧壁及多个下电极2上。为了将各个相变存储单元的隔离材料8和OTS材料9,或加热电极材料11隔离开,本实施方式中,在位于相邻两条支撑结构3之间的相变材料层4之间形成贯穿相变材料层4的隔离槽6(详见图7),所述隔离槽6将相变材料层4分割为若干分离的刀片状相变材料层4,本实施方式中的“刀片状”相变材料层4指的是相变材料层4的厚度很薄。Specifically, as shown in FIG. 5 , after the phase change material layer 4 is deposited, the phase change material layer 4 covers the sidewalls of the plurality of
如图8所示,形成隔离槽6后,进一步在隔离槽6中沉积一绝缘层7并平坦化。沉积所述绝缘层7并平坦化的目的是为了后续进一步形成上电极10。As shown in FIG. 8 , after the
值得一提的是,被隔离槽6分隔且每个与下电极2接触的相变材料层4的横截面呈L型刀片状结构。It is worth mentioning that the cross section of each phase change material layer 4 which is separated by the
作为示例,本实施方式采用曝光和反应离子刻蚀法形成分隔槽6,分隔开相变材料层4之间的CGe2Sb2Te5膜,形成L型刀片状相变材料层4,该L型刀片状相变材料层4的厚度范围是1~10纳米,优选为10纳米;高度范围是10~500纳米,优选为50纳米;L型刀片状相变材料层4结构的底部宽度范围是5~50纳米。As an example, in this embodiment, exposure and reactive ion etching are used to form
步骤(5):对所述绝缘层7进行抛光,抛光至绝缘层7上表面、支撑结构3上表面、相变材料层4上表面持平,即使相变材料层4上表面暴露出来(详见图9)。Step (5): polishing the insulating layer 7 until the upper surface of the insulating layer 7, the upper surface of the
具体地,采用机械抛光工艺对刀片状相变材料及其包覆层5进行抛光,使其暴露出相变材料层4一端。Specifically, the blade-shaped phase change material and its coating layer 5 are polished by a mechanical polishing process, so that one end of the phase change material layer 4 is exposed.
步骤(6):在抛光好的相变材料层4的上方进行自对准刻蚀,形成限定型孔。Step (6): performing self-alignment etching on the polished phase change material layer 4 to form a defined hole.
具体地,采用对相变材料层4进行刻蚀,在相变材料层4的上方刻蚀出一定深度的限定型孔,该限定型孔的高度为高度为10~100纳米,详见图10。Specifically, the phase change material layer 4 is etched, and a defined hole of a certain depth is etched above the phase change material layer 4, and the height of the defined hole is 10-100 nanometers in height, as shown in FIG. 10 for details. .
步骤(7):在所述限定型孔中放置填充材料,形成相变存储结构。Step (7): placing a filling material in the defined hole to form a phase change memory structure.
(一)当填充材料为依次填充的隔离材料8和OTS材料9时(详见图11),所述隔离层材料8为碳、Ti或钨金属及其氧化物、氮化物中的一种或其混合物;所述OTS材料9为AsTeGeSiN、AsGeTeSi、GeTe、GeSe等。制备隔离材料8和OTS材料9的方法均为溅射法、蒸发法、化学气相沉积法、等离子体增强化学气相沉积法、低压化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法和原子层沉积法中的任意一种。(1) When the filling material is the isolation material 8 and the OTS material 9 filled in sequence (see FIG. 11 for details), the isolation layer material 8 is one of carbon, Ti or tungsten metal and oxides and nitrides thereof or A mixture thereof; the OTS material 9 is AsTeGeSiN, AsGeTeSi, GeTe, GeSe and the like. The methods for preparing the isolation material 8 and the OTS material 9 are sputtering, evaporation, chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic Either vapor deposition method or atomic layer deposition method.
(二)当填充材料为加热电极材料11时,所述加热电极层材料8为单金属材料W、Ti或合金材料WN、TiN、TaN中的任一种,或其组合成的合金材料,或所述电极单金属材料的氧化物材料。制备加热电极层材料8的方法为溅射法、蒸发法、化学气相沉积法、等离子体增强化学气相沉积法、低压化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法和原子层沉积法中的任意一种。关于由加热电极材料11构成的相变存储单元,请依次参阅图14—图16。(2) When the filling material is the heating electrode material 11, the heating electrode layer material 8 is any one of the single metal material W, Ti or the alloy material WN, TiN, TaN, or an alloy material composed thereof, or The oxide material of the electrode single metal material. The method for preparing the heating electrode layer material 8 is sputtering, evaporation, chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition and Atomic Layer Deposition. Regarding the phase-change memory cell composed of the heating electrode material 11, please refer to FIG. 14 to FIG. 16 in turn.
步骤(8):对所述填充材料进行抛光工艺,形成平坦的上表面。Step (8): performing a polishing process on the filling material to form a flat upper surface.
具体地,采用机械抛光工艺对OTS材料9进行抛光,使其暴露出上表面。Specifically, the OTS material 9 is polished by a mechanical polishing process to expose the upper surface.
步骤(9):在所述填充材料平坦的上表面设置上电极10,详见图12。Step (9): disposing the upper electrode 10 on the flat upper surface of the filling material, see FIG. 12 for details.
步骤(10):在所述填充材料的上表面设置上电极10,将上电极10刻蚀成条状(详见图13),刻蚀方向与支撑结构3设置的方向一致。Step (10): disposing the upper electrode 10 on the upper surface of the filling material, etching the upper electrode 10 into a strip shape (see FIG. 13 for details), and the etching direction is the same as the direction in which the
具体地,所述上电极10的材料为单金属材料W、Pt、Au、Ti、Al、Ag、Cu和Ni中的任一种,或其组合成的合金材料,或所述电极单金属材料的氮化物或氧化物。制备上电极10的方法为溅射法、蒸发法、化学气相沉积法、等离子体增强化学气相沉积法、低压化学气相沉积法、金属化合物气相沉积法、分子束外延法、原子气相沉积法和原子层沉积法中的任意一种。Specifically, the material of the upper electrode 10 is any one of single metal materials W, Pt, Au, Ti, Al, Ag, Cu and Ni, or an alloy material composed of a combination thereof, or the electrode single metal material of nitrides or oxides. The methods for preparing the upper electrode 10 are sputtering, evaporation, chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition and atomic vapor deposition Any of the layer deposition methods.
作为示例,在相变材料层4上采用磁控溅射法制备上电极10,工艺参数为:本底气压为1×10-5Pa,溅射时气压为0.2Pa,Ar/N2的气体流量比例为1:1,溅射功率为300W,衬底温度为25℃,TiN上电极高度为50nm。As an example, the magnetron sputtering method is used to prepare the upper electrode 10 on the phase change material layer 4, and the process parameters are: the background gas pressure is 1×10 -5 Pa, the gas pressure during sputtering is 0.2 Pa, and the gas flow rate of Ar/N2 The ratio was 1:1, the sputtering power was 300 W, the substrate temperature was 25 °C, and the electrode height on the TiN was 50 nm.
后续可进一步采用标准半导体工艺引出上电极10和下电极2,与器件单元的控制开关、驱动电路和外围电路集成,从而制备出完整的相变存储器器件单元。作为引出电极的材料可以为W、Pt、Au、Ti、Al、Ag、Cu和Ni中的任一种,或其组合成合金材料。Subsequently, the upper electrode 10 and the
本发明的相变存储单元的制作方法利用一支撑结构3使得刀片状相变材料层4结构成型,并使刀片状相变材料层4与下电极2呈一定角度交叉接触,通过控制刀片状相变材料层4的厚度实现接触面最小化,即相变材料层4的厚度越薄,其和下电极2接触的面积自然就越小,进而达到减小器件单元的相变区域目的,并通过自对准刻蚀出限定型孔,在限定型孔中依次填充隔离层8和OTS材料9,实现1S1R结构,或在限定型孔中填充加热电极材料11,实现限定性结构,从而大大降低功耗和提高存储密度。The manufacturing method of the phase-change memory cell of the present invention utilizes a
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111523997.5A CN114361202B (en) | 2021-12-14 | 2021-12-14 | Phase change memory unit and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111523997.5A CN114361202B (en) | 2021-12-14 | 2021-12-14 | Phase change memory unit and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN114361202A true CN114361202A (en) | 2022-04-15 |
CN114361202B CN114361202B (en) | 2024-12-03 |
Family
ID=81099529
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111523997.5A Active CN114361202B (en) | 2021-12-14 | 2021-12-14 | Phase change memory unit and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN114361202B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN118019352A (en) * | 2023-11-16 | 2024-05-10 | 深圳市红芯微科技开发有限公司 | Storage device, digital subsystem, terrestrial broadcast receiver and boot firmware method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1828922A (en) * | 2005-02-18 | 2006-09-06 | 三星电子株式会社 | Phase-change memory device and manufacturing method thereof |
CN104779349A (en) * | 2015-04-15 | 2015-07-15 | 中国科学院上海微系统与信息技术研究所 | Phase change memory cell and manufacturing method thereof |
CN106299112A (en) * | 2016-08-18 | 2017-01-04 | 中国科学院上海微系统与信息技术研究所 | Multi-state phase-change memory unit element and preparation method thereof |
CN107195776A (en) * | 2016-03-15 | 2017-09-22 | 三星电子株式会社 | Semiconductor devices |
CN109216543A (en) * | 2017-07-06 | 2019-01-15 | 三星电子株式会社 | Semiconductor devices |
-
2021
- 2021-12-14 CN CN202111523997.5A patent/CN114361202B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1828922A (en) * | 2005-02-18 | 2006-09-06 | 三星电子株式会社 | Phase-change memory device and manufacturing method thereof |
CN104779349A (en) * | 2015-04-15 | 2015-07-15 | 中国科学院上海微系统与信息技术研究所 | Phase change memory cell and manufacturing method thereof |
CN107195776A (en) * | 2016-03-15 | 2017-09-22 | 三星电子株式会社 | Semiconductor devices |
CN106299112A (en) * | 2016-08-18 | 2017-01-04 | 中国科学院上海微系统与信息技术研究所 | Multi-state phase-change memory unit element and preparation method thereof |
CN109216543A (en) * | 2017-07-06 | 2019-01-15 | 三星电子株式会社 | Semiconductor devices |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN118019352A (en) * | 2023-11-16 | 2024-05-10 | 深圳市红芯微科技开发有限公司 | Storage device, digital subsystem, terrestrial broadcast receiver and boot firmware method |
Also Published As
Publication number | Publication date |
---|---|
CN114361202B (en) | 2024-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7173271B2 (en) | Phase-change memory device and method of manufacturing the same | |
US7514705B2 (en) | Phase change memory cell with limited switchable volume | |
TWI384664B (en) | Memory array with diode driver and method for fabricating the same | |
CN101246950B (en) | Memory elements with lower current phase change elements | |
US7618840B2 (en) | Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof | |
CN101461071B (en) | A vertical phase change memory cell and methods for manufacturing thereof | |
US7473921B2 (en) | Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement | |
US9276202B2 (en) | Phase-change storage unit containing TiSiN material layer and method for preparing the same | |
TW201042731A (en) | Buried silicide structure and method for making | |
JP2008060569A (en) | Thin-film phase-change memory cell formed on silicon-on-insulator substrate, method for forming the same, and integrated circuit including one or more memory cell | |
US11233198B2 (en) | Three-dimensional stacked memory and preparation method thereof | |
CN111146340A (en) | A phase change memory cell and method of making the same | |
CN112652714A (en) | Preparation method of phase change memory array | |
CN103066203A (en) | Phase-change memory device having multi-level cell and method of manufacturing the same | |
CN111029362B (en) | A method for preparing a high-density phase-change memory three-dimensional integrated circuit structure | |
CN114361202A (en) | Phase change memory cell and manufacturing method thereof | |
US20130292629A1 (en) | Phase change memory cell and fabrication method thereof | |
CN110931637B (en) | Preparation method of gate tube | |
CN103794722A (en) | Novel phase change storage cell structure and manufacturing method thereof | |
CN106997924B (en) | Phase transition storage and its manufacturing method and electronic equipment | |
CN105633279A (en) | Phase-change memory unit comprising partially defined phase-change material structures and fabrication method | |
US7985693B2 (en) | Method of producing phase change memory device | |
CN104078563A (en) | Phase change memory, forming method of phase change memory and phase change memory array | |
CN103441215B (en) | Phase change storage structure of sandwich type blade-like electrode and preparation method thereof | |
CN100442566C (en) | Phase change memory and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |