CN114361127B - High bandwidth impedance matching integrated ceramic substrate circuit and manufacturing method thereof - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 87
- 239000000919 ceramic Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010931 gold Substances 0.000 claims abstract description 89
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 82
- 229910052737 gold Inorganic materials 0.000 claims abstract description 82
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 238000007747 plating Methods 0.000 claims abstract description 37
- 230000005540 biological transmission Effects 0.000 claims abstract description 31
- 238000005070 sampling Methods 0.000 claims abstract description 24
- 230000007704 transition Effects 0.000 claims abstract description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 22
- 229910052697 platinum Inorganic materials 0.000 claims description 20
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 19
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 19
- 238000009713 electroplating Methods 0.000 claims description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical group [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000004088 simulation Methods 0.000 description 9
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
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- 238000004544 sputter deposition Methods 0.000 description 2
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- 238000006243 chemical reaction Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 238000000227 grinding Methods 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明涉及一种高带宽阻抗匹配集成陶瓷基板电路，包括陶瓷基板，所述陶瓷基板的正面设置有通过金属镀层形成的信号输出微带线、接地金属镀层、微带线过渡段、P电极连接部、两个N电极传输线和匹配网络的采样电阻；所述P电极连接部和两个N电极传输线上分别设有倒装金柱；所述接地金属镀层的中部开设有接地通孔，所述陶瓷基板的反面和接地通孔的孔壁覆盖有金层。本发明中，在陶瓷基板上采用镀层的方式形成电路结构，通过对陶瓷基板电路各器件尺寸的设计，使微带线传输与高速光电二极管芯片匹配度高，传输损耗小，从而能够使陶瓷基板电路的3dB带宽达到36.95GHz，30GHz内射频反射损耗达到‑8.366dB。
The present invention relates to a high-bandwidth impedance matching integrated ceramic substrate circuit, comprising a ceramic substrate, wherein the front of the ceramic substrate is provided with a signal output microstrip line formed by metal plating, a grounding metal plating, a microstrip line transition section, a P-electrode connection part, two N-electrode transmission lines and a sampling resistor of a matching network; the P-electrode connection part and the two N-electrode transmission lines are respectively provided with flip-chip gold pillars; a grounding through hole is provided in the middle of the grounding metal plating, and the back of the ceramic substrate and the hole wall of the grounding through hole are covered with a gold layer. In the present invention, a circuit structure is formed on the ceramic substrate by plating, and by designing the size of each device of the ceramic substrate circuit, the microstrip line transmission has a high matching degree with the high-speed photodiode chip, and the transmission loss is small, so that the 3dB bandwidth of the ceramic substrate circuit can reach 36.95GHz, and the radio frequency reflection loss within 30GHz can reach 8.366dB.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a high-bandwidth impedance matching integrated ceramic substrate circuit and a manufacturing method thereof.
Background
With the continuous development of 5G communication, the high-speed optical fiber communication system has been rapidly developed and widely applied, and the demand of the high-speed photoelectric detector module as a core device of the high-speed optical fiber communication system is also continuously increased.
The existing high-speed photoelectric detector module impedance matching circuit is mainly assembled by adopting discrete components to be attached and connected through gold wire bonding, the assembly steps are complex, the reliability is low, the radio frequency reflection loss is large, and the performance of the subsequent power devices is influenced.
Disclosure of Invention
Accordingly, the present invention is directed to a high bandwidth impedance matching integrated ceramic substrate circuit and a method for fabricating the same.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a high-bandwidth impedance matching integrated ceramic substrate circuit comprises a ceramic substrate, wherein the ceramic substrate is provided with a front surface and a back surface opposite to the front surface, the front surface is provided with a signal output microstrip line formed by a first metal plating layer, a grounding metal plating layer, a microstrip line transition section, a P electrode connection part, two N electrode transmission lines and a sampling resistor of a matching network formed by a second metal plating layer, one end of the signal output microstrip line is connected with the P electrode connection part through the trapezoid microstrip line transition section, the two N electrode transmission lines are symmetrically arranged on two sides of the P electrode connection part, a first flip gold column is arranged on the P electrode connection part, the two N electrode transmission lines are respectively provided with a second flip gold column, one side of the signal output microstrip line is connected with the sampling resistor, the sampling resistor is connected with the grounding metal plating layer, a grounding through hole penetrating through the back surface is formed in the middle of the grounding metal plating layer, the back surface of the ceramic substrate is covered with a second gold layer which is used for grounding, and the wall of the grounding through hole is covered with a third gold layer which is connected with the grounding metal plating layer.
Further, the size of the signal output microstrip line is 1.15mm×0.4mm, the size of the grounding metal plating layer is 1mm×0.3mm, and the sizes of the two N electrode transmission lines are 0.3mm×
0.06mm。
Further, the first metal plating layer comprises a tungsten-titanium alloy layer arranged on the ceramic substrate, a platinum layer arranged on the tungsten-titanium alloy layer, and a first gold layer arranged on the platinum layer.
Further, the thickness of the tungsten-titanium alloy layer is 0.1 mu m, the thickness of the platinum layer is 0.2 mu m, and the thickness of the first gold layer is 3.0-3.5 mu m.
Further, the second metal coating is a tantalum nitride layer, the size of the tantalum nitride layer is 0.15mm multiplied by 0.3mm, and the resistance value is 50Ω.
Further, the front face is provided with a third flip-chip gold column, and the third flip-chip gold column is used for chip fixation.
Further, the number of the grounding through holes is two, and the radius is 0.1mm.
A manufacturing method of a high-bandwidth impedance matching integrated ceramic substrate circuit comprises the following steps:
S1, polishing, cleaning and drying a ceramic substrate;
S2, forming a tantalum nitride layer in a resistor area on the front surface of the ceramic substrate, forming a tungsten-titanium alloy layer in a metal area, and forming a platinum layer on the tungsten-titanium alloy layer;
s3, forming a first gold layer on the platinum layer by adopting an electroplating process;
s4, forming a grounding through hole penetrating through the front surface and the back surface of the ceramic substrate on the grounding metal coating, forming a second gold layer on the back surface of the ceramic substrate by adopting an electroplating process, and forming a third gold layer on the wall of the grounding through hole;
s5, completing pattern preparation of the sampling resistor of the signal output microstrip line, the grounding metal plating layer, the microstrip line transition section, the P electrode connecting part, the two N electrode transmission lines and the matching network by adopting photoetching and etching processes;
s6, performing heat treatment on the ceramic substrate, performing L-shaped cutting on the sampling resistor, adjusting the resistance to 50 omega, and performing heat treatment again;
S7, forming flip-chip gold columns on the P electrode connecting part and the two N electrode transmission lines respectively by adopting an electroplating process;
s8, dividing the ceramic substrate into independent units through dicing.
Further, the thickness of the tungsten-titanium alloy layer is 0.1 mu m, the thickness of the platinum layer is 0.2 mu m, the thickness of the first gold layer is 3.0-3.5 mu m, and the thicknesses of the second gold layer and the third gold layer are 1.5-2.0 mu m.
Further, the step S6 specifically includes the following substeps:
S61, performing heat treatment on the ceramic substrate with the patterns at the temperature of 250-350 ℃ for 1.5-2.5 hours;
S62, performing heat treatment on the ceramic substrate at 130-170 ℃ for 20-28 hours;
S63, carrying out L-shaped cutting on the sampling resistor by using laser, and adjusting the resistance value according to the required target resistance value and precision;
S64, performing heat treatment on the ceramic substrate subjected to resistance adjustment at 130-170 ℃ for 20-28 h.
According to the invention, a circuit structure is formed on the ceramic substrate in a plating way, and the microstrip line transmission and high-speed photodiode chip matching degree is high and the transmission loss is small through the design of the size of each device of the ceramic substrate circuit, so that the 3dB bandwidth of the ceramic substrate circuit can reach 36.95GHz, and the radio frequency reflection loss in 30GHz can reach-8.366 dB.
Drawings
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a preferred embodiment of a high bandwidth impedance matching integrated ceramic substrate circuit of the present invention.
Fig. 2 is an enlarged view at a in fig. 1.
Fig. 3 is a top view of fig. 1.
Fig. 4 is a bottom view of fig. 1.
Fig. 5 is a flow chart of a preferred embodiment of a method of fabricating a high bandwidth impedance matching integrated ceramic substrate circuit of the present invention.
Fig. 6 is a schematic diagram of a simulated equivalent circuit of a high bandwidth impedance matching integrated ceramic substrate circuit.
Fig. 7 is a graph of simulation S-parameter output results for a high bandwidth impedance matching integrated ceramic substrate circuit.
In the figure, a ceramic substrate 1, a grounding through hole 2, a front surface 100, a signal output microstrip line 110, a microstrip line transition section 111, a 112P electrode connecting part 120.N electrode transmission line 130, a sampling resistor 140, a grounding metal coating 151, a first flip-chip gold column 152, a second flip-chip gold column 153, a third flip-chip gold column 153 and a back surface 200.
Detailed Description
The following description of the embodiments of the invention is given by way of specific examples, the illustrations provided in the following examples merely illustrate the basic idea of the invention, and the following examples and features of the examples can be combined with one another without conflict.
As shown in fig. 1, 2 and 3, a preferred embodiment of the high-bandwidth impedance matching integrated ceramic substrate circuit of the present invention includes a ceramic substrate 1, preferably an alumina ceramic substrate, having a size of preferably 2mm×2mm×0.381mm, the ceramic substrate 1 being provided with a front surface 100 and a reverse surface 200 opposite to the front surface 100, the front surface 100 being provided with a signal output microstrip line 110 formed by a first metal plating layer, a ground metal plating layer 140, a microstrip line transition section 111, a P electrode connection 112 and two N electrode transmission lines 120. The first metal plating layer includes a tungsten-titanium alloy layer provided on the ceramic substrate 1, a platinum layer provided on the tungsten-titanium alloy layer, and a first gold layer provided on the platinum layer. The tungsten-titanium alloy layer is made of WTi, the thickness of the tungsten-titanium alloy layer is preferably 0.1 mu m, the platinum layer is made of Pt, the thickness of the platinum layer is preferably 0.2 mu m, the first gold layer is made of Au, and the thickness of the first gold layer is preferably 3.0-3.5 mu m. The front surface 100 is further provided with a sampling resistor 130 of a matching network formed by a second metal plating layer, which is a tantalum nitride layer.
The size of the signal output microstrip line 110 is preferably 1.15mm×0.4mm, one end of the signal output microstrip line 110 is connected with the P electrode connection portion 112 through a trapezoid microstrip line transition section 111, two N electrode transmission lines 120 are symmetrically arranged at two sides of the P electrode connection portion 112, and the sizes of the two N electrode transmission lines 120 are preferably 0.3mm×0.06mm. The P electrode connection portion 112 is provided with a first flip gold column 151, the first flip gold column 151 is used for connecting P electrodes of the high-speed photodiode chip, the two N electrode transmission lines 120 are respectively provided with a second flip gold column 152, the second flip gold column 152 is used for connecting N electrodes of the high-speed photodiode chip, and materials of the first flip gold column 151 and the second flip gold column 152 are Au. For ease of attachment, in some embodiments, the front side 100 may further be provided with a third flip-chip gold stud 153, preferably two third flip-chip gold studs 153, and the third flip-chip gold stud 153 has the same dimensions and materials as the first flip-chip gold stud 151.
One side of the signal output microstrip line 110 is connected with a sampling resistor 130 of the matching network, and the size of the sampling resistor 130 is preferably 0.15mm×0.3mm, and the resistance value is 50Ω. The sampling resistor 130 is connected to the ground metallization 140, and the size of the ground metallization 140 is preferably 1mm×0.3mm. As shown in fig. 4, the middle part of the grounding metal coating 140 is provided with grounding through holes 2 penetrating to the back surface 200, the number of the grounding through holes 2 is preferably two, and the radius is preferably 0.1mm. The opposite surface 200 of the ceramic substrate 1 is covered with a second gold layer, which is used for grounding. The wall of the grounding through-hole 2 is covered with a third gold layer connecting the grounding metal plating 140 and the second gold layer. The second gold layer and the third gold layer are made of Au, and the thickness of the Au is 1.5-2.0 mu m.
In the embodiment, a circuit structure is formed on a ceramic substrate in a plating mode, CPW (coplanar waveguide) connection is realized between the ceramic substrate circuit and a high-speed photodiode chip through a flip-chip gold column, conversion from current to voltage signals is realized through a sampling resistor, signal output is performed through a signal transmission microstrip line, the microstrip line transmission and the high-speed photodiode chip have high matching degree and small transmission loss through the design of the size of each device of the ceramic substrate circuit, and therefore the 3dB bandwidth of the ceramic substrate circuit can reach 36.95GHz, and the radio frequency reflection loss in 30GHz can reach-8.366 dB.
As shown in fig. 5, a preferred embodiment of the method for manufacturing a high bandwidth impedance matching integrated ceramic substrate circuit of the present invention comprises the steps of:
S1, polishing the ceramic substrate 1, cleaning the polished ceramic substrate 1 with deionized water, and drying.
S2, evaporating or sputtering a tantalum nitride layer with TaN material in a resistor area (an area for forming the sampling resistor 130) of the front surface 100 of the ceramic substrate 1 by adopting a stripping process, wherein the tantalum nitride layer is a second metal plating layer. A tungsten-titanium alloy layer of material WTi, preferably 0.1 μm thick, is formed by evaporation or sputtering using a lift-off process in the metal region of the front surface 100 of the ceramic substrate 1 (the region for forming the signal output microstrip line 110, the ground metal plating 140, the microstrip line transition section 111, the P electrode connection section 112, and the two N electrode transmission lines 120). A platinum layer of Pt is formed on the tungsten-titanium alloy layer, and the thickness of the platinum layer is preferably 0.2 μm.
S3, forming a first gold layer on the platinum layer by adopting an electroplating process, wherein the first gold layer is made of Au, and the thickness is preferably 3.0-3.5 mu m. The tungsten-titanium alloy layer on the front surface 100 of the ceramic substrate 1, the platinum layer on the tungsten-titanium alloy layer, and the first gold layer on the platinum layer form a first metal plating layer.
S4, forming a grounding through hole 2 penetrating through the front surface 100 and the back surface 200 of the ceramic substrate 1, preferably forming two grounding through holes 2, forming a second gold layer on the back surface 200 of the ceramic substrate 1 by adopting an electroplating process, and forming a third gold layer on the hole wall of the grounding through hole 2, wherein the second gold layer and the third gold layer can be formed simultaneously. The second gold layer and the third gold layer are made of Au, and the thickness of the Au is 1.5-2.0 mu m.
S5, adopting photoetching and etching processes to complete the pattern preparation of the signal output microstrip line 110, the grounding metal plating layer 140, the microstrip line transition section 111, the P electrode connecting part 112, the two N electrode transmission lines 120 and the sampling resistor 130 of the matching network. Specifically, a photolithography process is first used to define a signal output microstrip line 110, a grounded metal plating layer 140, a microstrip line transition section 111, a P electrode connection portion 112, and two N electrode transmission line 120 regions on a first metal plating layer, and the patterning of the device in the metal region is completed by combining ICP dry etching and wet etching, where the size of the signal output microstrip line 110 is 1.15mm×0.4mm, the size of the grounded metal plating layer 140 is 1mm×0.3mm, and the sizes of the two N electrode transmission lines 120 are 0.3mm×0.06mm. And defining a resistance region on the second metal coating by adopting a photoetching process, and completing the pattern preparation of a sampling resistor 130 of the resistance region in a mode of combining ICP dry etching and wet etching, wherein the size of the sampling resistor 130 is 0.15mm multiplied by 0.3mm.
S6, performing heat treatment on the ceramic substrate 1 with the patterns, performing L-shaped cutting on the sampling resistor 130, adjusting the resistance value to 50 omega, and performing heat treatment again. The method specifically comprises the following substeps:
s61, performing heat treatment on the ceramic substrate 1 with the patterns at 250-350 ℃ for 1.5-2.5 h, and preferably performing heat treatment at 300 ℃ for 2h.
S62, performing heat treatment on the ceramic substrate 1 at 130-170 ℃ for 20-28 h, and preferably performing heat treatment at 150 ℃ for 24h. The film layer (i.e., the metal plating layer) of the ceramic substrate 1 is cured by the heat treatment twice, keeping the film layer stable.
S63, carrying out L-shaped cutting on the sampling resistor 130 on the ceramic substrate 1 after heat treatment by using laser, so as to adjust the resistance value according to the required target resistance value (namely 50 omega) and precision.
S64, performing heat treatment at 130-170 ℃ for 20-28 h, preferably at 150 ℃ for 24h on the ceramic substrate 1 subjected to resistance adjustment.
And S7, forming flip-chip gold columns on the P electrode connecting part 112 and the two N electrode transmission lines 120 by adopting an electroplating process. Preferably, a first flip-chip gold pillar 151 is formed at the P-electrode connection portion 112, and a second flip-chip gold pillar 152 is formed at each of the two N-electrode transmission lines 120. To facilitate the fixing of the high-speed photodiode chip, the front surface 100 may further be formed with a third flip-chip gold column 153 by electroplating, preferably two third flip-chip gold columns 153, and the dimensions and materials of the third flip-chip gold columns 153 are the same as those of the first flip-chip gold columns 151. The dimensions of the first flip gold pillar 151, the second flip gold pillar 152 and the third flip gold pillar 153 are the same, and the dimensions of the flip gold pillar are calculated according to the pad size and the chip output bandwidth of the high-speed photodiode chip by using a CPW (coplanar waveguide) model, for example, in this embodiment, the diameter of the flip gold pillar is calculated to be 50 μm, and the height is calculated to be 10-15 μm.
And S8, dividing the ceramic substrate 1 into independent units by grinding wheel scribing. After that, the high-speed photodiode chip may be soldered on the ceramic substrate 1 of the independent unit by flip-chip bonding, so that the first flip-chip gold stud 151 is connected to the P electrode of the high-speed photodiode chip, and the two second flip-chip gold studs 152 are connected to the N electrode of the high-speed photodiode chip.
As shown in fig. 6 and 7, the dimensions of each device of the ceramic substrate circuit can be determined in a simulation mode before manufacturing, specifically, the simulation of the detector assembly equivalent circuit by ADS is performed to establish a circuit model of the ceramic substrate 1, and a simulation equivalent circuit schematic diagram of the high-bandwidth impedance matching integrated ceramic substrate circuit is shown in fig. 6. And then establishing a high-speed photodiode chip S parameter model through MATLB, combining the high-speed photodiode chip S parameter model with a circuit model for simulation, and outputting a simulation S parameter result diagram of the high-bandwidth impedance matching integrated ceramic substrate circuit as shown in figure 7. And then designing a microstrip structure of the circuit model through XLINE, and performing circuit structure simulation design through ADS, wherein when the simulation result shows that the 3dB bandwidth reaches 36.95GHz and the radio frequency reflection loss reaches-8.366 dB in 30GHz, the design circuit corresponding to the simulation result is used as a ceramic substrate circuit determined by layout design.
In the embodiment, the size of the flip gold column is calculated through a CPW model according to the size of the high-speed photodiode chip and the chip output bandwidth, the sampling resistance value is determined (namely 50 omega) according to the impedance matching principle, the width and the length of the microstrip line are calculated through a microstrip line model according to the dielectric constants of the alumina substrate and the surface coating and the thickness of the substrate, the matching degree of microstrip line transmission and the high-speed photodiode chip is high, the transmission loss is small, and therefore the 3dB bandwidth of a ceramic substrate circuit can reach 36.95GHz, and the radio frequency reflection loss in 30GHz can reach-8.366 dB.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.
Claims (7)
1. A high-bandwidth impedance matching integrated ceramic substrate circuit is characterized by comprising a ceramic substrate, wherein the ceramic substrate is provided with a front surface and a back surface opposite to the front surface, the front surface is provided with a signal output microstrip line formed by a first metal plating layer, a grounding metal plating layer, a microstrip line transition section, a P electrode connecting part, two N electrode transmission lines and a sampling resistor of a matching network formed by a second metal plating layer, the first metal plating layer comprises a tungsten titanium alloy layer arranged on the ceramic substrate, a platinum layer arranged on the tungsten titanium alloy layer and a first gold layer arranged on the platinum layer, the thickness of the tungsten titanium alloy layer is 0.1 mu m, the thickness of the platinum layer is 0.2 mu m, the thickness of the first gold layer is 3.0-3.5 mu m, the second metal plating layer is a tantalum nitride layer, the size of the tantalum nitride layer is 0.15mm multiplied by 0.3mm, the resistance value is 50 omega, one end of the signal output line is connected with the P electrode transition section through a trapezoid wire, the P electrode connecting part is connected with the N electrode connecting part, the two N electrode connecting parts are connected with the second metal plating layer, the second metal plating layer is connected with the second gold plating layer through a micro-strip, the second gold layer is connected with the second gold layer through a grounding electrode, the second gold layer is connected with the second gold layer through a micro-strip, the second gold layer is connected with the second gold layer through a grounding electrode, and the second gold layer is connected with the second gold layer through a grounding layer, and the second gold layer through a grounding layer is connected with the second gold layer through a grounding layer, and the second grounding layer is connected with the second grounding layer through the grounding electrode, and the grounding electrode has a grounding electrode.
2. The high bandwidth impedance matching integrated ceramic substrate circuit of claim 1, wherein the size of the signal output microstrip line is 1.15mm by 0.4mm, the size of the ground metallization layer is 1mm by 0.3mm, and the size of both the N electrode transmission lines is 0.3mm by 0.06mm.
3. The high bandwidth impedance matching integrated ceramic substrate circuit of claim 1, wherein the front side is provided with a third flip-chip gold stud for chip attach.
4. The high bandwidth impedance matching integrated ceramic substrate circuit of claim 3, wherein the number of ground vias is two and the radius is 0.1mm.
5. A method for manufacturing a high bandwidth impedance matching integrated ceramic substrate circuit, which is used for manufacturing the high bandwidth impedance matching integrated ceramic substrate circuit according to any one of claims 1 to 4, and is characterized by comprising the following steps:
S1, polishing, cleaning and drying a ceramic substrate;
S2, forming a tantalum nitride layer in a resistor area on the front surface of the ceramic substrate, forming a tungsten-titanium alloy layer in a metal area, and forming a platinum layer on the tungsten-titanium alloy layer;
s3, forming a first gold layer on the platinum layer by adopting an electroplating process;
s4, forming a grounding through hole penetrating through the front surface and the back surface of the ceramic substrate on the grounding metal coating, forming a second gold layer on the back surface of the ceramic substrate by adopting an electroplating process, and forming a third gold layer on the wall of the grounding through hole;
s5, completing pattern preparation of the sampling resistor of the signal output microstrip line, the grounding metal plating layer, the microstrip line transition section, the P electrode connecting part, the two N electrode transmission lines and the matching network by adopting photoetching and etching processes;
s6, performing heat treatment on the ceramic substrate, performing L-shaped cutting on the sampling resistor, adjusting the resistance to 50 omega, and performing heat treatment again;
S7, forming flip-chip gold columns on the P electrode connecting part and the two N electrode transmission lines respectively by adopting an electroplating process;
s8, dividing the ceramic substrate into independent units through dicing.
6. The method of claim 5, wherein the second and third gold layers have a thickness of 1.5-2.0 μm.
7. The method for manufacturing a high bandwidth impedance matching ceramic substrate circuit according to claim 5, wherein the step S6 specifically comprises the following substeps:
S61, performing heat treatment on the ceramic substrate with the patterns at the temperature of 250-350 ℃ for 1.5-2.5 hours;
S62, performing heat treatment on the ceramic substrate at 130-170 ℃ for 20-28 hours;
S63, carrying out L-shaped cutting on the sampling resistor by using laser, and adjusting the resistance value according to the required target resistance value and precision;
S64, performing heat treatment on the ceramic substrate subjected to resistance adjustment at 130-170 ℃ for 20-28 h.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011171501A (en) * | 2010-02-18 | 2011-09-01 | Fujikura Ltd | Flip-chip mounting device |
| CN104795614A (en) * | 2015-04-07 | 2015-07-22 | 上海大学 | Broad-stopband electrically-tunable dual-frequency band-pass filter |
| CN214278225U (en) * | 2020-10-14 | 2021-09-24 | 武汉格物芯科技有限公司 | Low-frequency noise test fixture for lead capacitor |
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