CN114356663A - Breakpoint synchronous stopping method for redundancy multiprocessor - Google Patents

Abstract

The application provides a breakpoint synchronous stopping method of a redundancy multiprocessor, which comprises the following steps: the software breakpoint of the first processor hits, sends a stop signal and enters a standby state; the software breakpoint is set by a debugging upper computer; the second processor receives the stop signal and is in a standby state; wherein the stop signal is used for enabling the processor to be in a standby state; the first computer comprises a first processor and a second processor; the debugging connector receives the stop signal and forwards the stop signal to the second computer; the second computer receives the stop signal and forwards the stop signal to the third processor and the fourth processor; wherein the second computer comprises a third processor and a fourth processor; the third processor and the fourth processor receive the stop signal and are in a standby state; wherein the first computer and the second computer are different.

Description

Breakpoint synchronous stopping method for redundancy multiprocessor

Technical Field

The application belongs to the technical field of computer debugging, and particularly relates to a breakpoint synchronous stopping method for a redundancy multiprocessor.

Background

In order to improve the fault tolerance of the control system, the control computer usually adopts redundancy configuration. To increase the computing power of the control system, a single control computer may employ a multi-processor configuration. A synchronization mechanism needs to be established among the multiple processors of the redundancy control computer of the control system so as to meet the requirement of synchronization control.

Meanwhile, the synchronous debugging capability of the multi-redundancy multiprocessor is indispensable, namely one processor stops running due to the debugging breakpoint, and other processors of the redundancy control computer and processors of other redundancy control computers also stop running synchronously so as to save the debugging site of the whole control system.

Because there is a difference in code logic between different processors, and there is a scenario in which all processors cannot stop running by setting the same debug breakpoint, a synchronous stop technique for redundant multiprocessor breakpoints is required.

Disclosure of Invention

In view of the above technical problem, the present application provides a method for synchronously stopping a breakpoint of a redundancy multiprocessor, where the method includes:

the software breakpoint of the first processor hits, sends a stop signal and enters a standby state; the software breakpoint is set by a debugging upper computer;

the second processor receives the stop signal and is in a standby state; wherein the stop signal is used for enabling the processor to be in a standby state; the first computer includes a first processor and a second processor.

Preferably, the method further comprises:

the debugging connector receives the stop signal and forwards the stop signal to the second computer;

the second computer receives the stop signal and forwards the stop signal to the third processor and the fourth processor; wherein the second computer comprises a third processor and a fourth processor;

the third processor and the fourth processor receive the stop signal and are in a standby state; wherein the first computer and the second computer are different.

Preferably, the method further comprises:

the debugging connector receives the stop signal and forwards the stop signal to a third computer;

the third computer receives the stop signal and forwards the stop signal to the fifth processor and the sixth processor; wherein the third computer comprises a fifth processor and a sixth processor;

the fifth processor and the sixth processor receive the stop signal and are in a standby state; wherein the first computer and the third computer are different.

Preferably, the debugging connectors are connected with the first computer, the second computer and the third computer, respectively.

Preferably, the debugging connector is further connected with the debugging upper computer.

Preferably, the method further comprises:

and the debugging upper computer sends a debugging instruction, and the debugging connector receives the debugging instruction and forwards the debugging instruction to the first processor, the second processor, the third processor, the fourth processor, the fifth processor and the sixth processor.

Preferably, the first processor is connected with the second processor; the third processor is connected with the fourth processor; the fifth processor is connected with the sixth processor.

Preferably, the debugging upper computer is connected with the debugging connector through a debugging bus; and the data line of the stop signal is connected with an external interrupt pin of the processor.

The invention has the beneficial effects that:

according to the synchronous debugging mechanism of the redundancy multiprocessor, when one processor stops running due to breakpoint hit, other processors of the redundancy and processors of other redundancies can be triggered to stop running synchronously.

Drawings

Fig. 1 is a system connection block diagram provided in an embodiment of the present application;

FIG. 2 is a block diagram of a debug connector hard-wired connection provided by an embodiment of the present application;

fig. 3 is a connection block diagram of a control computer according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-3, the technical solution provided by the present application: the system comprises a debugging upper computer, a debugging connector and a redundancy configuration control computer (the assumed redundancy number is N). The debugging upper computer is used for sending debugging instructions (such as setting breakpoints, reading and writing variables and the like), the debugging connector is used for debugging signal connection between the debugging upper computer and the N redundancy control computers, and each redundancy control computer comprises a plurality of processors (the number of the processors is assumed to be M).

2) External connection relationship: the debugging upper computer is connected with M processors of the N redundancy control computers through a debugging bus, the debugging upper computer is connected with the debugging connector through 1 debugging bus, and the debugging connector is responsible for transferring debugging data to the M processors of the N redundancy control computers. The debugging connector and the control computer are connected BY hard wires, and each redundancy control computer has an SBO _ OUT _ FROM _ X (SBO: STOP BY OTHER) output signal and an SBO _ IN _ TO _ X input signal which are connected with the debugging connector.

3) Debugging the internal connection relation of the connector: the SBO _ OUT _ FROM _ X signals (not including the SBO _ OUT _ FROM _ X signals) FROM the N-1 redundancy control computers are logically combined TO generate the SBO _ OUT _ TO _ X signals.

4) Controlling the internal connection relation of the computer: each processor of the redundancy X control computer has 3 signals: the SBO _ OUT output signal, the SBO _ IN input signal, and the SBO _ IN _ LOCAL input signal. After the SBO _ OUT signals of the M processors are subjected to OR logic synthesis, the SBO _ OUT _ FROM _ X signals are output. The SBO _ IN _ TO _ X input signals from the debug connectors are connected TO the SBO _ IN input signals of the M processors, respectively. The SBO _ OUT output signal of any one processor is connected to the SBO _ IN _ LOACAL input signals of the other M-1 processors.

6) The signal flow describes: the debugging breakpoint of software in any processor of the computer is controlled by setting the redundancy X through the debugging upper computer, the software debugging breakpoint is hit, an exception handling program is entered, and after an SBO signal is immediately sent, the debugging instruction from the debugging upper computer is circularly waited. IN the control computer, SBO _ IN _ LOCAL is output to other M-1 processors through SBO _ OUT signal. And the SBO _ IN _ TO _ (representing other redundancies except the redundancy X) is sent TO the debugging connector through an SBO _ OUT _ FROM _ X signal outside the control computer, and is sent TO other redundancy control computers after being subjected TO OR logic synthesis inside the debugging connector. After receiving the SBO _ IN _ TO _ signals, other redundancy control computers respectively send SBO _ IN signals TO M processors of the redundancy control computer.

7) After an SBO _ IN input signal and an SBO _ IN _ LOCAL input signal of the processor are subjected to logical synthesis, the SBO _ IN input signal and the SBO _ IN _ LOCAL input signal are connected with an external interrupt pin of the processor, external interrupt is triggered when the signal comes, software enters an interrupt processing program, and the SBO _ IN input signal and the SBO _ IN _ LOCAL input signal are subjected to round-robin waiting for a debugging instruction from a debugging upper computer.

According to the invention, through a STOP BY OTHER software and hardware integrated design, any processor STOPs running and sends an SBO signal, and all OTHER processors of the whole control system can be triggered to STOP running, so that synchronous running field snapshots of the whole control system are completely saved, and the synchronous debugging problem of redundant multiprocessors is solved.

Note that the first computer is a redundancy a computer, the second computer is a redundancy B computer, and the third computer is a redundancy C computer. The first processor is the CPU1 of the redundancy a computer, the second processor is the CPU2 of the redundancy a computer, the third processor is the CPU1 of the redundancy B computer, the fourth processor is the CPU2 of the redundancy B computer, the fifth processor is the CPU1 of the redundancy C computer, and the sixth processor is the CPU2 of the redundancy C computer.

Specific embodiments are described in detail with examples shown in fig. 1-3.

1) The control computer of the control system adopts three-redundancy control, comprising a redundancy A, a redundancy B and a redundancy C.

2) The control computer for each redundancy is in a dual processor configuration, including CPU1 and CPU 2.

3) The debugging upper computer sets a redundancy A to control the debugging breakpoint of software in the CPU1 of the computer through a debugging bus, the debugging breakpoint is hit, the software enters an exception handling program, an SBO signal is sent out immediately, and then the debugging upper computer enters a round-robin waiting state to wait for a debugging instruction of the debugging upper computer.

4) The margin a controls the computer CPU2 to stop running: the SBO signal is sent to an SBO _ IN _ LOCAL signal of a redundancy A control computer CPU2, external interruption is triggered, software carries out an interruption processing program, and the software enters a round-robin waiting state to wait for debugging instructions of an upper computer.

5) The redundancy B controls the computer CPU1/2 to stop running: after the SBO signal is subjected to OR logic processing inside the redundancy A control computer, the SBO signal is synthesized into an SBO _ OUT _ FROM _ A signal and is sent to the debugging connector. IN the debugging connector, after the SBO _ OUT _ FROM _ A passes through OR logic, the SBO _ IN _ TO _ B signals are synthesized and sent TO a redundancy B control computer. The SBO _ IN _ TO _ B signal controls the computer at redundancy B, splitting into two, entering the SBO _ IN input signals of CPU1 and CPU2, respectively. The SBO _ IN signal can trigger external interrupts of the CPU1 and the CPU2, software enters an interrupt processing program, enters a round-robin waiting state and waits for a debugging instruction of a debugging upper computer.

6) The redundancy C controls the computer CPU1/2 to stop running: after the SBO signal is subjected to OR logic processing inside the redundancy A control computer, the SBO signal is synthesized into an SBO _ OUT _ FROM _ A signal and is sent to the debugging connector. IN the debugging connector, after the SBO _ OUT _ FROM _ A passes through OR logic, the SBO _ IN _ TO _ C signals are synthesized and sent TO a redundancy C control computer. The SBO _ IN _ TO _ C signal controls the computer at redundancy C, split IN two, and goes TO the SBO _ IN input signals of CPU1 and CPU2, respectively. The SBO _ IN signal can trigger external interrupts of the CPU1 and the CPU2, software enters an interrupt processing program, enters a round-robin waiting state and waits for a debugging instruction of a debugging upper computer.

7) So far, the breakpoint of the redundancy A control computer CPU1 software stops running, the redundancy A control computer CPU2 and the redundancy B/C control computer CPU1/2 software stop running. All processor software of the whole control system enters a round-robin waiting state to wait for a debugging instruction from a debugging upper computer. The software of the whole control system is synchronously operated and stored on site.

8) The debugging upper computer can read and write the variable of software in any processor of the control system and develop the needed debugging work.

The foregoing is merely a detailed description of the embodiments of the present invention, and some of the conventional techniques are not detailed. The scope of the present invention is not limited thereto, and any changes or substitutions that can be easily made by those skilled in the art within the technical scope of the present invention will be covered by the scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (8)

1. A multi-redundancy multiprocessor breakpoint synchronous stopping method is characterized by comprising the following steps:

the software breakpoint of the first processor hits, sends a stop signal and enters a standby state; the software breakpoint is set by a debugging upper computer;

the second processor receives the stop signal and is in a standby state; wherein the stop signal is used for enabling the processor to be in a standby state; the first computer includes a first processor and a second processor.

2. The method of claim 1, further comprising:

the debugging connector receives the stop signal and forwards the stop signal to the second computer;

the second computer receives the stop signal and forwards the stop signal to the third processor and the fourth processor; wherein the second computer comprises a third processor and a fourth processor;

the third processor and the fourth processor receive the stop signal and are in a standby state; wherein the first computer and the second computer are different.

3. The method of claim 2, further comprising:

the debugging connector receives the stop signal and forwards the stop signal to a third computer;

the third computer receives the stop signal and forwards the stop signal to the fifth processor and the sixth processor; wherein the third computer comprises a fifth processor and a sixth processor;

the fifth processor and the sixth processor receive the stop signal and are in a standby state; wherein the first computer and the third computer are different.

4. The method of claim 3, wherein the debug connector is connected to the first computer, the second computer, and the third computer, respectively.

5. The method of claim 4, wherein the debug connector is further connected to the debug host computer.

6. The method of claim 5, further comprising:

and the debugging upper computer sends a debugging instruction, and the debugging connector receives the debugging instruction and forwards the debugging instruction to the first processor, the second processor, the third processor, the fourth processor, the fifth processor and the sixth processor.

7. The method of claim 6, wherein the first processor is connected to the second processor; the third processor is connected with the fourth processor; the fifth processor is connected with the sixth processor.

8. The method of claim 5, wherein the debug host computer is connected to the debug connector via a debug bus; and the data line of the stop signal is connected with an external interrupt pin of the processor.

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