CN114356411A - A hard disk power-on and power-off control system applied to an Ampere server - Google Patents

Abstract

The embodiment of the application provides a hard disk power-on and power-off control system applied to an ampere server, which is used for solving the problems of platform downtime, hard disk identification errors and the like possibly caused by the fact that an ampere service platform powers on and off an idle hard disk. The hard disk power-on and power-off control system comprises a BMC, a CPLD, a hard disk connector and a CPU; the hard disk connector is used for inserting a hard disk; the BMC is used for sending a power-down command to the CPLD, and the power-down command is used for powering down the hard disk; the CPLD is used for receiving a power-down command from the BMC and sending first notification information to the CPU according to the power-down command, wherein the first notification information is used for indicating that the hard disk is in an out-of-position state; the CPU is used for receiving the first notification information from the CPLD and cutting off PCIe connection corresponding to the hard disk according to the first notification information.

Description

A hard disk power-on and power-off control system applied to an Ampere server

technical field

The present application relates to the technical field of server hard disk management, and in particular, to a hard disk power-on and power-off control system applied to an Ampere server.

Background technique

Currently, Ampere servers only support violent hot-plugging of non-volatile memory express (NVMe) hard drives. Simply cutting off the 12V power supply of NVMe hard drives will result in high-speed connection of peripheral components to Ampere servers. interconnect express, PCIe) is incorrectly identified and leads to downtime. In addition, when the hard disk is in an idle state, if the server continues to supply power to the hard disk, it will cause a large waste of power resources of the server, which is not conducive to saving energy. At the same time, a large amount of heat energy is generated in the server chassis, which causes the server to operate in a high temperature environment for a long time, resulting in the attenuation of the working life.

When it is necessary to unplug the NVMe hard disk in the idle state in the backplane of the Ampere server platform, the server maintenance personnel must perform the unplugging operation on the NVMe hard disk, which not only increases the complexity of the maintenance personnel's work, but also increases the probability of the maintenance personnel unplugging the wrong hard disk. .

At present, there is an urgent need for a power-on and power-off solution for hard disks applied to the Ampere server, to solve the problem that when the Ampere server platform is powered on and off the NVMe hard disk, the Ampere server platform may be down, the hard disk is identified incorrectly, and the NVMe hard disk needs to be manually plugged and unplugged. The problem.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a hard disk power-on and power-off control system applied to an Ampere server, which is used to solve problems such as platform downtime and hard disk identification errors that may be caused by power-on and power-off of idle hard disks on the Ampere service platform.

In the first aspect, an embodiment of the present application provides a hard disk power-on/off control system applied to an Ampere server, including a baseboard management controller BMC, a complex programmable logic device CPLD, a hard disk connector, and a central processing unit CPU; wherein, the hard disk The connector is used to insert the hard disk; the BMC is used to send a power-off command to the CPLD, and the power-off command is used to power off the hard disk; the CPLD is used to receive the power-off command from the BMC. a power-on command, sending first notification information to the CPU according to the power-off command, where the first notification information is used to indicate that the hard disk is in an out-of-position state; the CPU is used to receive the first notification information from the CPLD Notification information, according to the first notification information, cut off the high-speed serial computer expansion bus standard PCIe connection corresponding to the hard disk.

In a possible design, the CPLD sends the first notification information to the CPU according to the power-off command, including: after receiving the power-off command, inverting the value of the first register and storing it in the CPU The second register and the first chip simulated by the CPLD, the value of the first register is used to indicate that a hard disk is inserted, and the value of the first chip simulated by the CPLD is used to indicate that the hard disk is in the in-position state or not in position state; if it is detected that the value of the second register changes, the hot-plug alarm signal with the CPU is set to a low level.

In a possible design, the CPU receives the first notification information from the CPLD, and cuts off the PCIE connection corresponding to the hard disk according to the first notification information, including: After the hot-plug alarm signal between the CPLDs is at a low level, read the value of the first chip simulated by the CPLD; after determining that the hard disk is in an out-of-position state according to the value of the first chip simulated by the CPLD, Cut off the PCIe connection corresponding to the hard disk.

In a possible design, the CPLD is further configured to disable the power supply control signal of the hard disk connector after receiving the power-off command and sending the first notification information.

In a possible design, the BMC is configured to send a power-on command to the CPLD, where the power-on command is used to power on the hard disk; the CPLD is further configured to receive data from the BMC the power-on command, send second notification information to the CPU according to the power-on command, and the second notification information is used to indicate that the hard disk is in the in-position state; the CPU is also used to receive data from all The second notification information of the CPLD is used, and a PCIE connection corresponding to the hard disk is established according to the second notification information.

In a possible design, the CPLD sends the second notification information to the CPU according to the power-on command, including: after receiving the power-on command, storing the value of the first register in the second register and the first chip simulated by the CPLD, the value of the first register is used to indicate that a hard disk is inserted, and the value of the first chip simulated by the CPLD is used to indicate that the hard disk is in the in-position state or not in the in-position state; if If it is detected that the value of the second register changes, the hot-plug alarm signal with the CPU is set to a low level.

In a possible design, the CPU receives the second notification information from the CPLD, and establishes a PCIE connection corresponding to the hard disk according to the second notification information, including: After the hot-plug alarm signal between the CPLDs is at a low level, read the value of the first chip simulated by the CPLD; after determining that the hard disk is in the in-position state according to the value of the first chip simulated by the CPLD, A PCIe connection corresponding to the hard disk is established.

In a possible design, the CPLD is further configured to enable the power supply control signal of the hard disk connector after receiving the power-on command and sending the second notification information.

In a possible design, the CPLD is further configured to, at each rising edge of the clock, detect the PRSNT signal value and the IFDET signal value transmitted between the hard disk connector and the hard disk connector, and after inverting the PRSNT signal value The operation result of OR operation with the IFDET signal value is stored in the first register.

In a second aspect, an embodiment of the present application provides an Ampere server, where the Ampere server includes the baseboard management controller BMC according to any one of the first aspects, a complex programmable logic device CPLD, a hard disk connector, and a central processing unit CPU.

In this embodiment of the present application, after receiving the power-off command from the BMC, the CPLD sends first notification information to the CPU according to the power-off command, where the first notification information is used to indicate that the hard disk is in an out-of-position state. After the notification information, it can be considered that the NVMe hard disk is no longer in place at this time, and the PCIe connection corresponding to the NVMe hard disk is then cut off. This method can realize the remote power-off control of the NVMe hard disk through the BMC, and avoid the problem of the downtime of the Ampere server due to the violent destruction of the PCIe connection state. In addition, since the CPLD has notified the CPU that the NVMe hard disk is not in place, the drive letter under the OS will also disappear.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic diagram of a hard disk power-on and power-off control system applied to an Ampere server provided by an embodiment of the present application;

2 is a schematic diagram of a signal processing flow of a CPLD applied to a hard disk power-on/off control system of an Ampere server according to an embodiment of the present application;

3 is a schematic diagram of an Ampere server provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of hardware of a hard disk power-on and power-off control system applied to an Ampere server according to an embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In the embodiments of the present application, a plurality of refers to two or more. Words such as "first" and "second" are only used for the purpose of distinguishing and describing, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

FIG. 1 exemplarily shows a hard disk power-on/off control system applied to an Ampere server provided by an embodiment of the present application. As shown in FIG. 1 , the hard disk power-on/off control system includes a baseboard manager controller (BMC) , complex programmable logic device (complex programming logic device, CPLD), hard disk connector and central processing unit (central processing unit, CPU).

The CPLD powers on or off the 12V power supply of the hard disk through a power supply control circuit, wherein the power supply control circuit may include a power supply chip with a model of MP5000ADQ_LF_Z. The Pin4 pin and Pin10 pin of the U.2 specification hard disk connector are connected to the CPLD through general-purpose input/output (GPIO), among which, the Pin4 pin transmits the IFDET signal, and the Pin10 pin Transmit the PRSNT signal. The hard disk connector can be used to plug hard disks of various specifications such as SATA hard disks, SAS hard disks or NVMe hard disks.

The BMC and the CPLD perform data interaction through an integrated circuit bus (inter-integrated circuit, IIC). The BMC sends a power-on command or a power-off command to the CPLD, where the power-on command is used to power on the hard disk, and the power-off command is used to power off the hard disk. After detecting that a hard disk is inserted, the CPLD can send the hard disk status information of the corresponding slot to the BMC, so that the BMC can know which slot has a hard disk inserted in the hard disk connector.

It should be noted that the power-on or power-off command to the hard disk is usually a fixed value, which is determined by the CPLD and submitted to the BMC. For example, the command can be a byte, that is, an 8-digit number consisting of 0 or 1. The last two digits of the command can indicate power-on or power-off of the hard disk. For example, 01 indicates that the NVMe hard disk is powered off, and 10 Indicates the power-on operation of the NVMe hard disk. The remaining 6 bits of the command can indicate which slot the NVMe hard disk is inserted into the hard disk connector to power on or power off. For example, 00000101 indicates the hard disk connector in slot 000001. Power off the NVMe hard disk inserted on the top, 00001010 means power on the NVMe hard disk inserted in the hard disk connector in slot 000010. The above-mentioned representation of the power-on command or the power-off command is only an example, which is not limited in this application.

The CPLD exchanges data with the CPU through a set of virtual pin ports (VPPs), and the set of VPPs is composed of an IIC module and a first chip simulated by the CPLD. The first chip can be a chip with a model of PCA9535 or a chip with a model of PCA9555, and the CPU can read the value of the first chip simulated by the CPLD. The following describes the technical solution of the present application in detail by taking the chip with the model of PCA9555 as an example. . The CPLD and CPU also have a single-ended GPIO signal as the hot-plug alarm signal (Hot_Plug_Alert) that the CPLD informs the CPU. After receiving the power-on or power-off command from the BMC, the CPLD sends first notification information to the CPU according to the power-on or power-off command, where the first notification information is used to indicate the in-position state of the hard disk. The CPU receives the first notification information from the CPLD, and cuts off or establishes the PCIe connection corresponding to the hard disk according to the first notification information.

When maintenance personnel need to stop the work of an idle NVMe hard disk and perform power-off processing, they first send a power-off command to the CPLD through the BMC. After receiving the power-off command sent by the BMC, the CPLD compares the data format of the command (used to determine the specific disk number), and sends the first notification information to the CPU according to the power-off command. The first notification information is used to indicate the NVMe hard disk. in an absent state. After receiving the first notification information from the CPLD, the CPU cuts off the high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) connection corresponding to the NVMe hard disk according to the first notification information. After that, the CPLD disables the power supply control signal of the hard disk connector, and cuts off the 12V power supply from the Ampere server to the NVMe hard disk. The power supply control signal is an enable signal of the power supply control circuit of the hard disk connector. In this way, the problem of crashing the Ampere server due to the violent destruction of the PCIe connection state can be avoided, and since the CPU has been notified that the NVMe hard disk is not in place before the CPLD disables the power supply control signal of the hard disk connector, the operating system (operating system) , OS), the drive letter will also disappear.

Specifically, on each rising edge of the clock, the CPLD detects the PRSNT signal value and the IFDET signal value transmitted between the CPLD and the hard disk connector, and stores the result of the OR operation with the IFDET signal value after inverting the PRSNT signal value. a register. After the CPLD receives the power-off command, it inverts the value of the first register and stores it in the second register and the PCA9555 simulated by the CPLD. The value of the first register is used to indicate that the NVMe hard disk is inserted, and the value of the PCA9555 simulated by the CPLD is used to indicate that the NVMe hard disk is in the in-position state or not in the in-position state. If the CPLD detects that the value of the second register has changed, it sets the hot-plug alarm signal (Hot_Plug_Alert) with the CPU to a low level. The hot-plug alarm signal here is equivalent to an interrupt signal. After the plugging alarm signal becomes low level, the execution of the currently executing program is suspended, and the value of the PCA9555 simulated by the CPLD is read. Optionally, in a possible implementation manner, after receiving the power-off command, the CPLD inverts the value of the first register and stores it in the third register, and then stores the value of the third register in the second register and the CPLD. Emulated PCA9555. The third register is used to temporarily store the inverted value of the first register.

After the CPU detects that the hot-plug alarm signal between the CPU and the CPLD is low, it can read the value of the PCA9555 simulated by the CPLD, determine that the NVMe hard disk is not in place according to the value of the PCA9555 simulated by the CPLD, and then release the hot-plug alarm. signal, and cut off the PCIe connection corresponding to the NVMe hard disk. Wherein, releasing the hot-plug alarm signal refers to converting the hot-plug alarm signal from a low level to a high level, so that the CPU continues to execute the previously executed program, and the CPU can also continue to receive the hot-plug alarm signal from the CPLD.

When maintenance personnel need to power on an idle NVMe hard disk, they first send a power-on command to the CPLD through the BMC. After receiving the power-on command sent by the BMC, the CPLD compares the data format of the command (used to determine the specific disk number), and sends the second notification information to the CPU according to the power-on command. The second notification information is used to indicate the NVMe hard disk. is in place. After receiving the second notification information from the CPLD, the CPU establishes a PCIe connection corresponding to the NVMe hard disk according to the second notification information. After that, the CPLD enables the power supply control signal of the hard disk connector, so that the Ampere server provides 12V power supply to the NVMe hard disk. The power supply control signal is an enable signal of the power supply control circuit of the hard disk connector. Before the CPU of the Ampere server recognizes the PCIe device, it needs to confirm that the device is in place before the PCIe link training action will take place. Otherwise, the PCIe device will not be initialized. The PCIe link training refers to a process in which devices at both ends of the PCIe link are finally allowed to perform data communication by initializing the PCIe link. Therefore, before enabling the power supply control signal of the hard disk connector, the CPLD needs to send the second notification information to the CPU, so that the CPU thinks that the NVMe hard disk is already in place at this time, and then the CPU will initialize the NVMe hard disk independently, so as to avoid the ampere server with The problem that the NVMe hard disk is not recognized when the external power is turned on.

Specifically, on each rising edge of the clock, the CPLD detects the PRSNT signal value and the IFDET signal value transmitted between the CPLD and the hard disk connector, and stores the result of the OR operation with the IFDET signal value after inverting the PRSNT signal value. a register. After the CPLD receives the power-on command, it stores the value of the first register into the second register and the PCA9555 simulated by the CPLD. The value of the first register is used to indicate that the NVMe hard disk is inserted, and the value of the PCA9555 simulated by the CPLD is used to indicate that the NVMe hard disk is in the in-position state or not in the in-position state. If the CPLD detects that the value of the second register changes, it sets the hot-plug alarm signal (Hot_Plug_Alert) with the CPU to a low level. Optionally, in a possible implementation manner, after the CPLD receives the power-off command, it stores the value of the first register in the fourth register, and then stores the value of the fourth register in the second register and the PCA9555 simulated by the CPLD. . The fourth register is used to temporarily store the value of the first register.

After the CPU detects that the hot-plug alarm signal between the CPLD and the CPLD is low, it can read the value of PCA9555 simulated by CPLD, and release the hot-plug alarm after confirming that the NVMe hard disk is in place according to the value of PCA9555 simulated by CPLD. signal, and establish a PCIe connection corresponding to the NVMe hard disk.

In order to understand the embodiments of the present application more clearly, the following describes the signal processing flow of the CPLD in the technical solution of the present application in detail with reference to FIG. 2 and Table 1. FIG.

Table 1 shows the state changes of PIN10 and PIN4 when SAS/SATA hard disks and NVMe hard disks are inserted or pulled out.

Table 1

Step 201: The CPLD detects whether the IFDET value of Pin4 becomes low. If it becomes low, it indicates that a hard disk has been inserted, and then executes step 202;

It can be seen from Table 1 that when the SATA/SAS hard disk or NVMe hard disk is inserted into the hard disk connector on the backplane of the Ampere server, the IFDET signal of Pin4 is all low level. After the CPLD detects that the IFDET value becomes low, the enable terminal of the 12V power supply IC of the hard disk is enabled, and the hard disk is powered on. It should be noted that, whether it is a SATA/SAS hard disk or an NVMe hard disk, as long as the CPLD detects that a hard disk is inserted, it will be powered on.

Step 202: The CPLD detects the values of PRSNT and IFDET, inverts the value of PRSNT and performs OR operation with IFDET, and puts the calculation result into register A (equivalent to the first register).

The calculation result is 0 when an NVMe hard disk is inserted, 1 when no NVMe hard disk is inserted, and 1 whether a SATA/SAS hard disk is inserted or not. Taking an NVMe hard disk as an example, when the NVMe hard disk is inserted, PRSNT is at a high level (ie, 1), and IFDET is at a low level (ie, 0). After the inversion of PRSNT, it becomes 0, and after the OR operation with IFDET, the calculation result is 0; when the NVMe hard disk is pulled out, PRSNT is low and high, which is 0, and IFDET is high, which is 1. After PRSNT is inverted, it becomes 1, and after OR operation with IFDET, the calculation result is 1.

Step 203: Determine whether the value of register A is 0, if it is 0, execute step 204; if it is not 0, execute step 202 repeatedly.

According to the calculation result in step 202, it can be known that the calculation result is 0 only when the NVMe hard disk is inserted. Therefore, it can be determined whether an NVMe hard disk is inserted by judging whether the value of the register A is 0 or not.

Step 204: The CPLD detects whether the BMC sends a power-on command or a power-off command. If a power-off command is sent, step 205 is executed; if a power-on command is sent, step 206 is executed.

Step 205: Invert the value of register A and store it in register D (equivalent to the second register) and the PCA9555 simulated by CPLD. Optionally, first invert the value of register A and store it in register B (equivalent to the third register), and then store the value of register B into register D and the PCA9555 simulated by CPLD.

Specifically, the value of register A is 0, and the value of A is inverted and stored in register D and the PCA9555 simulated by CPLD. At this time, the value of register D is 1, and the value of PCA9555 simulated by CPLD is 1.

Step 206: Store the value of register A into register D and the PCA9555 simulated by CPLD. Optionally, first store the value of register A into register C (equivalent to the fourth register), and then store the value of register C into register D and the PCA9555 simulated by the CPLD.

Specifically, the value of register A is 0, and the value of A is inverted and stored in register D and the PCA9555 simulated by CPLD. At this time, the value of register D is 0, and the value of PCA9555 simulated by CPLD is 0.

Step 207: The CPLD detects whether the value of the register D changes, and if it changes, executes step 208; if there is no change, executes step 202 repeatedly.

The CPLD detects whether the value of register D changes. If it changes, it means that a power-on or power-off command is issued.

The CPLD calculates the values of PRSNT and IFDET at each rising edge of the clock, stores the calculation result in register A, and then processes the value of register A and stores it in register D. Register D stores the current calculated value, which is called It is the current state. Since the value stored before the D register has been processed by multiple clocks, its value is the calculation result before multiple clocks, which is called the next state. If there is a power-on command or a power-off command, the value of register D will change, so the next state and the current state are not equal.

Step 208: Set the Hot_Plug_Alert signal directly connected between the CPLD and the CPU to a low level.

When the CPLD detects that a power-on command or a power-off command is issued, the Hot_Plug_Alert signal directly connected between the CPLD and the CPU is set to a low level.

Step 209, the CPU reads the value of the PCA9555 simulated by the CPLD.

The CPU reads the value of PCA9555 simulated by CPLD. The value of PCA9555 simulated by CPLD is 1, which means that the NVMe hard disk is not in place, and the value of PCA9555 simulated by CPLD is 0, which means that the NVMe hard disk is in place.

After the CPU read is completed, the Hot_Plug_Alert signal is released. The CPLD then disables the power supply control signal of the hard disk connector according to the power-off command to power off the NVMe hard disk; or enables the power supply control signal of the hard disk connector according to the power-on command to power on the NVMe hard disk.

An embodiment of the present application provides a hard disk power-on and power-off control system applied to an Ampere server. When the NVMe hard disk inserted on the backplane of the Ampere server needs to be powered off, the power supply control signal of the hard disk connector can be disabled before enabling the power supply control signal. Send a hot-plug alarm signal to the CPU, triggering the CPU to read the value of the PCA9555 simulated by the CPLD. According to the value of PCA9555 simulated by CPLD, the CPU can determine that the NVMe hard disk is no longer in place at this time, and can then disconnect the PCIe connection. It can be seen that this solution can realize the remote power-off control of the NVMe hard disk through the BMC, and can avoid the problem of the downtime of the Ampere server due to the violent destruction of the PCIe connection state. In addition, since the CPU has been notified that the NVMe hard disk is not in place before the CPLD disables the power supply control signal of the hard disk connector, the drive letter under the OS will also disappear.

When the NVMe hard disk inserted on the backplane of the Ampere server needs to be powered on, a hot-plug alarm signal is sent to the CPU before enabling the power supply control signal of the hard disk connector, which triggers the CPU to read the value of the PCA9555 simulated by the CPLD. The CPU determines that the NVMe hard disk is in place at this time according to the value of the PCA9555 simulated by the CPLD, and then establishes a PCIe connection. It can be seen that this solution can realize remote power-on control of NVMe hard disks through BMC. Since the CPU has been notified that the NVMe hard disk is in place before the CPLD enables the power supply control signal of the hard disk connector, the problem of not recognizing the NVMe hard disk when the Ampere server is powered on out-of-band is avoided.

FIG. 3 exemplarily shows an Ampere server provided by an embodiment of the present application. The Ampere server 300 includes the baseboard management controller BMC310, the complex programmable logic device CPLD 320, the hard disk connector 330 and the Central processing unit CPU340.

FIG. 4 exemplarily shows a schematic diagram of hardware of a hard disk power-on and power-off control system applied to an Ampere server provided by an embodiment of the present application.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

While the preferred embodiments of the present application have been described, additional changes and modifications to these embodiments may occur to those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be construed to include the preferred embodiment and all changes and modifications that fall within the scope of this application.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (10)

1. a hard disk power-on and power-off control system applied to Ampere server, is characterized in that, described hard disk power-on and power-off control system comprises baseboard management controller BMC, complex programmable logic device CPLD, hard disk connector and central processing unit CPU; Wherein , The hard disk connector is used for plugging in a hard disk; The BMC is used to send a power-off command to the CPLD, where the power-off command is used to power off the hard disk; The CPLD is configured to receive the power-off command from the BMC, and send first notification information to the CPU according to the power-off command, where the first notification information is used to indicate that the hard disk is in an out-of-position state; The CPU is configured to receive the first notification information from the CPLD, and cut off the high-speed serial computer expansion bus standard PCIe connection corresponding to the hard disk according to the first notification information. 2. The system according to claim 1, wherein the CPLD sends first notification information to the CPU according to the power-off command, comprising: After receiving the power-off command, invert the value of the first register and store it in the second register and the first chip simulated by the CPLD. The value of the first register is used to indicate that there is a hard disk inserted, and the CPLD The value of the simulated first chip is used to indicate that the hard disk is in the in-position state or in the in-position state; If it is detected that the value of the second register changes, the hot-plug alarm signal with the CPU is set to a low level. 3. The system according to claim 2, wherein the CPU receives the first notification information from the CPLD, and cuts off the PCIe connection corresponding to the hard disk according to the first notification information, comprising: After the CPU detects that the hot-plug alarm signal between the CPU and the CPLD is a low level, it reads the value of the first chip simulated by the CPLD; After it is determined that the hard disk is in an out-of-position state according to the value of the first chip simulated by the CPLD, the PCIe connection corresponding to the hard disk is cut off. 4 . The system according to claim 1 , wherein the CPLD is further configured to, after receiving the power-off command and sending the first notification information, disable power supply of the hard disk connector. 5 . control signal. 5. The system according to claim 1, wherein the BMC is used to send a power-on command to the CPLD, and the power-on command is used to power on the hard disk; The CPLD is further configured to receive the power-on command from the BMC, and send second notification information to the CPU according to the power-on command, where the second notification information is used to indicate that the hard disk is in place state; The CPU is further configured to receive second notification information from the CPLD, and establish a PCIe connection corresponding to the hard disk according to the second notification information. 6. The system according to claim 5, wherein the CPLD sends second notification information to the CPU according to the power-on command, comprising: After receiving the power-on command, the value of the first register is stored in the second register and the first chip simulated by the CPLD. The value of a chip is used to indicate that the hard disk is in the in-position state or not in the in-position state; If it is detected that the value of the second register changes, the hot-plug alarm signal with the CPU is set to a low level. 7. The system according to claim 6, wherein the CPU receives the second notification information from the CPLD, and establishes a PCIe connection corresponding to the hard disk according to the second notification information, comprising: After the CPU detects that the hot-plug alarm signal between the CPU and the CPLD is a low level, it reads the value of the first chip simulated by the CPLD; After it is determined that the hard disk is in the in-position state according to the value of the first chip simulated by the CPLD, a PCIe connection corresponding to the hard disk is established. 8. The system according to claim 5, wherein the CPLD is further configured to enable power supply control of the hard disk connector after receiving the power-on command and sending the second notification information Signal. 9. The system according to any one of claims 1 to 8, wherein the CPLD is also used for, At each rising edge of the clock, the PRSNT signal value and the IFDET signal value transmitted between the hard disk connector are detected, and the result of the OR operation with the IFDET signal value after the inversion of the PRSNT signal value is stored in the first a register. 10. An Ampere server, characterized in that the Ampere server comprises a baseboard management controller (BMC), a complex programmable logic device (CPLD), a hard disk connector, and a central processing unit (CPU) as described in any one of claims 1 to 9. .

Images