CN114340139B - Circuit board and electronic equipment - Google Patents
Circuit board and electronic equipment Download PDFInfo
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- CN114340139B CN114340139B CN202111433718.6A CN202111433718A CN114340139B CN 114340139 B CN114340139 B CN 114340139B CN 202111433718 A CN202111433718 A CN 202111433718A CN 114340139 B CN114340139 B CN 114340139B
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- 239000002184 metal Substances 0.000 claims abstract description 123
- 229910052751 metal Inorganic materials 0.000 claims abstract description 123
- 230000008054 signal transmission Effects 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims description 25
- 229920005989 resin Polymers 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 22
- 229920001955 polyphenylene ether Polymers 0.000 claims description 11
- 239000013039 cover film Substances 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 abstract description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 25
- 239000004810 polytetrafluoroethylene Substances 0.000 description 25
- 229940058401 polytetrafluoroethylene Drugs 0.000 description 23
- -1 polytetrafluoroethylene Polymers 0.000 description 22
- 230000005540 biological transmission Effects 0.000 description 19
- 239000006260 foam Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004721 Polyphenylene oxide Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229920006380 polyphenylene oxide Polymers 0.000 description 4
- 229920000106 Liquid crystal polymer Polymers 0.000 description 3
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 238000003801 milling Methods 0.000 description 3
- 229920013636 polyphenyl ether polymer Polymers 0.000 description 3
- 238000012805 post-processing Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
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- 230000017525 heat dissipation Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 125000001033 ether group Chemical group 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
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- 239000011521 glass Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application discloses a circuit board and electronic equipment, wherein the circuit board comprises a first dielectric layer and a second dielectric layer which are sequentially stacked along the thickness direction, an inner layer sub-board is filled in the second dielectric layer, the inner layer sub-board is provided with a through groove penetrating through the inner layer sub-board along the thickness direction, one side of the first dielectric layer, which is away from the second dielectric layer, is provided with a first metal layer, a second metal layer is arranged between the first dielectric layer and the second dielectric layer, the second metal layer is provided with a first opening, the surface of the inner layer sub-board is provided with a third metal layer, and one side of the second dielectric layer, which is away from the first dielectric layer, is provided with a fourth metal layer. The circuit board can effectively reduce signal transmission loss.
Description
Technical Field
The present application relates to the field of radar technologies, and in particular, to a circuit board and an electronic device.
Background
Technology of millimeter wave radar is continuously developed in view of urgent demands for vehicle-mounted imaging radar. The planar phased array antenna is a common design mode of millimeter radar waves, the radio frequency chip and the antenna of the traditional millimeter wave radar can realize coplanar design, but because more antenna arrays are needed for high-density point cloud imaging, the antenna surface space of a circuit board is limited, part of the radio frequency chip needs to be distributed on the bottom surface of the circuit board, at the moment, antenna microwave signals need to be transmitted from the antenna surface to the bottom surface of the circuit board, the antenna signals are interconnected from the antenna surface to the bottom surface through a via hole in the traditional design, but because the frequency of the vehicle-mounted radar is as high as 77GHz, the loss of the traditional via hole is very high, and the loss becomes a main factor affecting the performance of the antenna.
Disclosure of Invention
The application provides a circuit board and electronic equipment, which are used for reducing the transmission loss of the circuit board and reducing the production cost.
In a first aspect, the present application provides a circuit board, including a first dielectric layer, a second dielectric layer, and an inner layer sub-board, where the first dielectric layer and the second dielectric layer are stacked in sequence along a thickness direction, the inner layer sub-board is filled in the second dielectric layer, and the inner layer sub-board is provided with a through slot penetrating through itself along the thickness direction, and the through slot can be used for signal transmission. In addition, one side that first dielectric layer deviates from the second dielectric layer is equipped with first metal level, is equipped with the second metal level between first dielectric layer and the second dielectric layer, is equipped with the third metal level between first inlayer subplate and the second dielectric layer, and one side that second dielectric layer deviates from first dielectric layer is equipped with the fourth metal level, and wherein, the second metal level still is equipped with first opening to make first dielectric layer accessible first opening and second dielectric layer intercommunication.
Compared with the traditional circuit board, the inner-layer sub-board is filled in the second medium layer, and the through grooves are formed in the inner-layer sub-board to transmit signals, so that signals on the upper surface of the circuit board can be transmitted to the lower surface of the circuit board after sequentially passing through the first metal layer, the first medium layer, the first opening, the second medium layer, the through grooves and the fourth metal layer.
In some possible embodiments, the material of the second dielectric layer may be a polyphenylene ether resin, and the transmission loss may be reduced due to the low dielectric loss (Df) of the polyphenylene ether resin.
In some possible embodiments, the through slots may also be filled with a dielectric block, and the dielectric loss (Df) of the dielectric block may be 0.004 or less, so that the transmission loss can be further reduced when the signal passes through the through slots.
In some embodiments, the material of the dielectric block comprises fluororesin, which may be fluororesin or a composite material thereof, and when in implementation, the dielectric block may be polytetrafluoroethylene block or polytetrafluoroethylene foam, so that dielectric loss can be further reduced.
In some possible embodiments, the two end openings of the through groove can be respectively provided with a cover film, and the cover films cover the two end openings, so that an air-filled closed space is formed inside the through groove, and the loss can be further reduced due to low dielectric loss of air.
In some possible embodiments, the first metal layer is further provided with a first shielding hole, so as to avoid poor shielding, and one end of the first shielding hole is electrically connected with the first metal layer, and the other end of the first shielding hole extends to the third metal layer and is electrically connected with the third metal layer, so that radiation loss is effectively reduced.
In some possible embodiments, the fourth metal layer is further provided with a second shielding hole, so as to avoid a situation of poor shielding, one end of the second shielding hole is electrically connected with the fourth metal layer, and the other end of the second shielding hole extends to the third metal layer and is electrically connected with the third metal layer, thereby effectively reducing radiation loss.
In some possible embodiments, the circuit board is further provided with a metallized via penetrating the circuit board in the thickness direction, the metallized via being disposed away from the open slot so as to facilitate signal interconnection, and shielding heat dissipation may also be achieved.
In some possible embodiments, the circuit board further includes a third dielectric layer between the second dielectric layer and the fourth metal layer, a fifth metal layer is disposed between the third dielectric layer and the second dielectric layer, and the fifth metal layer is provided with a second opening, such that the second dielectric layer can communicate with the third dielectric layer through the second opening.
In a second aspect, the present application further provides an electronic device, including an antenna, a radio frequency chip, and a circuit board in any of the foregoing embodiments, where the antenna is disposed on a surface of a first metal layer of the circuit board, and the radio frequency chip is disposed on a surface of a fourth metal layer of the circuit board.
Drawings
Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a circuit board according to an embodiment of the present application;
fig. 3 is a schematic top view of a circuit board according to an embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of the circuit board of FIG. 1;
FIG. 5 is a schematic diagram of a cross-sectional structure of the circuit board in FIG. 1;
FIG. 6 is a schematic illustration of a loss simulation of the foam of the fill media of FIG. 4;
FIG. 7 is a schematic diagram of a cross-sectional structure of the circuit board shown in FIG. 1;
fig. 8 is a schematic diagram of a cross-sectional structure of the circuit board in fig. 1.
Reference numerals:
1-a circuit board; a 2-antenna; 3-a radio frequency chip; 10-a first dielectric layer; 20-a second dielectric layer; 30-inner layer sub-boards; 31-through grooves; 40-a first metal layer; 50-a second metal layer; 51-a first opening; 60-a third metal layer; 70-a fourth metal layer; 80-a first shielding hole; 90-a second shielding hole; 100-medium blocks; 110-a cover film; 120-metallizing the via; 130-a third dielectric layer; 140-fifth metal layer; 141-a second opening; 150-a first wire; 160-second wire.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.
In embodiments of the present application, the terms "first," "second," "third," "fourth," "fifth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "first", "second", "third", "fourth", "fifth" may explicitly or implicitly include one or more such feature.
In the embodiment of the present application, "and/or" is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship. Connection includes direct connection or indirect connection.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
The planar phased array antenna is the most commonly used design mode of millimeter wave radar, the radio frequency chip and the antenna of the traditional 3T4R millimeter wave radar can realize the coplanar design on a circuit board, but the high-density point cloud imaging needs more antenna arrays, and because the antenna surface space of the circuit board is limited, part of the radio frequency chip needs to be distributed on the bottom surface of the circuit board, and the radio frequency chip and the antenna are not coplanar. The antenna microwave signals need to be transmitted from the antenna surface to the bottom surface, and the antenna signals are interconnected from the antenna surface to the bottom surface through the via holes in the traditional design, but the loss of the traditional via holes is very high due to the fact that the frequency of the vehicle-mounted radar is as high as 77 GHz.
Based on the above, the embodiment of the application provides a circuit board which can be applied to electronic equipment for realizing functions of electric interconnection, signal transmission and the like of electronic components so as to meet the electric characteristics required by the electronic equipment, wherein the electronic equipment can be equipment such as a mobile phone, a tablet computer, a notebook computer, a server, a router, a switch, a vehicle-mounted radar and the like in the prior art.
In this embodiment, an electronic device is described as an in-vehicle radar. As shown in fig. 1, the vehicle-mounted radar comprises a circuit board 1, a radio frequency chip 3 and a radio frequency transceiver circuit are arranged on the circuit board 1, the radio frequency chip 3 can be arranged on the circuit board in a wafer level packaging or inverted packaging mode, and the radio frequency transceiver circuit is connected with a radio frequency port of the radio frequency chip 3. The vehicle-mounted radar can further comprise an antenna 2, the antenna 2 can comprise a dielectric substrate and a radiator, the dielectric substrate can be used for supporting and fixing the radiator, the radiator is arranged on the dielectric substrate, the radiator can be electrically connected with the radio frequency transceiver circuit through a feed transmission line, so that the radio frequency transceiver circuit can convert current energy fed into the antenna 2 through the feed transmission line into electromagnetic energy to radiate, and electromagnetic energy received by the antenna 2 can be converted into current energy to be transmitted to the radio frequency transceiver circuit through the feed transmission line, and the vehicle-mounted radar can achieve a signal transceiving function. The vehicle-mounted radar can be mounted on a vehicle, and can be used for finding obstacles, predicting collision, self-adaptive cruise control and the like when in use so as to assist the vehicle to realize an intelligent driving function.
Referring to fig. 2 to 4, the circuit board includes a first dielectric layer 10 and a second dielectric layer 20 stacked in a thickness direction, the second dielectric layer 20 being internally filled with an inner-layer sub-board 30, the inner-layer sub-board having a through slot 31, the through slot 31 being penetratable through the inner-layer sub-board 30 in the thickness direction for signal transmission. The side of the first dielectric layer 10 facing away from the second dielectric layer 20 may be provided with a first metal layer 40, the surface of the first metal layer 40 may be provided with a first conductive wire 150, the first conductive wire 150 is electrically connected with the first metal layer 40, and illustratively, the first metal layer 40 may be a copper sheet, the side of the first conductive wire 150 facing toward the first metal layer 40 also has a copper sheet, and the copper sheet of the first conductive wire 150 is connected with the first metal layer 40 to realize signal transmission. A second metal layer 50 may be disposed between the first dielectric layer 10 and the second dielectric layer 20, the second metal layer 50 may be provided with a first opening 51, and the first dielectric layer 10 may be in communication with the second dielectric layer 20 through the first opening 51. A third metal layer 60 may be disposed between the second dielectric layer 20 and the inner layer daughter board 30, a fourth metal layer 70 may be disposed on a side of the second dielectric layer 20 facing away from the first dielectric layer 10, a second conductive wire 160 may be disposed on a surface of the fourth metal layer 70, the second conductive wire 160 is electrically connected with the fourth metal layer 70, and illustratively, the fourth metal layer 70 may be a copper sheet, a copper sheet is also disposed on a side of the second conductive wire 160 facing toward the fourth metal layer 70, and the copper sheet of the second conductive wire 160 is connected with the fourth metal layer 70 to realize signal transmission.
The material of the first dielectric layer 10 may be a material with low dielectric loss (Df), for example, the material of the first dielectric layer 10 may be RO3003, that is, ceramic filled polytetrafluoroethylene (poly tetra fluoroethylene, PTFE) composite material, NF30, R5515 (thermosetting resin material), industrialized liquid crystal polymer (liquid crystal polymer, LCP), and the like, which has good mechanical stability and electrical performance, low dielectric loss, not only ensures good signal transmission, but also facilitates reduction of transmission loss.
In some embodiments, the material of the second dielectric layer 20 may be a low-loss resin such as polyphenylene ether, and the dielectric loss (Df) of the low-loss resin such as polyphenylene ether is also relatively low, so that it is advantageous to further reduce the transmission loss. In addition, since the use of low-loss resin such as polyphenylene ether is avoided, the cost can be reduced conveniently. In one implementation, a low-loss resin such as polyphenylene ether and the like may be laminated together with the inner-layer sub-board 30, so that the inner-layer sub-board 30 is filled in the second dielectric layer 20, so as to simplify the process flow. Since the inner-layer sub-board 30 is provided with the through groove 31, when the low-loss resin such as polyphenylene ether is used to press the inner-layer sub-board 30, the through groove 31 may be filled with the low-loss resin such as polyphenylene ether.
The inner layer sub-board 30 may be a double-sided board or a multi-layer board, and when the inner layer sub-board 30 is a multi-layer board, the inner layer sub-board may be a four-layer board, a five-layer board, a six-layer board, or the like, and the specific structure thereof may be designed according to the signal to be transmitted, which is not limited in the present application. The inner layer sub-board 30 can be made of FR4 (epoxy glass cloth laminated board) board, the electrical insulation of the FR4 board is good, the dielectric loss (Df) is low, the surface is smooth, and the conductor loss can be effectively reduced.
In this embodiment, the first conductive wire 150 may be electrically connected to a component disposed on the surface of the first metal layer 40 of the circuit board, the second conductive wire 160 may be electrically connected to a component disposed on the surface of the fourth metal layer 70 of the circuit board, and the component disposed on the surface of the first metal layer 40 of the circuit board may be an antenna, and the component disposed on the surface of the fourth metal layer 70 may be a radio frequency chip. At this time, the path of signal transmission on the circuit board may be: the antenna, the first wire 150, the first metal layer 40, the first dielectric layer 10, the first opening 51, the second dielectric layer 20, the through groove 31, the second dielectric layer 20, the fourth metal layer 70, the second wire 160 and the radio frequency chip are transmitted by adopting the through groove structure in the signal transmission process of the circuit board, so that the through hole design is avoided, the conductor loss can be reduced, and the through groove 31 structure is adopted, so that the process tolerance of the circuit board is large, the impedance matching performance is good, the yield of the circuit board can be improved, and the reflection loss is reduced.
The first conductive line 150 and the second conductive line 160 are both used for transmitting microwave signals, and when the circuit board is applied to an electronic device with a higher operating frequency, for example, a millimeter wave radar with an operating frequency of 77GHz, the first conductive line 150 and the second conductive line 160 may be specifically microstrip lines, so as to improve the efficiency of signal transmission.
Referring to fig. 3, the cross-sectional shape of the through groove 31 perpendicular to the thickness direction may be substantially rectangular, and it is to be noted that when the operating frequency of the transmission signal is higher, the volume of the through groove 31 is smaller, and for example, in the millimeter wave radar having an operating frequency of 77GHz, the cross-sectional size of the through groove 31 may be designed to be a=1.5 mm, b=2 mm, due to the higher operating frequency. Referring to fig. 4, the inner wall of the through groove 31 is further provided with a third metal layer 60, and by providing the third metal layer 60 for shielding, not only leakage loss can be reduced, but also roughness of the inner wall of the through groove 31 can be reduced, so that the inner wall of the through groove 31 is smoother, and transmission loss can be further reduced.
With continued reference to fig. 4, in some embodiments, the circuit board is further provided with a first shielding hole 80, where the first shielding hole 80 may be a blind hole formed in the first metal layer 40, the sidewall of the first shielding hole 80 is made of metal, and the first shielding hole 80 may extend from the first metal layer 40 to a side of the third metal layer 60 facing the first dielectric layer 10 after passing through the first dielectric layer 10, so as to electrically connect the first metal layer 40 and the third metal layer 60. The first shielding hole 80 can prevent electromagnetic leakage in the through slot 31, thereby improving shielding performance and reducing signal transmission loss. The first shielding hole 80 may be filled with a material such as a resin, or may be not filled with a medium, which is not limited herein.
In this embodiment, the number of the first shielding holes 80 may be one or more, and, for example, as shown in fig. 3, when the number of the first shielding holes 80 is plural, the plurality of first shielding holes 80 may be uniformly distributed around the circumference of the through slot 31 to further improve the shielding performance to the through slot.
With continued reference to fig. 4, in some embodiments, the circuit board is further provided with a second shielding hole 90, where the second shielding hole 90 may be a blind hole formed in the fourth metal layer 70, and a sidewall of the second shielding hole 90 is made of metal, and the second shielding hole 90 may extend from the fourth metal layer 70 into the second dielectric layer 20 to a side of the third metal layer 60 facing the fourth metal layer 70 after extending into the second dielectric layer 20, so as to electrically connect the fourth metal layer 70 with the third metal layer 60. Similar to the first shielding hole 80, the second shielding hole 90 can also avoid electromagnetic leakage in the through slot 31, thereby improving shielding performance and reducing signal transmission loss. The second shielding hole 90 may be filled with a material such as a resin, or may be not filled with a medium, which is not limited herein.
In this embodiment, the number of the second shielding holes 90 may be one or more, and when the number of the second shielding holes 90 is plural, the arrangement manner may refer to the arrangement of the first shielding holes 80, that is, the arrangement is uniformly distributed around the circumference of the through groove 31, so as to further improve the shielding performance to the through groove.
With continued reference to fig. 4, in some embodiments, the circuit board may further be provided with a metallized via 120, and the metallized via 120 penetrates through the circuit board in a thickness direction, and it should be noted that the metallized via 120 may be disposed away from the through slot 31 so as to avoid affecting the signal transmission effect of the through slot 31. The metallized via 120 may be used for signal interconnection and shielding heat dissipation, and its function is the same as that of a conventional circuit board arrangement, and will not be described again here.
In this embodiment, the number of the metallized vias 120 may be one or more, for example, as shown in fig. 3, the metallized vias 120 may be disposed outside the first shielding hole 80 and the second shielding hole 90, and it is also understood that, as viewed from the surface of the first metal layer 40, the metallized vias 120 are located on a side of the first shielding hole 80 away from the through slot 31, and as viewed from the surface of the fourth metal layer 70, the metallized vias 120 are located on a side of the second shielding hole 90 away from the through slot 31.
Taking the circuit board shown in fig. 4 as an example, when the material of the second dielectric layer 20 is filled in the through groove 31, the circuit board may be manufactured by the following process: the inner layer sub-board 30 is first manufactured, the through grooves 31 are formed by milling or drilling at the positions corresponding to the through grooves 31, then the surface of the inner layer sub-board 30 is electroplated to form the third metal layer 60, and then normal etching and browning are performed. The manufactured inner-layer sub-board 30 and the first dielectric layer 10 are pressed into a whole by adopting low-loss resin such as polyphenyl ether, wherein the low-loss resin such as polyphenyl ether forms the second dielectric layer 20, the inner-layer sub-board 30 is coated, and the space in the through groove 31 is directly filled with the low-loss resin such as polyphenyl ether. Then, the first shielding hole 80 and the second shielding hole 90 are formed, the first shielding hole 80 penetrates through the first dielectric layer 10, then extends into the second dielectric layer 20 and is electrically connected with one side of the third metal layer 60 facing the first dielectric layer 10, and the second shielding hole 90 extends into the second dielectric layer 20 and is electrically connected with one side of the third metal layer 60 facing the fourth metal layer 70. Finally, electroplating and post-processing are performed, for example, a first metal layer 40 is formed on a surface of a side of the first dielectric layer 10 facing away from the inner-layer daughter board 30, a first conductive wire 150 is formed on a side of the first metal layer 40 facing away from the first dielectric layer 10, a fourth metal layer 70 is formed on a surface of a side of the second dielectric layer 20 facing away from the first dielectric layer 10, and a second conductive wire 160 is formed on a side of the fourth metal layer 70 facing away from the second dielectric layer 20.
In this embodiment, the circuit board adopts a 2+6+1 structure, that is, a structure of the first dielectric layer 10+the second dielectric layer 20+the inner layer sub-board 30 with six layers, the inner layer sub-board 30 is located at a position opposite to the middle part of the second dielectric layer 20, the material of the first dielectric layer 10 may be RO3003 or other low-loss dielectric materials, the inner layer sub-board 30 may be an FR4 board, and the material of the second dielectric layer 20 may be low-loss resin such as polyphenylene oxide. The manufacturing flow of the circuit board is simple, the resin hole filling process is avoided, and the loss of the dielectric material filled in the through groove 31 is low, so that the transmission loss is reduced.
The process of the present embodiment is suitable for the case where the thickness of the inner sub-board 30 is small and the size of the through groove 31 is small, because the flow of the low-loss resin such as polyphenylene ether is limited.
In some embodiments, referring to fig. 5, a dielectric block 100 may be further disposed in the through slot 31, and when implemented, the dielectric loss (Df) of the dielectric block 100 may be relatively low, so as to further reduce the loss and improve the electrical performance of the circuit board. Illustratively, the dielectric loss (Df) of the dielectric block 100 may be 0.004 or less, thereby effectively reducing transmission loss during signal transmission.
In some embodiments, the material of the dielectric block 100 may be a fluororesin or a composite material thereof, and the transmission loss of signals may be reduced because the dielectric loss (Df) of the fluororesin is low. Or in other embodiments the material of dielectric block 100 may be other low dielectric loss materials.
Referring to fig. 5, when the material of the dielectric block 100 is a fluororesin and a composite material thereof, the material of the dielectric block 100 may be polytetrafluoroethylene (poly tetra fluoroethylene, PTFE), soluble polytetrafluoroethylene (polytetrafluoro ethylene, PFA), or the like, for example. In particular, the dielectric block 100 may be a polytetrafluoroethylene block, or a polytetrafluoroethylene foam, or other low-loss high-temperature-resistant foam, where the polytetrafluoroethylene block has a dielectric constant of 2.1, a dielectric loss (Df) of 0.0001-0.0009, and the polytetrafluoroethylene foam has a dielectric constant of about 1.2, and a dielectric loss (Df) of 0.001. The dielectric loss of the polytetrafluoroethylene block or the polytetrafluoroethylene foam is low, so that the transmission loss is reduced.
In manufacturing the circuit board shown in fig. 5, the inner sub-board 30 may be first formed, the through grooves 31 may be formed by milling or drilling at positions corresponding to the positions where the through grooves 31 are formed, and then the third metal layer 60 and the fourth metal layer 70 may be formed by electroplating on the surface of the inner sub-board 30, and then normally etched and browned. The polytetrafluoroethylene block or polytetrafluoroethylene foam is placed in the through groove 31, and the inner layer sub-board 30 filled with the polytetrafluoroethylene block or polytetrafluoroethylene foam is pressed into one body with the first dielectric layer 10 by using low-loss resin such as polyphenylene oxide, wherein the low-loss resin such as polyphenylene oxide can form the second dielectric layer 20, and the inner layer sub-board 30 filled with the polytetrafluoroethylene block or polytetrafluoroethylene foam is coated. Then, the first shielding hole 80 and the second shielding hole 90 are formed, the first shielding hole 80 penetrates through the first dielectric layer 10, then extends into the second dielectric layer 20 and is electrically connected with one side of the third metal layer 60 facing the first dielectric layer 10, and the second shielding hole 90 extends into the second dielectric layer 20 and is electrically connected with one side of the third metal layer 60 facing the fourth metal layer 70. Finally, electroplating and post-processing are performed, for example, a first metal layer 40 is formed on a surface of a side of the first dielectric layer 10 facing away from the inner-layer daughter board 30, a first conductive wire 150 is formed on a side of the first metal layer 40 facing away from the first dielectric layer 10, a fourth metal layer 70 is formed on a surface of a side of the second dielectric layer 20 facing away from the first dielectric layer 10, and a second conductive wire 160 is formed on a side of the fourth metal layer 70 facing away from the second dielectric layer 20.
In this embodiment, the material of the first dielectric layer 10 may be RO3003 or other low-loss dielectric materials, the inner sub-board 30 may be FR4 board, and the dielectric loss (Df) of the dielectric block 100 filled in the through groove 31 is low, so as to be beneficial to reducing the transmission loss.
Referring to fig. 6, fig. 6 is a schematic diagram of simulation of loss of a circuit board when the through groove 31 is filled with polytetrafluoroethylene foam or other high temperature-resistant low-loss foam, wherein L1 is a curve of transmission loss, L2 and L3 are curves of reflection loss, and as an example, a millimeter wave radar with an operating frequency of 77GHz can be used, dielectric loss (Df) can be reduced to 0.84dB, and reflection loss is also obviously reduced.
It should be noted that, since the through grooves 31 are filled with polytetrafluoroethylene blocks or polytetrafluoroethylene foam, the process of this embodiment is not limited by the flow of resin, and can be applied to the case where the inner sub-board 30 is thicker or the through grooves 31 are larger.
In some embodiments, referring to fig. 7, the through slot 31 may also adopt a cavity design, i.e. the filling medium in the through slot 31 is air, and this design is also beneficial for reducing transmission loss due to the very low dielectric loss (Df) of air. As shown in fig. 7, both end openings of the through groove 31 may be covered with a cover film 110 so that the through groove 31 forms a sealed cavity, thereby preventing the filling resin from flowing into the through groove 31 when the second dielectric layer 20 is formed later.
In manufacturing the circuit board in fig. 7, the inner layer sub-board 30 is first manufactured, the through grooves 31 are formed by milling or drilling at the positions corresponding to the through grooves 31, then the third metal layer 60 is formed by electroplating on each exposed side wall of the inner layer sub-board 30, and then normal etching and browning are performed. The cover film 110 is provided to the openings at both ends of the through groove 31 so that the openings at both ends are sealed, and the inflow into the through groove 31 is prevented when the resin is pressed subsequently. The inner sub-board 30 is laminated with the first dielectric layer 10 as a whole using a low-loss resin such as polyphenylene ether, which can form the second dielectric layer 20 and cover the inner sub-board 30 covered with the cover film 110. Then, the first shielding hole 80 and the second shielding hole 90 are formed, the first shielding hole 80 penetrates through the first dielectric layer 10, then extends into the second dielectric layer 20 and is electrically connected with one side of the third metal layer 60 facing the first dielectric layer 10, and the second shielding hole 90 extends into the second dielectric layer 20 and is electrically connected with one side of the third metal layer 60 facing the fourth metal layer 70. Finally, electroplating and post-processing are performed, for example, a first metal layer 40 is formed on a surface of a side of the first dielectric layer 10 facing away from the inner-layer daughter board 30, a first conductive wire 150 is formed on a side of the first metal layer 40 facing away from the first dielectric layer 10, a fourth metal layer 70 is formed on a surface of a side of the second dielectric layer 20 facing away from the first dielectric layer 10, and a second conductive wire 160 is formed on a side of the fourth metal layer 70 facing away from the second dielectric layer 20.
The cover film 110 may have a laminated structure of a polyimide film and a glue layer, and the glue layer adheres the polyimide film around the openings at both ends of the through groove 31 so as to cover the openings.
In the above embodiment, the material of the first dielectric layer 10 may be RO3003 or other low-loss dielectric materials, the inner sub-board 30 may be FR4 board, and the through groove 31 has a cavity structure, so that the transmission loss can be further reduced due to the relatively low dielectric loss (Df) of air.
In some embodiments, as shown in fig. 8, the circuit board may further include a third dielectric layer 130, where the third dielectric layer 130 is located between the second dielectric layer 20 and the fourth metal layer 70, and a fifth metal layer 140 may be disposed between the third dielectric layer 130 and the second dielectric layer 20, and the fifth metal layer 140 may be provided with a second opening 141, and the second dielectric layer 20 may communicate with the third dielectric layer 130 through the second opening 141. In this embodiment, the path of signal transmission between the upper and lower surfaces of the circuit board may be: first conductor 150, first metal layer 40, first dielectric layer 10, first opening 51, second dielectric layer 20, through slot 31, second dielectric layer 20, second opening 141, third dielectric layer 130, fourth metal layer 70, and second conductor 160.
The material of the third dielectric layer 130 may be the same as that of the second dielectric layer 20, and may be low-loss resin such as polyphenylene oxide, so as to save process flow and reduce cost.
It should be further noted that, in the present embodiment, when the second shielding hole 90 is provided, the structure of the second shielding hole 90 may be similar to that of the second shielding hole 90 in fig. 4, that is, the second shielding hole 90 may be a blind hole formed in the fourth metal layer 70, and the second shielding hole 90 may extend from the fourth metal layer 70 through the third dielectric layer 130 into the second dielectric layer 20 and extend to a side of the third metal layer 60 facing the third dielectric layer 130, so as to electrically connect the fourth metal layer 70 and the third metal layer 60.
Compared with the traditional circuit board with vertical interconnection, the circuit board of the embodiment has the advantages that through grooves are formed, filling media with lower dielectric loss (Df) can be arranged in the through grooves, and metal layers are formed on the side wall surfaces of the through grooves, so that the transmission loss of the vertical interconnection is reduced, the machining precision specification is reduced, the machining yield is improved, the process flow is simplified, and the manufacturing cost of the circuit board is reduced.
The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. The utility model provides a circuit board, its characterized in that, including first dielectric layer and the second dielectric layer that stacks gradually along thickness direction, still including fill in the inside inlayer daughter board of second dielectric layer, the inlayer daughter board is equipped with logical groove, lead to the groove along the thickness direction of circuit board runs through the inlayer daughter board, just it is used for signal transmission to lead to the groove, wherein:
A first metal layer is arranged on one side of the first dielectric layer, which is away from the second dielectric layer;
A second metal layer is arranged between the first medium layer and the second medium layer, the second metal layer is provided with a first opening, and the first medium layer is communicated with the second medium layer through the first opening;
a third metal layer is arranged between the inner-layer sub-board and the second dielectric layer;
A fourth metal layer is arranged on one side, away from the first medium layer, of the second medium layer;
The third metal layer is also arranged on the inner wall of the through groove and is arranged at intervals with the second metal layer through the second dielectric layer;
and a filling medium is arranged in the through groove.
2. The circuit board of claim 1, wherein the material of the second dielectric layer is polyphenylene ether resin.
3. The circuit board of claim 1, wherein the through slot is filled with a dielectric block, and wherein a dielectric loss (Df) of the dielectric block is less than or equal to 0.004.
4. A circuit board according to claim 3, wherein the material of the dielectric block comprises a fluororesin.
5. The circuit board according to claim 1, wherein openings at both ends of the through-slot are respectively covered with a cover film, and the cover film and the through-slot form a hollow structure.
6. The circuit board of any one of claims 1-5, wherein the first metal layer is further provided with a first shielding hole, one end of the first shielding hole is electrically connected to the first metal layer, and the other end of the first shielding hole extends to the third metal layer and is electrically connected to the third metal layer.
7. The circuit board of claim 1, wherein the fourth metal layer is further provided with a second shielding hole, one end of the second shielding hole is connected to the fourth metal layer, and the other end of the second shielding hole extends to and is connected to the third metal layer.
8. The circuit board of claim 1, wherein the circuit board is further provided with a metallized via extending through the circuit board in a thickness direction.
9. The circuit board of claim 1, further comprising a third dielectric layer between the second dielectric layer and the fourth metal layer, a fifth metal layer being disposed between the third dielectric layer and the second dielectric layer, the fifth metal layer being provided with a second opening through which the second dielectric layer communicates with the third dielectric layer.
10. An electronic device, comprising an antenna, a radio frequency chip and the circuit board according to any one of claims 1-9, wherein the antenna is disposed on a surface of a first metal layer of the circuit board, and the radio frequency chip is disposed on a surface of a fourth metal layer of the circuit board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202111433718.6A CN114340139B (en) | 2021-11-29 | 2021-11-29 | Circuit board and electronic equipment |
| PCT/CN2022/133305 WO2023093690A1 (en) | 2021-11-29 | 2022-11-21 | Circuit board and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111433718.6A CN114340139B (en) | 2021-11-29 | 2021-11-29 | Circuit board and electronic equipment |
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| CN114340139B true CN114340139B (en) | 2024-09-17 |
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| CN114340139B (en) * | 2021-11-29 | 2024-09-17 | 华为技术有限公司 | Circuit board and electronic equipment |
| CN117013248B (en) * | 2023-08-31 | 2024-11-22 | 西安电子科技大学 | Lightweight and low-cost transmitting antenna subarray structure |
| CN117651368B (en) * | 2023-12-08 | 2024-11-12 | 皆利士多层线路版(中山)有限公司 | I-shaped groove production of circuit board |
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| CN113054425A (en) * | 2021-03-17 | 2021-06-29 | 东南大学 | Millimeter wave dual-frequency dual-polarization filtering antenna |
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| US7636063B2 (en) * | 2005-12-02 | 2009-12-22 | Eswarappa Channabasappa | Compact broadband patch antenna |
| CN110300498A (en) * | 2019-06-26 | 2019-10-01 | Oppo广东移动通信有限公司 | Laminated structure of multilayer circuit board |
| CN110572965A (en) * | 2019-09-19 | 2019-12-13 | 深圳明阳电路科技股份有限公司 | HDI circuit board manufacturing process method |
| CN110690570B (en) * | 2019-10-18 | 2021-06-22 | Oppo广东移动通信有限公司 | Millimeter wave antennas and electronic equipment |
| CN110676578B (en) * | 2019-10-18 | 2021-07-09 | Oppo广东移动通信有限公司 | Millimeter wave antenna and electronic device |
| CN112867243A (en) * | 2021-01-06 | 2021-05-28 | 英韧科技(上海)有限公司 | Multilayer circuit board |
| CN114340139B (en) * | 2021-11-29 | 2024-09-17 | 华为技术有限公司 | Circuit board and electronic equipment |
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| CN113054425A (en) * | 2021-03-17 | 2021-06-29 | 东南大学 | Millimeter wave dual-frequency dual-polarization filtering antenna |
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| CN114340139A (en) | 2022-04-12 |
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