CN114337304A - Control chip and built-in MOS tube driving speed control method thereof - Google Patents

Abstract

The invention discloses a control chip and a built-in MOS tube driving speed control method thereof, wherein the control chip is provided with a programmable current input pin which is connected with the input voltage of a flyback converter through a resistor, and the current value input to the programmable current input pin is controlled by adjusting the resistance value of the resistor, and the current value is increased along with the increase of the input voltage of the flyback converter and is reduced along with the reduction of the input voltage; the control chip is internally provided with an MOS tube, and the on-off speed of the internally arranged MOS tube is controlled by controlling the current of the programmable current input pin; when the current of the programmable current input pin is increased, the turn-on and turn-off speed of the built-in power MOS is reduced, and when the current of the programmable current input pin is reduced, the turn-on and turn-off speed of the built-in power MOS is increased. The switching speed of the MOS tube of the invention is adaptive to the change of the input voltage of the flyback converter, and meets the required index under different input voltages.

Description

Control chip and its built-in MOS tube driving speed control method

technical field

The invention relates to the technical field of MOS tube driving circuits, in particular to a built-in MOS tube driving speed adaptive control chip and a flyback converter.

Background technique

In the decades of development of silicon semiconductor integrated circuit technology, especially the characteristic technology suitable for power chip design, the first-generation Biporlar process that originally only contained bipolar transistors has developed into an insulated gate MOS with a higher level of integration. The CMOS process of the tube was developed, and then the BCD process including bipolar devices, CMOS devices and DMOS devices was developed. With each advanced generation of semiconductor technology, the corresponding power chip integration and performance are closely followed by the advanced generation. For example, a few decades ago, TI (Texas Instruments) launched a series of first-generation classic power control chips such as UCC3843, UCC3842, UCC6840, etc. They are power control chips designed based on the mature Bipolar process. Due to the long history and easy-to-learn functions, part of the process design has been written into textbooks, making it a chip familiar to generations of power supply engineers. Even in today's mature development of various advanced semiconductor processes, these chips are also widely used. In various fields of power supply design. The second-generation CMOS process is characterized by high integration. Power chips based on this process naturally have more functions and lower power consumption, such as LM5020 and LM5021 from TI, and NCP12700 from NCP (ON Semiconductor). With the rapid development of the characteristic process of analog integrated circuit semiconductors in recent years, the third-generation BCD process has significant advantages compared with the previous two-generation processes. The most basic advantage is that circuit designers can simulate bipolar devices with high precision. Free choice between highly integrated CMOS devices and DMOS devices as power output stages. In particular, the resistivity of the LDMOS tube decreases significantly under the same withstand voltage, which makes the high-voltage power device, low-voltage signal processing circuit and peripheral interface, detection, protection and other functional circuits integrated into a single-chip integrated circuit technology. Intelligent power integrated circuits ( SPIC) has become a trend. LT (Linear Technology Corporation) launched the LT8302 series products earlier, and TI also launched the LM5181 series products in the last two years.

As shown in Figure 1, it is a simple schematic diagram of the first and second generation power control chips. It forms a flyback converter with peripheral flyback transformers, resistors, capacitors, etc. Its working principle is: _NP , N _S and N _A are the primary winding, secondary winding and auxiliary winding of the flyback transformer, respectively. When the power MOS transistor NM0 is turned on, the primary winding NP passes current, and the transformer is excited to store energy. At this time, the secondary winding and the auxiliary winding The windings are all turned off; when the MOS tube NM0 is turned off, the voltage of the primary winding is turned off in the reverse direction, and the secondary windings N _S and N _A are demagnetized, and the voltages of the N _A and N _S windings are proportional to their coil turns. The energy is mainly transferred to the output terminal V _OUT of the flyback converter through N _S . When the voltage of V _OUT is high, the negative input terminal of the differential amplifier EA is greater than the reference voltage V _ref , and its output voltage V _C decreases, so the current passing through the current sampling resistor R _CS decreases, and the stored value is stored when the flyback transformer is excited. The energy decreases, and the energy released to V _OUT during degaussing decreases accordingly, resulting in a decrease in the V _OUT voltage; conversely, when the V _OUT voltage is low, the negative input of the differential amplifier is less than the reference voltage V _ref , it The output voltage V _C increases, and under the control of this voltage, more energy is transferred to the output V _OUT through the flyback transformer to increase it. Repeating in this way, the target output voltage V _OUT can be continuously adjusted to reach a stable value. The output voltage V _C of the error amplifier EA is called the pulse width modulation voltage. The excitation current of the flyback transformer is compared with the V _C generated by the sampling resistor R _CS , which determines the pulse time width of the MOS transistor NM0 and the excitation current of the transformer. , so the size of the load of the flyback converter can be judged by the size of the modulation voltage V _C . As shown in Figure 2, the voltage of the secondary side V _OUT is induced by the auxiliary winding of the flyback transformer that shares the "ground" with the control chip. This feedback method is often referred to as primary side feedback (PSR). As the name implies, there is also a secondary side feedback SSR (Secondary Side Feedback), as shown in Figure 2, TL431, optocoupler and other resistors and capacitors form an isolated transconductance amplifier, which is generated by the pull-up resistor at the chip feedback pin FB. PWM voltage V _C , so it plays the same role as the differential amplifier EA in the PSR feedback mode, except that the voltage divider resistors R _FB1 and R _FB2 directly detect V _OUT in the secondary of the isolated flyback converter, hence the name secondary side feedback.

When the power tube is turned off, the flyback converter will generate a peak voltage due to the leakage inductance of the transformer. The faster the turn-off speed is, the greater the peak voltage will be. At the same time, it will cause excessive dv/dt and cause electromagnetic interference and EMI problems. The advantage is the turn-off loss. Small. Their common feature is that the drive circuit and MOS tube are built around the chip. In Figure 2, the drive resistor R _G1 is used to adjust the turn-on speed, the drive resistor R _G2 is used to adjust the turn-off speed, the resistor R _sn , the capacitor C _sn , and the diode D _sn It is composed of commonly used RCD absorption, which absorbs leakage inductance spikes to a certain extent, avoids exceeding the breakdown voltage of the MOS tube and improves EMI. Because the specification requirements of flyback converters, as well as the specifications and fabrication of transformers, are varied, it is difficult to satisfy all applications with one set of circuit parameters. Therefore, when designing a flyback converter, it is often necessary to compromise the performance of switching losses, leakage inductance spikes, and EMI by tuning the drive resistance and RCD absorption. The advantage of this external MOS tube solution is that engineers can adjust the drive speed and RCD absorption capacity according to the actual application. The disadvantage is that the turn-off speed of the flyback converter is the same at low input voltage and high input voltage. In fact, only at high input voltage can the peak voltage of the power MOS tube easily exceed its breakdown voltage. In order to reduce the high-voltage input The peak voltage of the low voltage input also slows down the switching speed, and the switching loss increases.

As shown in Figure 3, it is the third-generation power integrated power control chip. Its low-voltage signal processing circuit, peripheral interface, detection, protection and other functional circuits and high-voltage power MOS transistors are integrated on one wafer. The advantage is that the periphery is extremely simple, easy to PCB layout, and does not require additional series resistance (R _sense is generally the trace of the source of the built-in MOS tube, which exists by itself, not an additional series resistance) to sense the current of the power MOS tube. Improved sampling efficiency. The disadvantage is that the internal resistance of the built-in MOS tube is not as good as that of the external MOS tube. In order to obtain a small internal resistance as much as possible, the breakdown voltage of the built-in MOS tube will not leave too much margin, so it is particularly important to prevent the leakage inductance peak from being too large. Importantly, TVS tubes are often used to absorb leakage inductance spikes, and even combined with RC to fully absorb the high-frequency and low-frequency components of the spikes. It can be seen that although the third-generation single-chip power integrated power chip solution has new unique advantages, it still has the same shortcomings as the previous two-generation solutions in the drive circuit. In addition, because the power MOS tube is integrated inside the chip, engineers cannot It is not universally applicable to debug the switching speed according to the actual needs of the power converter.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a control chip and a method for controlling the driving speed of a built-in MOS tube, which can solve the problem that the non-adaptive flyback converter in the prior art can turn off the MOS tube at a high input voltage and a low input voltage respectively. It can also solve the problem that the R&D personnel in the prior art cannot debug the switching speed of the internal MOS tube according to the actual needs.

The purpose of this invention is to realize through the following technical solutions:

In a first aspect, the present invention provides a method for controlling the driving speed of a built-in MOS tube of a control chip, including the following steps: the control chip is provided with a programmable current input pin, and the programmable current input pin is connected to a flyback converter through a resistor The input voltage of the inverter is controlled by adjusting the resistance value of the resistor to control the current value input to the programmable current input pin. Small and reduced; the control chip has a built-in MOS tube, and the turn-on and turn-off speed of the built-in MOS tube is controlled by controlling the current of the programmable current input pin; when the current of the programmable current input pin increases, the built-in MOS tube is controlled. The turn-on and turn-off speed of the power MOS is slowed down. When the current of the programmable current input pin is reduced, the turn-on and turn-off speed of the built-in power MOS transistor is accelerated.

Further, the programmable current input pin is an independent pin set separately, or the same pin is multiplexed with other functional pins of the control chip.

Further, the built-in MOS tube refers to a single-chip integration method in which the MOS tube and the control circuit of the control chip are integrated on the same wafer, or the separate MOS tube die and the control circuit die are sealed together. Multi-chip packaging.

In the second aspect, the present invention provides a control chip for implementing the above-mentioned method for controlling the driving speed of a built-in MOS transistor. The first solution includes a differential amplifier, a comparator, a proportional amplifier, a MOS transistor NM0, a current sampling resistor, and a frequency control. The circuit and the RS flip-flop also include a programmable drive current generating circuit and a controllable drive circuit; the negative input terminal of the differential amplifier is connected to the output voltage feedback pin of the control chip, and the positive input terminal of the differential amplifier inputs the reference voltage V _ref , the output end of the differential amplifier is connected to the positive input end of the comparator and the input end of the frequency control circuit; the output end of the frequency control circuit is connected to an input end of the RS flip-flop, and the comparison The output end of the controller is connected to the other input end of the RS flip-flop; the output end of the RS flip-flop is connected to the second input port of the controllable drive circuit; the drain of the MOS transistor NM0 is connected to the MOS of the control chip tube drain pin, the source of the MOS tube NM0 is connected to the positive input of the proportional amplifier, the gate of the MOS tube NM0 is connected to the fourth port of the controllable drive circuit; the negative of the proportional amplifier the input terminal is grounded; the current sampling resistor is connected between the positive input terminal and the negative input terminal of the proportional amplifier; the output terminal of the proportional amplifier is connected to the negative input terminal of the comparator; the programmable drive current generates The first port of the circuit is connected to the programmable current input pin of the control chip, the third port of the programmable drive current generation circuit is connected to the first port of the controllable drive circuit, and the third port of the programmable drive current generation circuit is connected. The four ports are connected to the sixth port of the controllable drive circuit; the fifth port of the programmable drive current generation circuit and the fifth port of the controllable drive circuit are connected to the supply voltage, and the programmable drive current generation circuit The second port and the third port of the controllable drive circuit are grounded.

The second scheme of the control chip, on the basis of the first scheme, also includes a hysteresis comparator and a MOS tube PM0; the source of the MOS tube PM0 is connected to the programmable current input pin, the hysteresis comparator The negative input port of the MOS transistor PMO is connected to the high positive input port of the hysteresis comparator and the reference voltage V _H ; the drain of the MOS transistor PM0 is connected to the programmable drive current generating circuit. The first port is connected; the low positive input port of the hysteresis comparator is connected with the reference voltage _VL .

Further, the programmable drive current generating circuit includes a MOS transistor NM1, a MOS transistor NM2, a MOS transistor NM3, a MOS transistor NM4, a MOS transistor NM5, a MOS transistor PM1, a MOS transistor PM2 and a resistor R1; the drain of the MOS transistor NM1. The electrode and the gate, the gate of the MOS transistor NM2 are connected to the first port of the programmable drive current generating circuit; the drain of the MOS transistor NM2 is respectively connected with the drain and the gate of the MOS transistor NM3, the The gate of the MOS transistor NM4, the gate of the NM5, and the second port of the resistor R1 are connected; the drain and gate of the MOS transistor PM1 are connected to the drain of the MOS transistor NM4, the MOS transistor The gate of PM2 is connected; the first port of the resistor R1 is connected to the source of the MOS transistor PM1, the source of the MOS transistor PM2, and the fifth port of the programmable drive current generating circuit; the MOS The source of the transistor NM1, the source of the MOS transistor NM2, the source of the MOS transistor NM3, the source of the MOS transistor NM4, the source of the MOS transistor NM5 and the programmable drive current generating circuit The drain of the MOS transistor PM2 is connected to the fourth port of the programmable drive current generating circuit; the drain of the MOS transistor NM5 is connected to the third port of the programmable drive current generating circuit connect.

Further, the controllable driving circuit includes MOS transistor NM11, MOS transistor NM12, MOS transistor NM13, MOS transistor NM14, MOS transistor NM15, MOS transistor PM11, MOS transistor PM12, MOS transistor PM13, MOS transistor PM14, MOS transistor PM15, Resistor R2 and resistor R3; the gate of the MOS transistor NM11 and the gate of the MOS transistor PM11 are connected to the second port of the controllable drive circuit; the drain of the MOS transistor NM11 is respectively connected to the MOS transistor The drain of PM11, the gate of the MOS transistor NM12, and the gate of the MOS transistor PM12 are connected; the drain of the MOS transistor NM12 is respectively connected to the drain of the MOS transistor PM12 and the gate of the MOS transistor NM13 the gate of the MOS transistor PM13; the drain of the MOS transistor NM13 is connected to the drain of the MOS transistor PM13, the gate of the MOS transistor NM14, the gate of the MOS transistor PM14, the The gate of the MOS transistor NM15 and the gate of the MOS transistor PM15 are connected; the drain of the MOS transistor PM14 is connected to the first port of the resistor R3; the drain of the MOS transistor NM14 is connected to the resistor R2 The second port of the resistor R3, the first port of the resistor R2, the drain of the MOS transistor NM15, and the drain of the MOS transistor PM15 are respectively connected with the controllable drive circuit. the fourth port is connected; the source of the MOS transistor NM15 is connected to the first port of the controllable drive circuit; the source of the MOS transistor PM15 is connected to the sixth port of the controllable drive circuit; the MOS The source of the tube NM11, the source of the MOS tube NM12, the source of the MOS tube NM13, and the source of the MOS tube NM14 are respectively connected to the third port of the controllable drive circuit; the MOS tube The source of the PM11, the source of the MOS transistor PM12, the source of the MOS transistor PM13, and the source of the MOS transistor PM14 are respectively connected to the fifth port of the controllable driving circuit.

Further, the reference voltage V _H is greater than the reference voltage _VL .

In a third aspect, the present invention provides a flyback converter, including the control chip of the first solution.

Further, the described flyback converter further includes a capacitor C _IN , a resistor R _in , a clamping absorbing circuit, a transformer, a diode D _OUT , a capacitor C _OUT , a resistor R _FB1 and a resistor R _FB2 , the capacitor C _IN One end is connected to the input voltage V _IN of the flyback converter, and the other end is grounded; one end of the resistor R _in and the opposite end of the primary winding of the transformer are connected to the input voltage V _IN , and the other end of the resistor R _in is connected to the input voltage V IN . One end is connected to the programmable current input pin of the control chip; the same-named end of the primary winding of the transformer is connected to the drain pin of the MOS tube of the control chip; the clamping absorption circuit is connected to the same-named end of the primary winding of the transformer and the different name terminal; the same name terminal of the auxiliary winding of the transformer is connected to one end of the resistor R _FB2 , and the other end of the resistor R _FB2 and one end of the resistor R _FB1 are connected to the output voltage feedback pin of the control chip; The other end of the resistor R _FB1 is grounded; the same name end of the transformer secondary winding is connected to the anode of the diode D _OUT , the cathode of the diode D _OUT outputs the voltage V _OUT +, the synonym of the transformer secondary winding The terminal outputs a voltage V _OUT -, and the capacitor C _OUT is connected between the cathode of the diode D _OUT and the opposite end of the secondary winding of the transformer.

In a fourth aspect, the present invention provides a flyback converter, including the control chip of the second solution above.

Further, the described flyback converter further includes a capacitor C _IN , a resistor R _in , a clamping absorbing circuit, a transformer, a diode D _OUT , a capacitor C _OUT , a resistor R _FB1 , a resistor R _FB2 and a resistor R _UNP , so One end of the capacitor C _IN is connected to the input voltage V _IN of the flyback converter, and the other end is grounded; one end of the resistor R _in and the opposite end of the primary winding of the transformer are connected to the input voltage V _IN , and the resistor R in is connected to the input voltage V IN . The other end of R _in and the first port of the resistor R _UVP are connected to the programmable current input pin of the control chip; the second port of the resistor R _UVP is grounded; the same-named end of the primary winding of the transformer is connected to the control chip The drain pin of the MOS tube; the clamping absorption circuit is connected between the same-named terminal and the different-named terminal of the primary winding of the transformer; the same-named terminal of the auxiliary winding of the transformer is connected to one end of the resistor R _FB2 , so the The other end of the resistor R _FB2 and one end of the resistor R _FB1 are connected to the output voltage feedback pin of the control chip; the other end of the resistor R _FB1 is grounded; the same-named end of the secondary winding of the transformer is connected to the diode D _OUT the positive pole of the diode D _OUT , the negative pole of the diode D OUT outputs the voltage V _OUT +, the opposite end of the transformer secondary winding outputs the voltage V _OUT -, the capacitor C _OUT is connected to the negative pole of the diode D _OUT and the transformer between the synonym ends of the secondary winding.

The built-in MOS transistor driving speed adaptive control chip and the flyback converter of the present invention suppress the peak voltage generated by the transformer in the flyback converter at the drain of the MOS transistor and the voltage stress of the output diode when the high voltage is input, and reduce the voltage stress of the output diode. The risk of being damaged does not affect or even improve the overall efficiency of the flyback converter. Reduce switching loss at low voltage input and increase overall machine efficiency. The switching speed of the MOS tube is adaptive to the change of the input voltage and meets the required indicators under different input voltages. R&D personnel can adjust the resistance outside the control chip, and design the switching speed of the power tube according to the requirements, which has universal applicability.

Description of drawings

Fig. 1 is the control chip of the first generation and the second generation external MOS tube of the prior art and its PSR feedback application diagram;

Fig. 2 is the control chip of the first generation and the second generation external MOS tube of the prior art and its SSR feedback application diagram;

Fig. 3 is the control chip and PSR feedback application diagram of the third generation built-in MOS transistor in the prior art;

FIG. 4 is an application diagram of the built-in MOS tube control chip and its PSR feedback proposed by the present invention;

FIG. 5 is a specific implementation circuit diagram of the programmable drive current generating circuit proposed by the present invention;

FIG. 6 is a specific implementation circuit diagram of the controllable drive circuit proposed by the present invention;

FIG. 7 is an application diagram of a control chip with functional pin multiplexing proposed by the present invention and its PSR feedback.

Detailed ways

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only some, but not all, embodiments of the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other under the condition of no conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

Example 1

The built-in MOS tube driving speed control method of the control chip of the present invention includes the following steps: the control chip is provided with a programmable current input pin, the programmable current input pin is connected to the input voltage of the flyback converter through a resistor, Adjust the resistance value of the resistor to control the current value input to the programmable current input pin. The current value of the programmable current input pin increases with the increase of the input voltage of the flyback converter, and decreases with the decrease of the input voltage. Small and reduced; the control chip has a built-in MOS tube, and the turn-on and turn-off speed of the built-in MOS tube is controlled by controlling the current of the programmable current input pin; when the current of the programmable current input pin increases, the built-in MOS tube is controlled. The turn-on and turn-off speed of the power MOS is slowed down. When the current of the programmable current input pin is reduced, the turn-on and turn-off speed of the built-in power MOS transistor is accelerated.

The programmable current input pin is an independent pin set separately, or multiplexed with other pins of the control chip.

The built-in MOS tube refers to the single-chip integration method in which the MOS tube and the control circuit of the control chip are integrated on the same wafer, or refers to the multi-chip package in which the separated MOS tube die and the control circuit die are sealed together. Way.

In order to better illustrate the method for controlling the driving speed of the built-in MOS transistor of the present invention, this embodiment provides a control chip. It should be noted that the control chip for realizing the built-in MOS tube driving speed control method of the present invention is not limited to the circuit structure indicated in this embodiment. Modifications that can achieve the purpose of the present invention all fall within the protection scope of the present invention.

A control chip with built-in MOS tube driving speed adaptation, as shown in Figure 4, includes basic functional modules forming a voltage-stabilized power supply control chip: differential amplifier EA, comparator, proportional amplifier, power MOS tube NM0, current sampling The resistor R _sense , the frequency control circuit and the RS flip-flop also include the programmable driving current generating circuit 100 and the controllable driving circuit 200 unique to the present invention. The programmable drive current generation circuit 100 at least includes a first port 101, a second port 102, a third port 103, a fourth port 104, and a fifth port 105. The second port 102 and the fifth port 105 are respectively used for programmable drive current generation. The power input of the circuit is negative and the power input is positive. The controllable driving circuit 200 includes at least a first port 201, a second port 202, a third port 203, a fourth port 204, a fifth port 205 and a sixth port 206, and the third port 203 and the fifth port 205 are respectively controllable The power input of the drive circuit is negative and the power input is positive. The control chip at least includes an output voltage feedback pin FB, a programmable current input pin RIN and a MOS transistor drain pin DRN. The negative input terminal of the differential amplifier EA is connected to the output voltage feedback pin FB, the positive input terminal of the differential amplifier EA inputs the reference voltage V _ref , and the output terminal of the differential amplifier EA is connected to the positive input terminal of the comparator and the input terminal of the frequency control circuit. The output end of the frequency control circuit is connected to one input end of the RS flip-flop, and the output end of the comparator is connected to the other input end of the RS flip-flop. The output end of the RS flip-flop is connected to the second input port 202 of the controllable driving circuit. The drain of the MOS transistor NM0 is connected to the drain pin DRN of the MOS transistor, the source is connected to the positive input terminal of the proportional amplifier, and the gate is connected to the fourth port 204 of the controllable driving circuit. The negative input of the proportional amplifier is grounded. The current sampling resistor R _sense is connected between the positive input terminal and the negative input terminal of the proportional amplifier. The output of the proportional amplifier is connected to the negative input of the comparator. The first port 101 of the programmable drive current generation circuit is connected to the programmable current input pin RIN, the third port 103 of the programmable drive current generation circuit is connected to the first port 201 of the controllable drive circuit, and the third port of the programmable drive current generation circuit is connected to the first port 201 of the programmable drive current generation circuit. The four port 104 is connected to the sixth port 206 of the controllable drive circuit. The fifth port 105 of the programmable driving current generating circuit and the fifth port 205 of the controllable driving circuit are connected to the supply voltage VCC, and the second port 102 of the programmable driving current generating circuit and the third port 203 of the controllable driving circuit are grounded.

The working principle of the control chip shown in Figure 4 is as follows: the negative input terminal of the differential amplifier EA receives a signal that can reflect the output voltage V _OUT of the flyback converter through the output voltage feedback pin FB, and differentiates from the reference voltage V _ref at its positive input terminal. Amplified to generate a pulse width modulated voltage V _C . The pulse width modulation voltage V _c is used as the input signal of the frequency control circuit to adjust the operating frequency according to the load condition of the flyback converter. The pulse width modulation voltage V _c is also used as the positive input signal of the comparator, which is connected with the proportional amplifier from the current sampling resistor R _sense . The sampled voltage signals are compared to generate the NMO turn-off sequence. The RS flip-flop receives the turn-on sequence provided by the frequency control circuit and the NMO turn-off sequence generated by the comparator, and generates the NMO switch sequence under their combined action, and provides it to the controllable drive circuit. The current detection port 101 (ie the first port 101 ) of the programmable drive current generation circuit 100 senses a programmable input current proportional to the input voltage V _IN of the flyback converter from the programmable current input pin RIN of the control chip, and Programmable turn-on drive current and programmable turn-off drive current are output at port 104 and port 103, respectively. Both currents decrease with the increase of programmable input current. Port 105 and port 102 are power input positive and power input, respectively. burden. The port 201 and port 206 of the controllable drive circuit 200 respectively receive the programmable turn-off drive current and the programmable turn-on drive current from the programmable drive current generating circuit 100, and the port 202 receives the NM0 switching timing output from the RS flip-flop, and according to the In this sequence, the MOS transistor NM0 is turned on and off at the output port 204 .

FIG. 4 is a circuit diagram of a flyback converter including a control chip of this embodiment. In addition to the control chip of this embodiment, it also includes a capacitor C _IN , a resistor R _in , a clamp absorption circuit, a transformer, a diode D _OUT , and a capacitor C _OUT , resistor R _FB1 and resistor R _FB2 , capacitor C _IN is an input filter capacitor, one end of which is connected to the input voltage V _IN of the flyback converter, and the other end is grounded. One end of the resistor R _in and the other end of the transformer primary winding _NP are connected to the input voltage V _IN of the flyback converter, and the other end of the resistor R _in is connected to the programmable current input pin RIN of the control chip. The same-named end of the primary winding _NP of the transformer is connected to the drain pin DRN of the MOS transistor of the control chip. The clamping absorption circuit is connected between the same-named terminal and the different-named terminal of the primary winding _NP of the transformer. _The same-named end of the transformer auxiliary winding NA is connected to one end of the resistor R _FB2 , and the other end of the resistor R _FB2 and one end of the resistor R _FB1 are connected to the output voltage feedback pin FB of the control chip. The other end of resistor R _FB1 is connected to ground. The same name terminal of the transformer secondary winding is connected to the anode of the diode D _OUT , the negative terminal of the diode D _OUT outputs the voltage V _OUT +, the opposite terminal of the transformer secondary winding outputs the voltage V _OUT -, and the capacitor C _OUT is connected to the cathode of the diode D _OUT and Between the synonym ends of the secondary winding of the transformer.

The pin RIN is connected to the input voltage V _IN of the flyback converter through the resistor R _in . With the increase of the input voltage V _IN , the programmable input current through the resistor R _in increases, and the programmable turn-on drive generated by the port 104 and the port 103 respectively The current and the programmable turn-off drive current are reduced, so the turn-on and turn-off speed of the MOS transistor NM0 becomes slower. When the flyback converter is at high voltage input, due to the slowing down of the switching speed of NM0, the voltage spike generated by the flyback transformer at the drain of NM0 and the voltage of the output diode D _OUT are suppressed, and the damage of the MOS transistor NM0 and the output diode D _OUT is reduced. Risk, although the reduction of switching speed increases the switching losses, but due to the high input voltage and low current of the flyback converter, the conduction loss becomes smaller, the overall efficiency does not necessarily decrease, on the contrary, due to the output diode D _OUT The voltage stress is suppressed, and a diode with a lower withstand voltage can be selected, which has a lower internal resistance and improves the overall efficiency of the converter; when the flyback converter is input at a low voltage, due to the increase in the switching speed of NM0, the reduction is reduced. It reduces the switching loss and improves the energy transfer efficiency of the flyback converter. Although the increase in switching speed will increase the voltage spike generated by the flyback transformer at the NMO drain and the voltage of the output diode D _OUT , the input voltage of the flyback converter is low at this time. , so it is not easy to damage the power tube NMO and the output diode D _OUT . By changing the size of the off-chip resistor R _in , under the same V _IN input voltage, different programmable turn-on drive currents and programmable turn-off drive currents are generated, so that NM0 has different switching speeds.

It can be seen from the above principles that the beneficial effects of the power control chip provided by the present invention are as follows: 1. When the flyback converter is input with high voltage, it suppresses the peak voltage generated by the transformer at the drain of the power tube and the voltage stress of the output diode, and reduces the voltage stress of the output diode. The risk of being damaged does not affect or even improve the overall efficiency of the converter; when the low-voltage input is used, the switching loss is reduced and the overall efficiency is increased. That is, the switching speed of the power tube is adaptive to the change of the input voltage, and meets the required index under different input voltages. 2. Engineers can adjust the resistance outside the chip and design the switching speed of the power tube according to the requirements, which has universal applicability.

Further, the specific implementation circuit of the programmable drive current generating circuit 100 in this embodiment is shown in FIG. 5 , including: N-channel MOS transistor NM1 , N-channel MOS transistor NM2 , N-channel MOS transistor NM3 , N Type channel MOS transistor NM4, N type channel MOS transistor NM5, P type channel MOS transistor PM1, P type channel MOS transistor PM2 and resistor R1. The drain and gate of the MOS transistor NM1 and the gate of the MOS transistor NM2 are connected to the first port 101 of the programmable drive current generating circuit; the drain of the MOS transistor NM2 is respectively connected with the drain and the gate of the MOS transistor NM3 and the MOS transistor NM4 The gate of NM5, the gate of NM5, and the second port of resistor R1 are connected. The drain and gate of the MOS transistor PM1 are connected to the drain of the MOS transistor NM4 and the gate of the MOS transistor PM2. The first port of the resistor R1 is connected to the source of the MOS transistor PM1, the source of the MOS transistor PM2, and the fifth port 105 of the programmable drive current generating circuit. The source of MOS transistor NM1, the source of MOS transistor NM2, the source of MOS transistor NM3, the source of MOS transistor NM4, and the source of MOS transistor NM5 are connected to the second port 102 of the programmable driving current generating circuit. The drain of the MOS transistor PM2 is connected to the fourth port 104 of the programmable drive current generating circuit; the drain of the MOS transistor NM5 is connected to the third port 103 of the programmable drive current generating circuit.

For the convenience of calculation, the width-length ratio of the MOS transistor NM1 and the MOS transistor NM2 is set as NM1:NM2=1:1, NM3:NM4:NM5=1:1:m, PM1:PM2=1:n. In order to save power consumption, the programmable current through the resistor R _in is uA level, generally in the range of ten to more than one hundred microamps, while the programmable turn-on drive current and programmable turn-off drive current provided by port 104 and port 103 are several The ten mA level, so the scale factors m and n are hundreds to thousands of times.

It is easy to calculate:

时 (1)I _NM5 = I _PM2 = 0, when

hour(1)

当V_IN<V_IN0时 (2)

When V _IN < V _IN0 (2)

当V_IN<V_IN0时 (3)

When V _IN < V _IN0 (3)

Among them, V _THN is the threshold voltage of the N-channel MOS transistor, which is generally about 0.7V, depending on the semiconductor process used. V _GS1 and V _GS3 are the gate-source voltages of NM1 and NM3 respectively, and their aspect ratios are properly designed in the integrated circuit design, and the gate-source voltage can be maintained at 0.7V to 1.3V. It can be seen from the above formula that when V _IN ≥ V _IN0 , the current provided by the programmable drive current generating circuit is zero, then the power tube operates at the minimum switching speed; when V _IN <V _IN0 , with the input voltage V With the increase of _IN , the programmable turn-on drive current I _PM2 and the programmable turn-off drive current I _NM5 provided by the programmable drive current generation circuit gradually decrease, so the switching speed of the power transistor also decreases gradually, realizing the first embodiment of the present invention. Program the function of the drive current generation circuit.

Further, the specific implementation circuit of the controllable driving circuit 200 in this embodiment is shown in FIG. 6 , including an N-channel MOS transistor NM11 , an N-channel MOS transistor NM12 , an N-channel MOS transistor NM13 , an N-channel MOS transistor NM13 , and an N-channel MOS transistor NM12 . MOS tube NM14, N-channel MOS tube NM15, P-channel MOS tube PM11, P-channel MOS tube PM12, P-channel MOS tube PM13, P-channel MOS tube PM14, P-channel MOS tube PM15, drive resistor R2 and drive resistor R3. The gate of the MOS transistor NM11 and the gate of the MOS transistor PM11 are connected to the second port 202 of the controllable driving circuit. The drain of the MOS transistor NM11 is connected to the drain of the MOS transistor PM11, the gate of the MOS transistor NM12, and the gate of the MOS transistor PM12, respectively. The drain of the MOS transistor NM12 is connected to the drain of the MOS transistor PM12, the gate of the MOS transistor NM13, and the gate of the MOS transistor PM13, respectively. The drain of the MOS transistor NM13 is connected to the drain of the MOS transistor PM13, the gate of the MOS transistor NM14, the gate of the MOS transistor PM14, the gate of the MOS transistor NM15, and the gate of the MOS transistor PM15, respectively. The drain of the MOS transistor PM14 is connected to the first port of the driving resistor R3. The drain of the MOS transistor NM14 is connected to the second port of the driving resistor R2. The second port of the driving resistor R3, the first port of the driving resistor R2, the drain of the MOS transistor NM15, and the drain of the MOS transistor PM15 are respectively connected to the fourth port 204 of the controllable driving circuit. The source of the MOS transistor NM15 is connected to the first port 201 of the controllable drive circuit; the source of the MOS transistor PM15 is connected to the sixth port 206 of the controllable drive circuit; the source of the MOS transistor NM11, the source of the MOS transistor NM12, The source of the MOS transistor NM13 and the source of the MOS transistor NM14 are respectively connected to the third port 203 of the controllable drive circuit; the source of the MOS transistor PM11, the source of the MOS transistor PM12, the source of the MOS transistor PM13, and the MOS transistor PM14 The sources of , respectively, are connected to the fifth ports 205 of the controllable driving circuit.

The working principle of the controllable drive circuit is: MOS tube NM11 and MOS tube PM12 form the first-level NOT gate, MOS tube NM12 and MOS tube PM12 form the second-level NOT gate, and MOS tube NM13 and MOS tube PM13 form the third-level NOT gate. , the driving ability of these three-level NOT gates is amplified step by step, the purpose is to gradually amplify the driving ability of the timing signal with weak driving ability received by the port 202, so as to quickly drive the larger MOS transistors NM14, MOS transistors NM15, MOS Tube PM14, MOS tube PM15, which are commonly used driving methods in CMOS technology. When the signal of port 202 changes from low level to high level, the gates of MOS transistor NM14, MOS transistor NM15, MOS transistor PM14 and MOS transistor PM15 change from high level to low level, MOS transistor NM14 and MOS transistor NM15 change. In the off state, the MOS transistor PM14 and the MOS transistor PM15 become on-state, then the output current from the port 204 is the sum of the current of the driving resistor R3 and the current received by the port 206; otherwise, the signal of the port 202 changes from high level to low level When the level is high, the gates of the MOS transistor NM14, MOS transistor NM15, MOS transistor PM14 and MOS transistor PM15 change from low level to high level, MOS transistor NM14 and MOS transistor NM15 become conductive, MOS transistor PM14 and MOS transistor The PM15 is turned off, and the current drawn from the port 204 is the sum of the current of the drive resistor R2 and the current received by the port 201 . The currents received by the port 206 and the port 201 are generated by the above-mentioned variable driving current generating circuit to change the switching speed of the MOS transistor NM0. The principle has been described in detail above and will not be repeated here. The drive resistors R2 and R3 provide the minimum drive current and ensure that the power tube is normally turned on and off when the variable drive current is zero.

Embodiment 2

The control chip of the present invention changes the driving speed by detecting the input voltage of the flyback converter and generating a driving current that changes with the input voltage. There are other functions in the flyback converter that also need to detect the input voltage, such as input under-voltage protection, input Overvoltage protection, feedforward compensation functions, etc., the drive speed adaptive function of the present invention can also multiplex the same pin with the above functions, thereby reducing chip pins and peripheral devices.

As shown in FIG. 7 , it is the pin multiplexing scheme of the built-in power MOS transistor driving speed adaptive function and the input under-voltage protection function proposed in the second embodiment. On the basis of the first embodiment, compared with FIG. 4 , a hysteresis comparator 300 and a P-channel MOS transistor PM0 are added. The source of the MOS transistor PM0 is connected to the programmable current input pin RIN of the control chip and the negative input port of the hysteresis comparator, and the gate of the MOS transistor PM0 is connected to the high positive input port of the hysteresis comparator 300 and the reference voltage _VH ; The drain of the MOS transistor PM0 is connected to the first port 101 of the programmable drive current generating circuit 100; the low positive input port of the hysteresis comparator 300 is connected to the reference voltage _VL . The reference voltage V _H is greater than the reference voltage _VL . Other connection relationships are the same as those in the first embodiment, and are not repeated here.

The input voltage V _IN of the flyback converter is divided by the peripheral resistor R _in and the resistor R _UVP of the control chip and then connected to the RIN pin of the chip. The sampling voltage V _RIN at the pin is:

When V _RIN is greater than the reference voltage V _H , the comparator output UVP_L is high level, indicating that the input voltage V _IN of the flyback converter is not under-voltage, when V _RIN is less than the reference voltage V _L , the comparator output UVP_L is low level , indicating that the input voltage V _IN is under-voltage, and it is forbidden to turn on the MOS tube NM0. This is a commonly used input undervoltage protection function.

In order to keep the input under-voltage protection function unaffected, in the range where V _RIN is less than the reference V _H , V _RIN should keep the above formula unchanged, then the first port 101 of the programmable driving current generating circuit 100 cannot sink current. However, in order to achieve the purpose of changing the switching speed of the power MOS transistor NM0 by changing the size of the resistor R _in proposed by the present invention, a programmable input current needs to be induced when V _RIN is greater than the reference voltage V _H . The role of PMO is to satisfy these two requirements at the same time:

1. When the RIN pin voltage V _RIN < V _H +V _THP (V _THP is the absolute value of the threshold voltage of the PMO), the P-channel MOS transistor PM0 is off, so it will not affect the input undervoltage protection function ;

2. PM0 will be turned on only when V _RIN ≥V _H +V _THP , and it can be calculated that the programmable current entering the programmable drive current generating circuit 100 after passing through PM0 is:

where V _SG0 is the voltage difference between the source and gate of the PMO. Combining formulas (4) and (5), it can be seen that the voltage _at which V _IN enters under-voltage protection can be set by designing the proportional coefficient of the resistance R _in and R _UVP ; The size of the programming current can be set so that the switching speed of the power MOS transistor NM0 can be set. The input under-voltage protection function and the built-in MOS transistor drive speed programmable and adaptive functions are realized at the same time through only one chip pin, and the parameters of the two functions can be designed by engineers according to their needs.

This embodiment provides a flyback converter, as shown in FIG. 7 , including the built-in MOS transistor driving speed adaptive control chip of the second embodiment. The difference between this embodiment and the flyback converter of the first embodiment is: A resistor R _UNP is added to the peripheral circuit of the control chip, the first port of the resistor R _UVP is connected to the programmable current input pin RIN of the control chip, and the second port of the resistor R _UVP is grounded.

The input voltage V _IN of the flyback converter is divided by the peripheral resistor R _in and the resistor R _UVP of the control chip and then connected to the RIN pin of the chip. The remaining connection relationships and working principles are the same as those in the first embodiment, and are not repeated here.

The above is only to illustrate the embodiments of the present invention, and not to limit the present invention. For those skilled in the art, all within the spirit and principle of the present invention, without any modification, equivalent replacement or improvement made by creative work etc., should be included within the protection scope of the present invention.

Claims (10)

1. The method for controlling the driving speed of the built-in MOS tube of the control chip is characterized by comprising the following steps of: the control chip is provided with a programmable current input pin, the programmable current input pin is connected with the input voltage of the flyback converter through a resistor, the value of a current input to the programmable current input pin is controlled by adjusting the resistance value of the resistor, the value of the current increases along with the increase of the input voltage of the flyback converter and decreases along with the decrease of the input voltage; the control chip is internally provided with an MOS tube, and the on-off speed of the internally arranged MOS tube is controlled by controlling the current of the programmable current input pin; when the current of the programmable current input pin is increased, the turn-on and turn-off speed of the built-in power MOS is reduced, and when the current of the programmable current input pin is reduced, the turn-on and turn-off speed of the built-in power MOS is increased.

2. The method of claim 1, wherein the programmable current input pin is a separate pin provided separately or is multiplexed with other functional pins of the control chip.

3. The method as claimed in claim 1, wherein the built-in MOS transistor is a single chip integrated type in which a MOS transistor and a control circuit of the control chip are integrated on a same wafer, or a multi-chip package type in which a separate MOS transistor die and a separate control circuit die are packaged together.

4. A control chip, for implementing the built-in MOS transistor driving speed control method of any one of claims 1 to 3, comprising a differential amplifier, a comparator, a proportional amplifier, a MOS transistor NM0, a current sampling resistor, a frequency control circuit, and an RS flip-flop, and further comprising a programmable driving current generation circuit and a controllable driving circuit; the negative input end of the differential amplifier is connected with an output voltage feedback pin of the control chip, and the positive input end of the differential amplifier inputs a reference voltage V_refThe output end of the differential amplifier is connected with the positive input end of the comparator and the frequency control circuitAn input terminal of (1); the output end of the frequency control circuit is connected with one input end of the RS trigger, and the output end of the comparator is connected with the other input end of the RS trigger; the output end of the RS trigger is connected with a second input port of the controllable driving circuit; the drain of the MOS transistor NM0 is connected to a drain pin of a MOS transistor of a control chip, the source of the MOS transistor NM0 is connected to the positive input terminal of the proportional amplifier, and the gate of the MOS transistor NM0 is connected to the fourth port of the controllable driving circuit; the negative input end of the proportional amplifier is grounded; the current sampling resistor is connected between the positive input end and the negative input end of the proportional amplifier; the output end of the proportional amplifier is connected with the negative input end of the comparator; the first port of the programmable driving current generating circuit is connected with a programmable current input pin of a control chip, the third port of the programmable driving current generating circuit is connected with the first port of the controllable driving circuit, and the fourth port of the programmable driving current generating circuit is connected with the sixth port of the controllable driving circuit; and a fifth port of the programmable driving current generation circuit and a fifth port of the controllable driving circuit are connected with a power supply voltage, and a second port of the programmable driving current generation circuit and a third port of the controllable driving circuit are grounded.

5. The control chip of claim 4, further comprising a hysteresis comparator and a MOS transistor PM 0; the source of the MOS transistor PM0 is connected with the programmable current input pin and the negative input port of the hysteresis comparator, and the gate of the MOS transistor PM0 is connected with the high positive input port of the hysteresis comparator and a reference voltage V_HConnecting; the drain electrode of the MOS transistor PM0 is connected with the first port of the programmable drive current generating circuit; the low-order positive input port of the hysteresis comparator is connected with a reference voltage V_LAnd (4) connecting.

6. The control chip according to claim 4 or 5, wherein the programmable driving current generating circuit comprises a MOS transistor NM1, a MOS transistor NM2, a MOS transistor NM3, a MOS transistor NM4, a MOS transistor NM5, a MOS transistor PM1, a MOS transistor PM2 and a resistor R1; the drain and the gate of the MOS transistor NM1 and the gate of the MOS transistor NM2 are connected with the first port of the programmable drive current generation circuit; the drain of the MOS transistor NM2 is connected to the drain and the gate of the MOS transistor NM3, the gate of the MOS transistor NM4, the gate of the NM5, and the second port of the resistor R1, respectively; the drain and the gate of the MOS transistor PM1 are connected with the drain of the MOS transistor NM4 and the gate of the MOS transistor PM 2; a first port of the resistor R1 is connected with a source electrode of the MOS transistor PM1, a source electrode of the MOS transistor PM2 and a fifth port of the programmable drive current generation circuit; the source electrode of the MOS transistor NM1, the source electrode of the MOS transistor NM2, the source electrode of the MOS transistor NM3, the source electrode of the MOS transistor NM4, and the source electrode of the MOS transistor NM5 are connected to the second port of the programmable driving current generation circuit; the drain electrode of the MOS transistor PM2 is connected with the fourth port of the programmable drive current generating circuit; the drain of the MOS transistor NM5 is connected to the third port of the programmable driving current generating circuit.

7. The control chip according to claim 4 or 5, wherein the controllable driving circuit comprises a MOS transistor NM11, a MOS transistor NM12, a MOS transistor NM13, a MOS transistor NM14, a MOS transistor NM15, a MOS transistor PM11, a MOS transistor PM12, a MOS transistor PM13, a MOS transistor PM14, a MOS transistor PM15, a resistor R2 and a resistor R3; the grid electrode of the MOS transistor NM11 and the grid electrode of the MOS transistor PM11 are connected with the second port of the controllable driving circuit; the drain of the MOS transistor NM11 is connected to the drain of the MOS transistor PM11, the gate of the MOS transistor NM12 and the gate of the MOS transistor PM12 respectively; the drain of the MOS transistor NM12 is connected to the drain of the MOS transistor PM12, the gate of the MOS transistor NM13 and the gate of the MOS transistor PM13 respectively; the drain of the MOS transistor NM13 is connected to the drain of the MOS transistor PM13, the gate of the MOS transistor NM14, the gate of the MOS transistor PM14, the gate of the MOS transistor NM15, and the gate of the MOS transistor PM 15; the drain electrode of the MOS transistor PM14 is connected with the first port of the resistor R3; the drain electrode of the MOS transistor NM14 is connected with the second port of the resistor R2; the second port of the resistor R3, the first port of the resistor R2, the drain of the MOS transistor NM15, and the drain of the MOS transistor PM15 are respectively connected to the fourth port of the controllable driving circuit; the source electrode of the MOS transistor NM15 is connected with the first port of the controllable driving circuit; the source electrode of the MOS transistor PM15 is connected with the sixth port of the controllable driving circuit; the source of the MOS transistor NM11, the source of the MOS transistor NM12, the source of the MOS transistor NM13, and the source of the MOS transistor NM14 are respectively connected to the third port of the controllable driving circuit; the source electrode of the MOS transistor PM11, the source electrode of the MOS transistor PM12, the source electrode of the MOS transistor PM13, and the source electrode of the MOS transistor PM14 are respectively connected to the fifth port of the controllable driving circuit.

8. The adaptive control chip for driving speed of built-in MOS transistor according to claim 5, wherein the reference voltage V is_HIs greater than the reference voltage V_L。

9. A flyback converter characterized by comprising the built-in MOS tube driving speed adaptive control chip of claim 4, 6 or 7.

10. A flyback converter characterized by comprising the built-in MOS tube driving speed adaptive control chip of any one of claims 5 to 7.

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