CN114337273A - Control circuit and method with slope compensation - Google Patents

Abstract

Embodiments of the present disclosure relate to control circuits and methods for multiphase switching converters. The multiphase switching converter includes a plurality of voltage conversion circuits coupled in parallel. The control circuit comprises a slope compensation circuit, wherein the slope compensation circuit receives the total control signal and the inductive current sampling signal of each voltage conversion circuit and generates a slope signal according to the total control signal and each current sampling signal. The falling slope of the ramp signal changes with the phase value of the voltage conversion circuit and the value of the inductor current sampling signal. The ramp signal is used for performing ramp compensation on the control loop, and is beneficial to the stability of the multiphase switching converter.

Description

Control circuit and method with slope compensation

Technical Field

The present invention relates to electronic circuits, and more particularly, to control circuits and methods with slope compensation in multiphase switching converters.

Background

With the rapid development of the consumer electronics market, the switching converter has also been widely used, and in some control schemes of the switching converter, it is often necessary to consider introducing slope compensation to avoid system oscillation in order to make the switching converter operate stably. However, in the multiphase switching converter, because the number of cascaded phases is different, how to perform better slope compensation and avoid unstable oscillation of the multiphase converter is a key point to be considered.

Disclosure of Invention

The present invention is directed to solving the above problems in the prior art, and provides a control circuit and a control method for a multiphase switching converter.

According to an aspect of the present invention, there is provided a control circuit for a multiphase switching converter including N voltage conversion circuits connected in parallel, where N is an integer equal to or greater than 2, the control circuit comprising: the loop control module receives a ramp signal and a voltage feedback signal representing the output voltage of the multiphase switching converter and generates a total control signal according to the ramp signal and the voltage feedback signal; and the slope compensation circuit is used for receiving the total control signal and the N current sampling signals and generating the slope signal according to the total control signal and the N current sampling signals, wherein each current sampling signal represents the inductive current in the corresponding voltage conversion circuit, and the N current sampling signals are used for adjusting the falling slope of the slope signal.

According to another aspect of the present invention, there is provided a control method for a multiphase switching converter including N voltage conversion circuits connected in parallel, where N is an integer equal to or greater than 2, the control method including: generating an overall control signal according to a ramp signal and a voltage feedback signal representing an output voltage of the multiphase switching converter; respectively sampling the value of the inductive current in each phase voltage conversion circuit and generating N current sampling signals; generating the ramp signal according to the total control signal and N current sampling signals, wherein the N current sampling signals are used for adjusting the falling slope of the ramp signal; and dividing the total control signal into N control signals, wherein each control signal controls the on-off switching of a controllable switch in a corresponding voltage conversion circuit.

Drawings

FIG. 1 is a circuit schematic of a multiphase switching converter 100 according to one embodiment of the invention;

FIG. 2 is a circuit schematic of a multiphase switching converter 200 according to one embodiment of the invention;

FIG. 3 is a circuit schematic of control circuit 20 according to one embodiment of the present invention;

FIG. 4 is a circuit schematic of the slope compensation circuit 23 according to one embodiment of the present invention;

fig. 5 is a circuit schematic diagram of a slope compensation circuit 23 according to yet another embodiment of the present invention;

fig. 6 is a circuit schematic diagram of a slope compensation circuit 23 according to yet another embodiment of the present invention;

fig. 7 is a circuit schematic diagram of a slope compensation circuit 23 according to another embodiment of the present invention;

fig. 8 is a flow chart illustrating an embodiment of a control method for a multiphase switching converter.

As shown in the drawings, like reference numerals refer to like parts throughout the different views. The drawings presented herein are for purposes of illustrating the embodiments, principles, concepts and the like and are not necessarily drawn to scale.

Detailed Description

Specific embodiments of the present invention will now be described without limitation in conjunction with the accompanying drawings. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The verbs "comprising" and "having" are used herein as open-ended limitations that neither exclude nor require the presence of unrecited features. The features recited in the dependent claims may be freely combined with each other, unless explicitly stated otherwise. The use of the terms "a" or "an" (i.e., singular forms) in defining an element throughout this document does not exclude the possibility of a plurality of such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct or may be via one or more other elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When referring to a voltage of a node or terminal, the voltage is considered to be the voltage between the node and a reference potential (typically ground) unless otherwise indicated. Further, when referring to the potential of a node or a terminal, the potential is considered to refer to a reference potential unless otherwise indicated. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of the logic signal may correspond to voltages or currents that may not be completely constant in the high or low states.

Fig. 1 is a circuit schematic of a multiphase switching converter 100 according to one embodiment of the invention. In the embodiment shown in fig. 1, multiphase switching converter 100 includes N parallel voltage conversion circuits (illustrated as 11, 12, …, 1N, respectively), control circuit 20, capacitor Cout, and a sampling circuit. Wherein N is an integer of 2 or more. The outputs of each voltage conversion circuit are connected together and coupled to the output of the switching converter 100. The capacitor Cout is coupled between the output of the switching converter 100 and ground.

In one embodiment, the N voltage conversion circuits (11, 12, …, 1N) are identical in structure. Each voltage conversion circuit comprises at least one controllable switch tube. Each voltage conversion circuit receives a corresponding phase control signal (PWM1, PWM2, …, PWMN) which switches on and off by controlling a controllable switch in each phase of the voltage conversion circuit, thereby converting the input voltage VIN to the output voltage VOUT. In one embodiment, the N parallel voltage converting circuits are illustrated as integrated circuit chips with the same structure and function, and those skilled in the art will understand that the N parallel voltage converting circuits may also be circuits built by discrete devices instead of integrated circuits. In the embodiment shown in fig. 1, the inductors L are all illustrated inside the integrated chip as part of the voltage conversion circuit (11, 12, …, 1N). In other embodiments, the inductance L may be placed outside the integrated chip. In addition, those skilled in the art will also appreciate that the multiphase switching converter 100 can employ any number of voltage conversion circuits in interleaved parallel connection according to the load requirements to provide higher current to accommodate more high current demand situations.

In the embodiment shown in fig. 1, the voltage conversion circuits (11, 12, …, 1N) are illustrated as switching circuits of BUCK topology. The main switching tube HS and the follow current switching tube LS are connected in series between the input end of the voltage conversion circuit and the reference ground, and the common node of the main switching tube HS and the follow current switching tube LS is marked as a switching node SW. The inductor L is coupled between the switch node SW and the output terminal of the voltage conversion circuit. It will be appreciated by those of ordinary skill in the art that in other embodiments, the voltage translation circuits (11, 12, …, 1N) may be illustrated as other types of suitable isolated or non-isolated topologies, such as BOOST topologies, BUCK-BOOST topologies, Z-type topologies, CUK topologies, FLYBACK topologies, and so forth.

In the embodiment shown in fig. 1, the main switch HS and the freewheeling switch LS are illustrated as N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). It will be appreciated by those skilled in the art that in other embodiments, the main switch HS and the freewheeling switch LS may also include other suitable Semiconductor switch device types, such as Junction Field-effect transistors (JFETs), Insulated Gate Bipolar Transistors (IGBTs), Double Diffused Metal Oxide Semiconductors (DMOS), and so on.

In one embodiment, the sampling circuit includes a voltage sampling circuit and a current sampling circuit. In the embodiment shown in fig. 1, a voltage sampling circuit is coupled to the output terminal of the multiphase switching converter 100 for sampling the output voltage VOUT and generating a voltage feedback signal VFB, wherein the voltage feedback signal VFB represents the output voltage VOUT. In one embodiment, the voltage sampling circuit includes a voltage divider formed of resistors. In the embodiment shown in fig. 1, the current sampling circuit IS used for sampling the current flowing through the inductor L in each phase of the voltage conversion circuit and generating current sampling signals (IS1, IS2, …, ISN). In one embodiment, the voltage signal at node SW may also be used to represent the current flowing through inductor L. Thus, in one embodiment, the voltage signal at node SW may be representative of the current flowing through inductor L, and thus the current sample signal may be the voltage signal at node SW. For example, the current sample signal IS1 may include a voltage signal at the node SW in the voltage converting circuit 11, the current sample signal IS2 may include a voltage signal at the node SW in the voltage converting circuit 12, and so on.

In the embodiment shown in fig. 1, the control circuit 20 receives the voltage feedback signal VFB and the current sampling signals (IS1, IS2, …, ISN) of the voltage-per-phase converting circuits, and generates N phase control signals (PWM1, PWM2, …, PWMN) for controlling on and off switching of the controllable switches in the voltage-per-phase converting circuits, respectively, based on the voltage feedback signal VFB and the current sampling signals (IS1, IS2, …, ISN).

In yet another embodiment, the control circuit 20 includes a loop control module 21 and a slope compensation circuit 23.

The loop control module 21 generates a total control signal PWM according to the voltage feedback signal VFB and the RAMP signal RAMP.

The slope compensation circuit 23 generates a slope signal RAMP based on the total control signal PWM and the current sampling signals (IS1, IS2, …, ISN) of the voltage conversion circuits per phase. The N current sampling signals (IS1, IS2, …, ISN) are used to adjust the falling slope of the RAMP signal RAMP. In one embodiment, the falling slope of the RAMP signal RAMP IS related to the values of the N current sample signals (IS1, IS2, …, ISN). In one embodiment, the falling slope of the RAMP signal RAMP IS related to the "operating condition" of the corresponding phase circuit characterized by the N current sample signals (IS1, IS2, …, ISN). In one embodiment, "operating condition" refers to whether a controllable switch in each phase of the voltage conversion circuit is operating. For example, when the value of a certain current sampling signal is not zero, the phase circuit is defined as "working"; when the value of a certain current sampling signal is zero, the controllable switch in the phase circuit is characterized to stop switching, the phase circuit enters an intermittent mode, and the phase circuit is defined to be out of work at the moment. In one embodiment, the falling slope of the RAMP signal RAMP is proportional to the number of "active" phase circuits during a switching cycle of the multiphase switching converter 100/200. I.e., the greater the number of phase circuits that are "active", the greater the falling slope of the RAMP signal RAMP and vice versa.

In one embodiment, the control circuit 20 further includes a phase splitting circuit 22. The phase separation circuit 22 receives the overall control signal PWM and generates N phase control signals (PWM1, PWM2, …, PWMN) according to the overall control signal PWM. The N-phase control signals (PWM1, PWM2, … and PWMN) have the same phase shift in sequence, so that the N-phase voltage conversion circuit can realize staggered parallel operation.

In one embodiment, the phase splitting circuit 22 includes a frequency divider that divides the overall control signal PWM to produce N phase control signals (PWM1, PWM2, …, PWMN). In other embodiments, such as a master-slave cascaded system, the phase splitting circuit 22 in the master circuit splits the total control signal PWM into two phase control signals, one phase control signal for controlling the voltage switching circuit in the master circuit and the other phase control signal to the next phase circuit in the cascade. For example, fig. 2 illustrates a switching converter circuit 200 in a master-slave cascade. In the embodiment shown in fig. 2, assuming that the first phase circuit 91 is a master circuit and the other phase circuits (92, …, 9N) are slave circuits, the phase separation circuit 22 in the first phase circuit 91 generates the first phase control signal PWM1 and the first output signal PWMout1 based on the overall control signal PWM. The first output signal PWMout1 is provided to the phase splitting circuit 22 of the second phase circuit 92 to generate the second phase control signal PWM2 and the second output signal PWMout2 based on the first output signal PWMout1, and so on. In the embodiment shown in fig. 2, the control circuit 20 and the switch converter circuit 11 are schematically integrated in the same chip. In other embodiments, the control circuit 20 and the switch converter circuit 11 may be constructed by using discrete devices.

Fig. 3 is a circuit schematic of the control circuit 20 according to an embodiment of the present invention. In the embodiment shown in FIG. 3, the control circuit 20 includes a loop control module 21, a slope compensation circuit 23, and a phase splitting circuit 22. Fig. 3 illustrates a Constant On Time (COT) controlled loop control module 21. In the embodiment shown in fig. 3, the loop control module 21 is illustrated as including an error amplification circuit 211, a comparison circuit 212, an on-time control circuit 213, and a logic circuit 214.

In one embodiment, the error amplifier circuit 211 receives the voltage feedback signal VFB and compares the voltage feedback signal VFB with a reference voltage signal VREF to generate an error signal Vea, wherein the error signal Vea represents a difference between the voltage feedback signal VFB and the reference voltage signal VREF. In one embodiment, the error amplifier circuit 211 comprises an error amplifier having a non-inverting input receiving the voltage feedback signal VFB and an inverting input receiving the reference voltage signal VREF.

In one embodiment, the comparison circuit 212 receives the error signal Vea, the voltage feedback signal VFB, and the RAMP signal RAMP. In one embodiment, the RAMP signal RAMP generated by the RAMP compensation circuit 23 includes a first RAMP signal RAMP1 and a second RAMP signal RAMP 2. In one embodiment, the comparison circuit 212 compares the sum of the first RAMP signal RAMP1 and the voltage feedback signal VFB with the sum of the second RAMP signal RAMP2 and the error signal Vea to generate the comparison signal TOFF. In one embodiment, the comparison signal TOFF comprises a high-low logic level signal for controlling the turn-on time of the controllable switch in the voltage conversion circuit (11, 12, …, 1N). For example, in one embodiment, when the comparison signal TOFF changes from logic low to logic high, the main switch tube (e.g., the main switch tube HS in the BUCK converter shown in fig. 1) in the voltage conversion circuit 11 is turned on, and the freewheeling switch tube (e.g., the lower switch tube LS in the BUCK converter) is turned off. In one embodiment, the comparator circuit 212 includes a voltage comparator having a non-inverting input receiving the error signal Vea and the second RAMP signal RAMP2 and an inverting input receiving the voltage feedback signal VFB and the first RAMP signal RAMP 1. In other embodiments, the comparison circuit 212 may also compare the sum of the first RAMP signal RAMP1 and the error signal Vea with the sum of the second RAMP signal RAMP2 and the voltage feedback signal VFB to generate the comparison signal TOFF.

The on-period control circuit 213 generates an on-period control signal TON. The on-time control signal TON is used to control the on-time of the controllable switches in the N voltage converting circuits (11, 12, …, 1N) in the embodiment shown in fig. 1. In one embodiment, the on-time control signal TON is used to control the on-time of the main switch HS in the voltage converting circuit. In other embodiments, the on-time control circuit 213 can also receive the input voltage VIN and the output voltage VOUT and generate the on-time control signal TON according to the input voltage VIN and the output voltage VOUT. In this case, the on-time control signal TON may vary with variations of the input voltage signal VIN and the output voltage signal VOUT, thereby implementing adaptive constant-time on-control.

The logic circuit 214 receives the comparison signal TOFF and the on-time control signal TON, and performs a logic operation on the comparison signal TOFF and the on-time control signal TON to generate a total control signal PWM. In the embodiment shown in fig. 3, the logic circuit 214 is illustrated as an RS flip-flop, a set terminal S of the RS flip-flop receives the comparison signal TOFF, a reset terminal R of the RS flip-flop receives the on-time control signal TON, and the RS flip-flop outputs the total control signal PWM at an output terminal Q.

Those skilled in the art will appreciate that fig. 3 is merely a symbolic illustration of a constant on-time controlled voltage loop control circuit. In other embodiments, other suitable control methods can be used to generate the total control signal PWM according to the actual system requirements, and these methods are within the scope of the present invention.

Fig. 4 is a circuit schematic diagram of the slope compensation circuit 23 according to an embodiment of the present invention. In the embodiment shown in fig. 4, the slope compensation circuit 23 includes a single pulse generation circuit 231, a controllable current source 232, a slope capacitor 233, a filter circuit 234, and an adjustable resistance network 30.

The single pulse generating circuit 231 receives the overall control signal PWM and generates a single pulse signal PLS of a fixed time width at the start timing of each active state of the overall control signal PWM. In one embodiment, the single pulse generating circuit 231 generates the single pulse signal PLS at each rising edge timing of the overall control signal PWM. The single pulse generating circuit 231 may set the pulse width of the single pulse signal PLS signal according to system requirements.

The controllable current source 232 is coupled between the supply voltage VCC and the ramp capacitor 233, and receives control of the single pulse signal PLS. During the active phase of the single pulse signal PLS, the controllable current source 232 charges the ramp capacitor 233. During the period when the single pulse signal PLS is inactive, the controllable current source 232 stops charging the ramp capacitor 233. In one embodiment, the active period of the single pulse signal PLS refers to a period in which the pulse signal has a pulse width; the period in which the single pulse signal PLS is inactive refers to a period in which the pulse signal does not have pulses. In one embodiment, the peak value of the RAMP signal RAMP is determined by the pulse width of the single pulse signal PLS and the magnitude of the current provided by the controllable current source.

The adjustable resistance network 30 has a first terminal, a second terminal, and N control terminals. A first terminal of the adjustable resistor network 30 is coupled to a common terminal of the controllable current source 232 and the ramp capacitor 233; a second terminal of the adjustable resistor network 30 is electrically connected to a reference ground; the N control terminals of the adjustable resistor network 30 receive the N current sampling signals (IS1, IS2, …, ISN), respectively. The resistance value of the adjustable resistor network 30 is related to the number of phases of the voltage converting circuit connected in parallel with the multiphase switching converter 100/200 and the value of the inductor current in each phase of the voltage converting circuit. In one embodiment, after the controllable current source 232 stops charging the ramp capacitor 233, the ramp capacitor 233 is discharged through the resistor network 30. The adjustable resistor network 30 adjusts the resistance of the adjustable resistor network 30 according to the N current sampling signals (IS1, IS2, …, ISN), thereby changing the discharge rate of the ramp capacitor 233.

In the embodiment shown in fig. 4, the adjustable resistor network 30 includes N ramp resistors (R1, R2, …, RN), N ramp switches (M1, M2, …, MN), and N zero-crossing comparators (COM1, COM2, …, COMN).

Each ramp resistor has a first end and a second end. Each ramp switch has a first terminal, a second terminal, and a control terminal. The first ends of each of the ramp resistors are coupled together as a first end of an adjustable resistor network 30; the second terminal of each ramp resistor is coupled to the first terminal of a corresponding ramp switch, and the second terminals of each ramp switch are coupled together as the second terminal of the adjustable resistor network 30. For example, the second terminal of the ramp resistor R1 is coupled to the first terminal of the corresponding ramp switch M1; the second terminal of the ramp resistor R2 is coupled to the first terminal of the corresponding ramp switch M2, and so on.

Each zero crossing comparator (COM1, COM2, … or COMN) has a first input receiving the corresponding current sampling signal (IS1, IS2, … or ISN), a second input receiving the zero crossing reference signal Zth, and an output, and each zero crossing comparator (COM1, COM2, … or COMN) compares the received corresponding current sampling signal (IS1, IS2, … or ISN) with the zero crossing reference signal Zth to generate a corresponding zero crossing indication signal (ZCD1, ZCD2, … or ZCDN). Each zero crossing indication signal (ZCD1, ZCD2, … or ZCDN) is to be sent to a control terminal of a corresponding ramp switch (M1, M2, … or MN) for controlling on and off switching of the corresponding ramp switch (M1, M2, … or MN). For example, a first input terminal of the zero-crossing comparator COM1 IS connected to the current sampling signal IS1, a second input terminal thereof receives the zero-crossing reference signal Zth, and the zero-crossing comparator COM1 compares the received current sampling signal IS1 with the zero-crossing reference signal Zth and generates a zero-crossing indication signal ZCD1, wherein the zero-crossing indication signal ZCD1 IS used for controlling on and off switching of the ramp switch M1; the first input end of the zero-crossing comparator COM2 IS connected with the current sampling signal IS2, the second input end thereof receives the zero-crossing reference signal Zth, the zero-crossing comparator COM2 compares the received current sampling signal IS2 with the zero-crossing reference signal Zth and generates a zero-crossing indication signal ZCD2, the zero-crossing indication signal ZCD2 IS used for controlling the on-off switching of the ramp switch M2, and so on. In one embodiment, the N zero crossing indication signals (ZCD1, ZCD2, …, ZCD) are all high and low logic level signals having an active state and an inactive state. In one embodiment, when the zero-crossing indication signal is in an invalid state, the corresponding ramp switch is kept conducted; when the zero-crossing indication signal changes from the inactive state to the active state, the corresponding ramp switch is turned off. In one embodiment, a logic low level indicates an active state of the signal for each zero crossing. For example, when the zero-crossing indication signal ZCD1 changes from an inactive state (e.g., a logic high level) to an active state (e.g., a logic low level), it indicates that the current sampling signal IS1 falls to zero, and the ramp switch M1 IS turned off; when the zero crossing indication signal ZCD2 changes from an inactive state (e.g., a logic high level) to an active state (e.g., a logic low level), it indicates that the current sampling signal IS2 falls to zero, the ramp switch M2 IS turned off, and so on.

It will be understood by those skilled in the art that in practical design, the zero-crossing reference signal Zth is a value close to zero, not completely equal to zero, which is related to the precision (e.g., offset voltage value) of the zero-crossing comparator.

By charging and discharging the RAMP capacitor 233, the first RAMP signal RAMP1 is finally generated at the common terminal of the RAMP capacitor 233 and the controllable current source 232. The filter circuit 234 receives the first RAMP signal RAMP1 and filters the first RAMP signal RAMP1 to generate a second RAMP signal RAMP 2. The second RAMP signal RAMP2 is used to perform dc compensation on the voltage comparator introduced into the second RAMP signal RAMP 2.

In the embodiment shown in fig. 4, the dc voltage value VDC of the first RAMP signal RAMP1 and the second RAMP signal RAMP2 may be illustrated as:

where Q is the charge amount of the ramp capacitor 233, N is the number of phases of the multiphase switching converter 100/200, T is the switching period of each phase voltage conversion circuit, and Rreg is the resistance value of the adjustable resistance network 30. As can be seen from the above formula, in one embodiment, in order to ensure that the dc voltage value VDC does not vary with the multiphase switching converter 100, it is possible to adjust the resistance value Rreg of the adjustable resistance network 30. In one embodiment, the more phases are connected in parallel in the multiphase switching converter 100/200, the less the resistance value Rreg of the adjustable resistance network 30 can be adjusted. In this way, the dc voltage value VDC of the first RAMP signal RAMP1 and the second RAMP signal RAMP2 remains unchanged, and the influence on the system is minimized, which is beneficial to the stability of the system. In one embodiment, the resistance value Rreg of the adjustable resistance network 30 is inversely proportional to the number of phase circuits that are "active".

Fig. 5 is a schematic circuit diagram of the slope compensation circuit 23 according to another embodiment of the present invention. The embodiment shown in fig. 5 differs from the embodiment shown in fig. 4 most significantly: the embodiment shown in fig. 5 also includes a ramp peak control circuit 40. In the embodiment shown in fig. 4, the charging time of the ramp capacitor 233 by the controllable current source 232 is determined by the pulse width of the pulse signal PLS generated by the single pulse generating circuit. In the embodiment shown in fig. 5, the charging time of the ramp capacitor 233 by the controllable current source 232 can be precisely controlled by the ramp peak control circuit 40. It should be noted that in the embodiment shown in fig. 5, the controllable current source 232 is illustrated as a constant current source 2321 and a current switch 2322. The constant current source 2321 is coupled to one end of the ramp capacitor 233 through the current switch 2322; the turning on and off of current switch 2322 is controlled by ramp peak control circuit 40. Specifically, the ramp peak control circuit 40 includes a coulomb counter 41 and a flip-flop 42. The coulometer 41 samples the current flowing through the current switch 2322 and generates a charge indication signal. The pulse signal PLS is used to set the flip-flop 42 to turn on the current switch 2322; the charge indication signal is used to reset the flip-flop 42 to turn off the current switch 2322.

Fig. 6 is a schematic circuit diagram of the slope compensation circuit 23 according to another embodiment of the present invention. The embodiment shown in fig. 6 differs from the embodiment shown in fig. 4 in that: the embodiment shown in fig. 6 illustrates an adjustable resistor network 50 having a different circuit configuration. As shown in fig. 6, the adjustable resistance network 50 includes N controllable current sources (511, 512, …, 51N), a resistor 52, an operational amplifier 53, and a transistor 54. Each controllable current source (511, 512, …, or 51N) has a first terminal, a second terminal, and a control terminal. A first terminal of each controllable current source (511, 512, … or 51N) receives a supply voltage VCC; a second terminal of each of the controllable current sources (511, 512, …, or 51N) is coupled together and to a first terminal of a resistor 52; the control terminal of each controllable current source (511, 512, … or 51N) receives a corresponding current sample signal (IS1, IS2, … or ISN). A second terminal of resistor 52 is connected to ground. The operational amplifier 53 has a first terminal, a second terminal, and an output terminal. A first terminal of the operational amplifier 53 is coupled to a first terminal of the resistor 52; the second terminal of the operational amplifier 53 is electrically connected to ground. Transistor 54 has a source, a drain, and a gate. Wherein, the gate of the transistor 54 is coupled to the output terminal of the operational amplifier 53; a source of the transistor 54 is coupled to the second terminal of the operational amplifier 53; the drain of transistor 54 is coupled to a first terminal of a ramp capacitor 233 (i.e., the common node of the controllable current source 232 and the ramp capacitor 233). In other embodiments, the adjustable resistor network 50 further includes a resistor 55, the resistor 55 being coupled between the source of the transistor 54 and ground.

In one embodiment, each current sampling signal (IS1, IS2, … or ISN) controls the current value outputted by the corresponding controllable current source (511, 512, … or 51N) according to the magnitude of the respective current value, so as to adjust the voltage value on the resistor 52 and further control the resistance value of the transistor 54. The resistance value output by the adjustable resistance network 50 IS controlled by the current sampling signals (IS1, IS2, … and ISN), and the falling slope of the first RAMP signal RAMP1 IS adjusted due to different discharge time of the RAMP capacitor 233 through the adjustable resistance network 50. In one embodiment, each current sampling signal (IS1, IS2, …, or ISN) may also control the current value output by the corresponding controllable current source (511, 512, …, or 51N) according to the "operating condition" of the corresponding phase circuit characterized by each current sampling signal (IS1, IS2, …, ISN), thereby adjusting the resistance value output by the adjustable resistance network 50. In one embodiment, the "operating condition" refers to whether the controllable switches in each phase voltage conversion circuit are operating, as defined in the embodiment of fig. 4. For example, when the value of a certain current sampling signal is not zero, the phase circuit is defined as "working"; when the value of a certain current sampling signal is zero, the controllable switch in the phase circuit is characterized to stop switching, the phase circuit enters an intermittent mode, and the phase circuit is defined to be out of work at the moment. In one embodiment, when a corresponding phase circuit characterized by a certain current sampling signal is "inactive", the corresponding controllable current source is turned off to supply no current; when a corresponding phase circuit represented by a certain current sampling signal works, the corresponding controllable current source outputs current. In this application, the adjustable resistor network 50 may further include N zero-crossing comparators (COM1, COM2, …, COMN) as in the embodiments shown in fig. 4 and 5.

Fig. 7 is a circuit schematic diagram of the slope compensation circuit 23 according to another embodiment of the present invention. The embodiment shown in fig. 7 differs from the embodiment shown in fig. 6 the most: the embodiment shown in fig. 7 also includes a ramp average control circuit 60. In the embodiment shown in fig. 7, the charging time of the ramp capacitor 233 by the controllable current source 232 is precisely controlled by the ramp peak control circuit 40. The ramp average control circuit 60 has a first input terminal, a second input terminal, and an output terminal. A first input terminal of the RAMP mean value control circuit 60 receives the second RAMP signal RAMP 2; a second input terminal thereof receives the average reference signal ref-avg, and the RAMP average control circuit 60 compares the received second RAMP signal RAMP2 with the average reference signal ref-avg and generates the RAMP average control signal RAMP-avg at an output terminal. In one embodiment, the RAMP average control signal RAMP-avg may be provided to the single pulse generating circuit 231 for controlling whether the single pulse generating circuit 231 operates, that is: and controls whether the single pulse generating circuit 231 generates a pulse signal at the active edge timing of the overall control signal PWM. For example, when the value of the second RAMP signal RAMP2 is equal to the average reference signal ref-avg, the RAMP average control signal RAMP-avg controls the single pulse generation circuit 231 to stop operating. In other embodiments, the slope compensation circuit shown in fig. 6 further includes a current switch (e.g., current switch 2322 in the embodiment shown in fig. 5) coupled between the controllable current source 232 and the first terminal of the slope capacitor 233. For example, when the value of the second RAMP signal RAMP2 is equal to the average reference signal ref-avg, the RAMP average control signal RAMP-avg controls the current switch to be turned off.

Fig. 8 is a flow chart illustrating an embodiment of a control method for a multiphase switching converter. The control method shown in fig. 8 may be used in the multiphase switching converter 100/200 described above, as well as other multiphase switching converters within the scope of the present application. The control method comprises steps 81-85.

And 81, generating a total control signal PWM according to the RAMP signal RAMP and a voltage feedback signal VFB of the output voltage VOUT of the multiphase switching converter.

The values of the inductor currents in each phase of the voltage conversion circuit are sampled and N current sampling signals (IS1, IS2, …, ISN) are generated, respectively, step 82.

And step 83, generating the RAMP signal RAMP according to the total control signal PWM and the N current sampling signals (IS1, IS2, …, ISN), wherein the falling slope of the RAMP signal RAMP changes with different values of N. In this step, an adjustable resistor network may be used to adjust the falling slope of the RAMP signal RAMP, wherein the N current sampling signals (IS1, IS2, …, ISN) adjust the falling slope of the RAMP signal RAMP by adjusting the resistance value of the adjustable resistor network.

And step 84, generating N control signals (PWM1, PWM2, … and PWMN) according to the total control signal PWM, wherein each control signal controls the on-off switching of the controllable switch in the corresponding voltage conversion circuit. The N-phase control signals (PWM1, PWM2, … and PWMN) have the same phase shift in sequence, so that the N-phase voltage conversion circuit can realize staggered parallel operation.

While the present invention has been described with reference to several exemplary embodiments, it is understood by those of ordinary skill in the relevant art that the terms used in the embodiments of the present invention disclosed are intended in an illustrative and exemplary rather than in a limiting sense, and are used in a descriptive sense only and not for purposes of limitation. Furthermore, various modifications in form and detail of the disclosed embodiments of the invention may occur to those skilled in the art without departing from the spirit and concept of the invention and, therefore, such modifications are intended to be included within the scope of the present invention as defined in the appended claims and their equivalents.

Claims (11)

1. A control circuit for a multiphase switching converter including N voltage conversion circuits connected in parallel, where N is an integer greater than or equal to 2, the control circuit comprising:

the loop control module receives a ramp signal and a voltage feedback signal representing the output voltage of the multiphase switching converter and generates a total control signal according to the ramp signal and the voltage feedback signal; and

and the slope compensation circuit receives the total control signal and N current sampling signals and generates the slope signal according to the total control signal and the N current sampling signals, wherein each current sampling signal represents the inductive current in the corresponding voltage conversion circuit, and the N current sampling signals are used for adjusting the falling slope of the slope signal.

2. The control circuit of claim 1, wherein the slope compensation circuit comprises:

the single pulse generating circuit receives the master control signal and generates a single pulse signal at the effective edge moment of the master control signal;

the controllable current source is provided with a first end, a second end and a control end, wherein the first end of the controllable current source receives the power supply voltage, and the control end of the controllable current source receives the single pulse signal;

the first end of the ramp capacitor is coupled with the second end of the controllable current source, and the second end of the ramp capacitor is electrically connected to the reference ground, wherein a voltage signal on the first end of the ramp capacitor is used as the ramp signal; and

the adjustable resistor network is provided with a first end, a second end and N control ends, the first end of the adjustable resistor network is coupled with the first end of the ramp capacitor, the second end of the adjustable resistor network is electrically connected to a reference ground, the N control ends respectively receive corresponding N current sampling signals, and the N current sampling signals are used for adjusting the resistance value of the adjustable resistor network.

3. The control circuit of claim 2, wherein the ramp signal comprises a first ramp signal and a second ramp signal, the voltage signal on the first terminal of the ramp capacitor being the first ramp signal, the ramp compensation circuit further comprising:

and the filter circuit receives the first slope compensation signal and filters the first slope compensation signal to generate a second slope compensation signal.

4. The control circuit of claim 2, wherein the adjustable resistance network comprises:

each zero-crossing comparator is provided with a first input end, a second input end and an output end, the first input end of each zero-crossing comparator receives the corresponding current sampling signal, the second input end of each zero-crossing comparator receives a zero-crossing reference signal, and each zero-crossing comparator compares the received current sampling signal with the zero-crossing reference signal to generate a corresponding zero-crossing indication signal;

n ramp resistors, each having a first end and a second end, the first ends of each ramp resistor being coupled together as a first end of an adjustable resistor network; and

the first end of each ramp switch is coupled with the second end of the corresponding ramp resistor, the second end of each ramp switch is coupled together to serve as the second end of the adjustable resistor network, and the control end of each ramp switch receives the corresponding zero-crossing indication signal.

5. The control circuit of claim 3, wherein the adjustable resistance network comprises:

the adjusting resistor is provided with a first end and a second end, and the second end of the adjusting resistor is connected to the reference ground;

the current sampling circuit comprises N controllable current sources, a current sampling circuit and a current sampling circuit, wherein each controllable current source is provided with a first end, a second end and a control end, the first end of each controllable current source receives a supply voltage, the second end of each controllable current source is coupled to the first end of an adjusting resistor, and the control end of each controllable current source receives a corresponding current sampling signal;

the operational amplifier is provided with a first input end, a second input end and an output end, wherein the first input end of the operational amplifier is coupled with the first end of the adjusting resistor, and the second input end of the operational amplifier is connected with the reference ground; and

and the transistor is provided with a source electrode, a drain electrode and a grid electrode, wherein the grid electrode of the transistor is coupled with the output end of the operational amplifier, the source electrode of the transistor is coupled with the second end of the operational amplifier, and the drain electrode of the transistor is coupled with the first end of the ramp capacitor.

6. The control circuit of claim 4, wherein the controllable current source comprises a constant current source and a current switch connected in series between the supply voltage and the first end of the ramp capacitor, the control circuit further comprising:

a coulometer for sampling the current flowing through the current switch and generating a charge indicating signal; and

the trigger is provided with a set end, a reset end and an output end, the set end of the trigger receives a single pulse signal, the reset end of the trigger receives a charge indication signal, the output end of the trigger outputs a charging control signal, and the charging control signal is used for controlling the on and off of the current switch.

7. The control circuit of claim 5, wherein the control circuit further comprises:

the slope average control circuit is provided with a first input end, a second input end and an output end, wherein the first input end of the slope average control circuit receives a second slope signal, the second input end of the slope average control circuit receives an average reference signal, the slope average control circuit compares the received second slope signal with the average reference signal and generates a slope average control signal at the output end, and the slope average control signal is used for controlling whether the single-pulse circuit works or not.

8. The control circuit of claim 3, wherein the loop control module comprises:

the error amplifying circuit receives the voltage feedback signal and compares the voltage feedback signal with an output voltage reference signal to generate an error signal;

a comparison circuit receiving the error signal, the voltage feedback signal, the first ramp signal and the second ramp signal, the comparison circuit comparing a sum of the first ramp signal and the voltage feedback signal with a sum of the second ramp signal and the error signal to generate a comparison signal;

a conduction time control circuit for generating a conduction time control signal; and

and the logic circuit receives the comparison signal and the conduction time control signal, performs logic operation on the comparison signal and the conduction time control signal, and generates a master control signal.

9. The control circuit of claim 1, wherein the control circuit further comprises a phase splitting circuit, the phase splitting circuit receives the overall control signal and generates N phase control signals according to the overall control signal, the N phase control signals are in one-to-one correspondence with the N voltage converting circuits, and each phase control signal is used for controlling on and off switching of a controllable switch in the corresponding voltage converting circuit.

10. A control method for a multiphase switching converter including N voltage conversion circuits connected in parallel, where N is an integer equal to or greater than 2, the control method comprising:

generating an overall control signal according to a ramp signal and a voltage feedback signal representing an output voltage of the multiphase switching converter;

respectively sampling the value of the inductive current in each phase voltage conversion circuit and generating N current sampling signals;

generating the ramp signal according to the total control signal and N current sampling signals, wherein the N current sampling signals are used for adjusting the falling slope of the ramp signal;

and dividing the total control signal into N control signals, wherein each control signal controls the on-off switching of a controllable switch in a corresponding voltage conversion circuit.

11. The control method of claim 10, wherein the generating the ramp signal according to the total control signal and the N current sampling signals comprises:

and adjusting the falling slope of the ramp signal by adopting an adjustable resistance network, wherein the N current sampling signals adjust the falling slope of the ramp signal by adjusting the resistance value of the adjustable resistance network.

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