CN114334657B - Methods for forming fin structures and methods for forming FinFET devices - Google Patents
Methods for forming fin structures and methods for forming FinFET devicesInfo
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- CN114334657B CN114334657B CN202111643210.9A CN202111643210A CN114334657B CN 114334657 B CN114334657 B CN 114334657B CN 202111643210 A CN202111643210 A CN 202111643210A CN 114334657 B CN114334657 B CN 114334657B
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Abstract
The invention provides a fin structure forming method and a fin structure forming method, the fin structure forming method comprises the steps of providing a substrate, forming a first dielectric layer, filling between fins in a fin group, forming a second dielectric layer, filling the fin group, covering the first dielectric layer, etching the second dielectric layer between the fin groups to form a groove, forming a third dielectric layer, filling the groove, enabling the first dielectric layer and the second dielectric layer to have opposite types of stress, performing a heat treatment process to form an isolation dielectric layer, and removing part of the isolation dielectric layer with thickness to enable the exposed part of fins to serve as a fin structure. According to the invention, the first dielectric layer, the second dielectric layer and the third dielectric layer are used for filling the space between the fin groups, and the stress between the fin groups is balanced by utilizing that the first dielectric layer and the second dielectric layer have opposite types of stress and the stress of the third dielectric layer is smaller than that of the first dielectric layer and the second dielectric layer, so that the stress difference between the fin groups is reduced, and the fin deformation is prevented.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to a method for forming a fin structure and a method for forming a FinFET device.
Background
With the continuous development of semiconductor technology, it has been difficult for conventional planar devices to meet the demands of high-performance devices. A Fin Field Effect Transistor (FinFET) is a three-dimensional device, which includes a Fin vertically formed on a substrate and a gate structure covering both sides of the Fin.
However, during the formation of the fin structure (fin) of the FinFET device, the fin is easily deformed (bent or inclined), which is not beneficial to the subsequent process (such as the formation of the source-drain structure in the fin and the formation of the gate structure on the fin), and may also cause electric leakage between the gate and the source-drain, which seriously affects the performance and reliability of the FinFET device.
Disclosure of Invention
The invention aims to provide a fin structure forming method and a FinFET device forming method, which are used for solving the problem of inclination or bending of a fin structure.
The method for forming the fin structure comprises the steps of providing a substrate, wherein the substrate is provided with at least two fin groups which are arranged at intervals, each fin group comprises at least two fins which are arranged at intervals, the interval between the fin groups is larger than the interval between the fins in the fin groups, forming a first dielectric layer which is filled between the fins in the fin groups and covers the surfaces of the fins and the substrate, forming a second dielectric layer which is filled between the fin groups and covers the surfaces of the first dielectric layer, performing an etching process to form grooves in the second dielectric layer between the fin groups, forming a third dielectric layer which is filled in the grooves, the stress of the first dielectric layer and the stress of the second dielectric layer are smaller than those of the first dielectric layer, performing a heat treatment process to enable the third dielectric layer, the second dielectric layer and the fin layer to be formed into a part of a dielectric isolation structure, and removing the third dielectric layer to be used as a part of the dielectric isolation structure.
Optionally, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer include one or more of silicon oxide, silicon oxynitride and silicon oxycarbide.
Optionally, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer all include silicon oxide and are formed by different processes.
Optionally, the first dielectric layer is formed by using an FCVD process of ozone treatment, the second dielectric layer is formed by using an FCVD process of ultraviolet treatment, or the first dielectric layer is formed by using an FCVD process of ultraviolet treatment, and the second dielectric layer is formed by using an FCVD process of ozone treatment.
Optionally, after the second dielectric layer is formed on the first dielectric layer and before the third dielectric layer is formed, a fourth dielectric layer is formed, the fourth dielectric layer covers the second dielectric layer, the third dielectric layer covers the fourth dielectric layer, and a planarization process is performed on the fourth dielectric layer.
Optionally, forming a trench in the second dielectric layer between the fin sets includes forming a mask layer with an opening that at least partially exposes the fourth dielectric layer between the fin sets, etching the fourth dielectric layer and a portion of the second dielectric layer to form the trench using the mask layer, and removing the mask layer.
Optionally, the fourth dielectric layer and the third dielectric layer are made of the same material and are formed by adopting the same process conditions.
Optionally, the cross section of the groove is inverted trapezoid.
Optionally, the process gas used in the heat treatment process includes one or more of steam, hydrogen, oxygen, and nitrogen.
According to another aspect of the present application, an embodiment of the present application further provides a method for forming a FinFET device, where the method for forming a FinFET device includes the method for forming a fin structure described above.
In summary, according to the method for forming the fin structure and the method for forming the FinFET device provided by the invention, the first dielectric layer is filled between fins in the fin group and partially filled between fins, the second dielectric layer and the third dielectric layer are filled between fins, the first dielectric layer and the second dielectric layer are utilized to have opposite types of stress, the stress of the third dielectric layer is smaller than that of the first dielectric layer and the second dielectric layer, and the stress balance among the fins is realized by balancing the first dielectric layer, the second dielectric layer and the third dielectric layer between the fins after heat treatment, so that the stress difference at two sides of the fins is reduced to prevent the fins from deforming, and the problem of inclination or bending of the fin structure is solved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation on the scope of the invention.
Fig. 1 is a flowchart of a method for forming a fin structure according to an embodiment of the present application;
Fig. 2a to 2h are schematic structural diagrams corresponding to respective steps of a method for forming a fin structure according to the present embodiment.
In the accompanying drawings:
10-substrate, 11-fin set, 111-fin;
21-a first dielectric layer, 22-a second dielectric layer, 23-a third dielectric layer, 24-a fourth dielectric layer, 25-a mask layer and 26-a trench;
30-isolating dielectric layer.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.
Fig. 1 is a flowchart of a method for forming a fin structure according to an embodiment of the present application.
As shown in fig. 1, the method for forming a fin structure provided in this embodiment includes the following steps:
S01, providing a substrate, wherein the substrate is provided with at least two fin groups which are arranged at intervals, each fin group comprises at least two fins which are arranged at intervals, and the interval between the fin groups is larger than the interval between the fins in the fin groups;
S02, forming a first dielectric layer, wherein the first dielectric layer is filled between fins in the fin group and covers the surfaces of the fins and the substrate;
s03, forming a second dielectric layer, wherein the second dielectric layer is filled between the fin groups and covers the surface of the first dielectric layer;
s04, performing an etching process to form a groove in the second dielectric layer between the fin groups;
s05, forming a third dielectric layer, wherein the third dielectric layer fills the groove, the first dielectric layer and the second dielectric layer have opposite types of stress, and the stress of the third dielectric layer is smaller than that of the first dielectric layer and that of the second dielectric layer;
And S06, executing a heat treatment process, forming the third dielectric layer, the second dielectric layer and the first dielectric layer into isolation dielectric layers, and removing part of the isolation dielectric layers with the thickness, wherein the exposed part of the fins is used as fin structures.
Fig. 2a to 2h are schematic structural diagrams corresponding to corresponding steps of the fin structure forming method according to the present embodiment, and the fin structure forming method will be described in detail with reference to fig. 2a to 2 h.
Referring to fig. 2a, step S01 is performed to provide a substrate 10, where the substrate 10 has at least two fin groups 11 arranged at intervals, each fin group 11 includes at least two fins 111 arranged at intervals, and a spacing between the fin groups 11 is greater than a spacing between the fins 111 in the fin groups 11.
The substrate 10 may be any suitable base material known to those skilled in the art, and may be, for example, at least one of silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. The material of the substrate 10 in this embodiment is exemplified by silicon.
Specifically, a plurality of fins 111 may be formed on the surface of the substrate 10 by using a self-aligned multiple patterning technique, and a hard mask layer (not shown) is remained on the top wall of the fins 111. The spacing between fins 111 in the fin group 11 and the specific spacing between the fin groups 11 may be determined according to practical requirements, and the spacing between fins 111 is not limited. In this embodiment, two fin groups 11 are located on the substrate 10, each fin group 11 includes 4 fins 111, and the spacing between the fin groups 11 is greater than the spacing between the fins 111 in the fin groups 11. Of course, in practice, the number of fins 111 within different fin groups 11 may also be different.
Next, referring to fig. 2b, step S02 is performed to form a first dielectric layer 21, where the first dielectric layer 21 fills between the fins 111 in the fin group 11 and covers the surfaces of the fins 111 and the substrate 10.
Specifically, the first dielectric layer 21 has better step coverage, can conformally cover the outer wall of the fin 111 and the surface of the substrate 10, and is filled in the fin group 11 and between the fin groups 11. In implementation, since the spacing between the fins 111 in the fin group 11 is smaller than the spacing between the fin groups 11, the first dielectric layer 21 can be filled between the fins 111 in the fin group 11 and partially fill the space between the fin groups 11 (cover the surface of the substrate 10) by controlling the filling amount and the filling rate of the first dielectric layer 21. The depth of the first dielectric layer 21 partially filling the fin group 11 can be specifically set in combination with the height at which the fins 111 begin to deform (bend or tilt) in the actual process, so that the filling depth is lower than or equal to the height at which the fins 111 begin to deform in the actual process, so as to improve the morphology of the fins 111 through the stress on both sides of the fins 111.
The first dielectric layer 21 may be formed by using an ozone curing FCVD (Ozone FCVD) process or an ultraviolet curing FCVD (UV cure FCVD) process to improve the filling effect, and the material of the first dielectric layer 21 includes silicon oxide, silicon oxynitride or silicon oxycarbide.
Next, referring to fig. 2c, step S03 is performed to form a second dielectric layer 22, where the second dielectric layer 22 fills between the fin groups 11 and covers the surface of the first dielectric layer 21.
The material and the forming process of the second dielectric layer 22 may be selected, so that the second dielectric layer 22 (after curing) has a stress opposite to that of the first dielectric layer 21 (after curing), so as to balance the stress between the first dielectric layer 21 and the second dielectric layer 22 between the fin groups 11.
Preferably, the material of the second dielectric layer 22 is the same as that of the first dielectric layer 21 but is formed by different processes so as to achieve different stresses, and an etching process can be used to etch both simultaneously so as to simplify the subsequent process steps. In this embodiment, if the first dielectric layer 21 is, for example, silicon oxide formed by an ozone-cured FCVD process, the second dielectric layer 22 may be silicon oxide formed by an ultraviolet-cured FCVD process, and if the first dielectric layer 21 is silicon oxide formed by an ultraviolet-cured FCVD process, the second dielectric layer 22 may be silicon oxide formed by an ozone-cured FCVD process. It should be appreciated that the first dielectric layer 21 (after curing) formed by the ozone-cured FCVD process has a tensile stress and the second dielectric layer 22 (after curing) formed by the ultraviolet-cured FCVD process has a tensile stress.
Next, referring to fig. 2d, a fourth dielectric layer 24 is formed, the fourth dielectric layer 24 covers the second dielectric layer 22, and a planarization process is performed on the fourth dielectric layer 24.
The fourth dielectric layer 24 with a flat surface serves as a subsequent process platform to facilitate the corresponding photolithography and etching processes. Preferably, the fourth dielectric layer 24 may be silicon oxide formed using a PECVD process to facilitate subsequent etching. It should be appreciated that the second dielectric layer 22 fills the fin group 11, and the top surface thereof is not flat, which is detrimental to the subsequent photolithography and etching processes. Of course, in other embodiments, the fourth dielectric layer 24 may not be formed, but the first dielectric layer 22 is primarily cured, and a planarization process is performed on the primarily cured second dielectric layer 22, so as to facilitate the subsequent photolithography process and etching process.
Next, in step S04, referring to fig. 2e, an etching process is performed to form a trench 26 in the second dielectric layer 22 between the fin sets 11.
The specific steps may include, for example, forming a mask layer 25 on the fourth dielectric layer 24, exposing the fourth dielectric layer 24 between the fin sets 11 through the openings of the mask layer 25, etching the fourth dielectric layer 24 and the second dielectric layer 22 using the mask layer 25, and forming trenches 26 in the second dielectric layer 22 between the fin sets 11. The depth of the trench 26 and the width of the trench 26 may be adjusted according to the deformation degree of the actual fin, so as to adjust the volume ratio of the first dielectric layer 21 between the fin groups 11, the second dielectric layer 22 remaining between the fin groups 11 after forming the trench 26, and the third dielectric layer to be filled in the trench 26, so as to achieve stress balance between the fin groups 11.
Preferably, the cross-sectional shape of the trench 26 is inverted trapezoid (wide upper and narrow lower) to facilitate filling of the subsequent third dielectric layer.
Next, in step S05, referring to fig. 2f, a third dielectric layer 23 is formed, the third dielectric layer 23 fills the trench 26, the first dielectric layer 21 and the second dielectric layer 22 have opposite types of stress, and the stress of the third dielectric layer 23 is smaller than the stress of the first dielectric layer 21 and the second dielectric layer 22.
Specifically, the mask layer 25 on the fourth dielectric layer 24 may be removed first, and then the third dielectric layer 23 is formed to fill the trench 26, cover the second dielectric layer 22, and extend to cover the fourth dielectric layer 24.
The third dielectric layer 23 is filled in the trenches 26 between the fin groups 11, and the stress of the third dielectric layer 23 is smaller than the stress of the first dielectric layer 21 and the stress of the second dielectric layer 22, so as to adjust the volume ratio (ratio) of the first dielectric layer 21 and the second dielectric layer 22 between the fin groups 11, so that the stress balance between the fin groups 11 is realized by utilizing different stress types of the first dielectric layer 21 and the second dielectric layer 22 and smaller stress of the third dielectric layer 23, and further, the fins 111 in the fin groups 11 are prevented from being deformed (bent or inclined) due to the stress unbalance between the fin groups 11.
Further, the material and the forming process (process conditions) of the third dielectric layer 23 may be the same as those of the fourth dielectric layer 24, so as to facilitate the subsequent etching.
Further, the third dielectric layer 23 may be made of the same material as the first dielectric layer 21 and the second dielectric layer 22, but the forming process is different to facilitate the subsequent etching. In this embodiment, the material of the third dielectric layer 23 is silicon oxide, and may be formed by a PECVD process or a HARP (HIGHASPECT RATIO PROCESS ) process. It should be appreciated that the silicon oxide formed using the PECVD process or the HARP process has a lower expansion rate, i.e., has less stress, after the heat treatment.
Next, step S06 is performed, referring to fig. 2g and fig. 2h, a heat treatment process is performed to form the third dielectric layer 23, the second dielectric layer 22, the first dielectric layer 21 and the fourth dielectric layer 24 into the isolation dielectric layer 30, and remove a portion of the thickness of the isolation dielectric layer 30, so that the exposed portion of the fin 111 is used as a fin structure.
Specifically, the process gas used in the heat treatment process (annealing process) includes one or more of steam, hydrogen, oxygen, and nitrogen, so that the first dielectric layer 21 and the second dielectric layer 22 formed by using different FCVD may be cured in the heat treatment process, and thus the stress balance between the fin groups 11 is achieved. After the heat treatment, the materials of the first dielectric layer 21 and the second dielectric layer 22 (for example, silicon oxide mixture) are converted into silicon dioxide, which is the same (or similar) as the materials of the fourth dielectric layer 24 and the third dielectric layer 23, so as to form (as) the isolation dielectric layer 30. Thus, a portion of the isolation dielectric layer 30 may be removed by dry etching to expose a portion of the fin 111, and the exposed portion of the fin 111 may be used as a fin structure.
The embodiment of the application also provides a forming method of the FinFET device, wherein the FinFET device comprises a fin structure, the forming method of the FinFET device comprises the forming method of the fin structure, namely the forming method of the FinFET device comprises the forming method of the fin structure.
In summary, according to the method for forming the fin structure and the method for forming the FinFET device provided by the invention, the first dielectric layer is filled between fins in the fin group and partially filled between fins, the second dielectric layer and the third dielectric layer are filled between fins, the first dielectric layer and the second dielectric layer are utilized to have opposite types of stress, the stress of the third dielectric layer is smaller than that of the first dielectric layer and the second dielectric layer, and the stress balance among the fins is realized by balancing the first dielectric layer, the second dielectric layer and the third dielectric layer between the fins after heat treatment, so that the stress difference at two sides of the fins is reduced to prevent the fins from deforming, and the problem of inclination or bending of the fin structure is solved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103187439A (en) * | 2011-12-29 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, formation method of semiconductor structure, complementary metal-oxide-semiconductor transistor (CMOS) and formation method of CMOS |
| CN103367253A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor forming method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7960791B2 (en) * | 2005-06-24 | 2011-06-14 | International Business Machines Corporation | Dense pitch bulk FinFET process by selective EPI and etch |
| US20120070947A1 (en) * | 2010-09-16 | 2012-03-22 | Globalfoundries Inc. | Inducing stress in fin-fet device |
| CN103515223A (en) * | 2012-06-20 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | FinFET manufacturing method |
| US8877588B2 (en) * | 2013-02-11 | 2014-11-04 | Globalfoundries Inc. | Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device |
| US9177955B2 (en) * | 2013-03-08 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation region gap fill method |
| US9548213B2 (en) * | 2014-02-25 | 2017-01-17 | International Business Machines Corporation | Dielectric isolated fin with improved fin profile |
| CN112103182B (en) * | 2019-06-18 | 2024-05-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187439A (en) * | 2011-12-29 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, formation method of semiconductor structure, complementary metal-oxide-semiconductor transistor (CMOS) and formation method of CMOS |
| CN103367253A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor forming method |
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