CN114326336B - Large-size chip exposure method - Google Patents

Abstract

The invention discloses a large-size chip exposure method, and belongs to the field of integrated circuit manufacturing. Dividing a chip to be manufactured into a structure formed by splicing a plurality of chips; manufacturing a photomask corresponding to each layer of circuit structure of each spliced chip; placing the photoetching pattern of the first spliced chip on the position of the first spliced chip of the wafer, exposing the first spliced chip, and leaving a mark of an alignment mark on the wafer; placing the photoetching patterns of the second spliced chips at the positions of the second spliced chips of the wafer, selecting alignment marks left after the exposure of the first spliced chips during alignment, and performing alignment exposure; and the like until the exposure of all spliced chips of the current level is completed. The mark is exposed when the mark is aligned in the subsequent exposure of the current layer, namely, the splicing precision among the patterns of the current layer is met, the process flows of one-time exposure and corrosion are saved, and the cost is reduced.

Description

Large-size chip exposure method

Technical Field

The invention relates to the technical field of integrated circuit manufacturing, in particular to a large-size chip exposure method.

Background

The exposure process is a very important process in the process of manufacturing chips, and the purpose of the exposure process is to transfer the geometric figure on the photolithography mask onto the wafer, and then form a circuit structure on the wafer through processes such as corrosion and the like.

Obviously, the geometry of the reticle is essentially the circuit structure of the chip, which is transferred to the wafer by means of exposure. When large chips are produced by an integrated circuit, sometimes the size is too large to exceed the field of view limit of a photoetching machine, the whole pattern cannot be transferred to a wafer through one exposure, at this time, the chip needs to be divided into a plurality of chips with the size smaller than or equal to the maximum exposure field of view of the photoetching machine, the exposure is carried out for a plurality of times by using a plurality of photoetching plates, and the pattern exposed by different photoetching plates is spliced to obtain a complete chip pattern, namely so-called spliced exposure.

At this time, the overlay accuracy among different patterns of the same layer for multiple exposure has great influence on the electrical parameters and yield of the product, and the alignment method plays a very important role in the precision of pattern splicing. In the actual process, when the exposure of the photoetching machine is aligned, the alignment is generally carried out by leaving marks on the pattern on the upper layer, and then the alignment precision is confirmed by developing and reading the alignment value. When the same layer is subjected to multiple exposure, the alignment of the same layer with the previous layer and the alignment of the same layer with the previous several exposure patterns are realized, so that an accurate splicing effect is achieved. In this case, if good splicing effect between different exposure patterns on the same layer is to be maintained, an alignment mark needs to be manufactured on the wafer in advance, and the process steps are increased.

Disclosure of Invention

The invention aims to provide a large-size chip exposure method, which is used for saving one-time exposure and corrosion process flows and reducing cost.

In order to solve the above technical problems, the present invention provides a method for exposing a large-sized chip, comprising:

dividing a chip to be manufactured into a structure formed by splicing a plurality of chips;

manufacturing a photomask corresponding to each layer of circuit structure of each spliced chip;

placing the photoetching pattern of the first spliced chip on the position of the first spliced chip of the wafer, exposing the first spliced chip, and leaving a mark of an alignment mark on the wafer after exposure;

placing the photoetching patterns of the second spliced chips at the positions of the second spliced chips of the wafer, selecting alignment marks left after the exposure of the first spliced chips during alignment, and performing alignment exposure;

and the like until the exposure of all spliced chips of the current level is completed.

Optionally, the chip to be manufactured is divided into a structure formed by splicing a plurality of chips according to the area size of the maximum exposure field of the photoetching machine.

Optionally, the size of each split chip is smaller than or equal to the maximum exposure field of the photoetching machine.

Optionally, after the exposure of all the spliced chips in the current layer is completed, the large-size chip exposure method further includes:

developing and inspecting the wafer, if the overlay difference exists, adjusting an overlay correction value, and entering the next working procedure after the wafer is qualified;

the subsequent exposure of the layers can be performed by using the alignment marks left after the photoetching and corrosion of the previous layers until the whole chip process flow is completed.

In the large-size chip exposure method provided by the invention, no extra mark is required to be manufactured, only the mark of the shallow alignment mark left after the primary exposure of the current level is required to be found, and the mark is aligned for exposure in the subsequent exposure of the current level, so that the splicing precision between the patterns of the current level can be met, the one-time exposure and corrosion process flow is saved, and the cost is reduced.

Drawings

FIG. 1 is a schematic flow chart of a large-size chip exposure method provided by the invention;

FIG. 2 is a schematic illustration of a latent image formed after exposure of a first splice chip;

FIG. 3 is a schematic diagram of the complete chip stitching after exposing a second stitched chip to an alignment latent image;

fig. 4 is a schematic diagram of a first layer of a developed completed chip.

Detailed Description

The following describes a method for exposing a large-sized chip according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The invention provides a large-size chip exposure method, the flow of which is shown in figure 1, comprising the following steps:

s11, dividing a chip to be manufactured into a structure formed by splicing a plurality of chips;

step S12, manufacturing a photomask corresponding to each layer of circuit structure of each spliced chip;

step S13, placing the photoetching pattern of the first spliced chip at the position of the first spliced chip of the wafer, exposing the first spliced chip, and leaving a mark of an alignment mark on the wafer after exposure;

s14, placing the photoetching patterns of the second spliced chips at the positions of the second spliced chips of the wafer, selecting alignment marks left after the exposure of the first spliced chips during alignment, and performing alignment exposure;

and S15, and the like until the exposure of all spliced chips in the current layer is completed.

Taking the chip division into two parts as an example for illustration: dividing a chip to be manufactured into a structure formed by splicing two chips according to the area size of the maximum exposure view field of the photoetching machine, wherein the size of each spliced chip is smaller than or equal to the maximum view field of the photoetching machine;

manufacturing a photomask corresponding to each layer of circuit structure of the two spliced chips according to the dividing result;

through the accurate operation of the photoetching machine, the photoetching pattern of the first spliced chip is placed at the position of the first spliced chip of the wafer, and is exposed, and a mark (latent image) of a shallow alignment mark is left on the wafer after exposure, as shown in fig. 2;

the photoetching pattern of the second spliced chip is placed at the position of the second spliced chip of the wafer through the accurate operation of the photoetching machine, and an alignment mark (latent image) left after the exposure of the first spliced chip is selected during alignment, so that alignment exposure is carried out, as shown in fig. 3;

developing the wafer to form a first layer pattern of the complete chip shown in fig. 4; performing display inspection, if the overlay difference exists, adjusting an overlay correction value, and entering the next working procedure after the overlay correction value is qualified;

the subsequent exposure of the layers can be performed by using the alignment marks left after the photoetching and corrosion of the previous layers until the whole chip process flow is completed.

The invention can save one exposure and corrosion process flow and reduce cost by using the latent image left on the wafer after the first exposure to conduct alignment exposure.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (4)

1. A method for exposing a large-sized chip, comprising:

dividing a chip to be manufactured into a structure formed by splicing a plurality of chips;

manufacturing a photomask corresponding to each layer of circuit structure of each spliced chip;

placing the photoetching pattern of the first spliced chip on the position of the first spliced chip of the wafer, exposing the first spliced chip, and leaving a mark of an alignment mark on the wafer after exposure;

placing the photoetching patterns of the second spliced chips at the positions of the second spliced chips of the wafer, selecting alignment marks left after the exposure of the first spliced chips during alignment, and performing alignment exposure;

and the like until the exposure of all spliced chips of the current level is completed.

2. The method for exposing a large-sized chip according to claim 1, wherein the chip to be fabricated is divided into a structure formed by splicing a plurality of chips according to the area size of the maximum exposure field of the lithography machine.

3. The method of exposing large-sized chips as defined in claim 2, wherein the size of each of the divided splice chips is smaller than or equal to a maximum exposure field of view of the lithography machine.

4. The method for exposing a large-sized chip according to claim 1, wherein after the exposure of all splice chips of the current level is completed, the method for exposing a large-sized chip further comprises:

developing and inspecting the wafer, if the overlay difference exists, adjusting an overlay correction value, and entering the next working procedure after the wafer is qualified;

the subsequent exposure of the layers can be performed by using the alignment marks left after the photoetching and corrosion of the previous layers until the whole chip process flow is completed.