CN114300442A - Test structure and test method for metal gate - Google Patents

Abstract

The invention provides a test structure and a test method of a metal gate. The test structure is very sensitive to the problem that polycrystalline silicon cannot be completely replaced due to low STI in the metal gate manufacturing process, can effectively monitor the replacement failure condition of the metal gate, can test each wafer before shipment, can carry out long-term effective monitoring compared with a scanning defect mode, and improves the reliability of a metal gate device.

Description

Test structure and test method for metal gate

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a test structure and a test method of a metal gate.

Background technique

DDDMOS (Double Diffused Drain MOSFET) device is the abbreviation of double-diffused drain high-voltage MOSFET device, which is a commonly used lateral high-voltage MOS device. Due to the particularity of its structure, during the fabrication process, LDD IMP (ion implantation of the lightly doped region of the drain) needs to be done before forming the polysilicon dummy gate, rather than the traditional self-alignment after the polysilicon dummy gate is formed. Quasi-LDD. However, as shown in Figures 1 and 2, performing LDD IMP before forming the polysilicon dummy gate will change the etch rate of the oxide insulating layer for the etch (WET) of the shallow trench isolation structure (STI), and further The result is that the STI regions that have been subjected to LDDIMP are lower in height after etching than the STI regions that have not been subjected to LDDIMP. This has little effect in the traditional poly/SiON (polysilicon gate + carbon oxynitride insulating layer gate structure) process, but in the HKMG process, as shown in Figure 3, it will cause polysilicon to remain in the STI, making subsequent polysilicon unable to It is completely replaced with metal, and it is difficult to completely fill the metal, resulting in the failure of metal gate replacement. Failure to replace the metal gate will affect the stability of the metal gate and reduce the reliability of the device.

At present, the problem of metal gate replacement failure in DDDMOS can be found through defect scan, but this method has a low sample rate and cannot be inspected for every wafer. It cannot be used as a long-term effective monitoring method.

SUMMARY OF THE INVENTION

In view of this, the present invention provides a metal gate testing structure and method for testing the stability of the metal gate manufacturing process.

The present invention provides a test structure of a metal gate, comprising:

A number of active regions spaced apart from each other;

a metal gate serpentinely distributed across and on the active region;

LDD regions at both ends of the active region; and

first and second pads.

Preferably, the active regions are elongated and arranged in parallel from left to right.

Preferably, the spacing of the spaces between the active regions gradually increases from a design rule minimum value.

Preferably, the metal gates distributed on the active region are connected end-to-end to form a series structure.

Preferably, the interval size of the serpentine distribution is a design rule minimum value.

The present invention also provides a method for testing a metal gate, comprising:

Connect the voltage source and the current acquisition unit between the first and second pads to form a test circuit;

Apply test voltage and collect test current;

calculating the resistance value of the metal grid;

According to the resistance value, determine the stability of the metal gate;

In response to the resistance value being too large, the metal gate replacement fails.

Preferably, the method further comprises that the metal gate is successfully replaced in response to the smaller resistance value.

The test structure of the present invention can be used in all metal gate manufacturing processes, especially processes that are sensitive to AA/STI step heights, and can be used to test whether the metal gate manufacturing process is stable when the step height difference is too large. The test structure of the present invention can effectively test the metal gate, and test each wafer before shipment, thereby improving the reliability of the device.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram showing the formation of LDD regions by ion implantation on both sides of the active region;

Figure 2 shows a schematic diagram of high defect generation after STI etching of LDD IMP;

FIG. 3 is a schematic diagram showing that there is still polysilicon residue after removing the dummy gate polysilicon;

FIG. 4 shows a schematic diagram of lens electronics of a metal gate structure with silicon residues;

Figure 5 shows a schematic diagram of the lens electronics along the X direction;

Figure 6 shows a schematic diagram of the lens electronics along the Y direction;

7 is a schematic diagram illustrating a test structure of a metal gate according to an embodiment of the present invention;

FIG. 8 is a flowchart of a method for testing a metal gate according to an embodiment of the present invention.

Detailed ways

The present invention is described below based on examples, but the present invention is not limited to these examples only. In the following detailed description of the invention, some specific details are described in detail. The present invention can be fully understood by those skilled in the art without the description of these detailed parts. Well-known methods, procedures, procedures, components and circuits have not been described in detail in order to avoid obscuring the essence of the present invention.

Furthermore, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless clearly required by the context, words such as "including", "comprising" and the like throughout this application should be construed in an inclusive rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

In the description of the present invention, it should be understood that the terms "first", "second" and the like are used for descriptive purposes only, and should not be construed as indicating or implying relative importance. Also, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

WAT (Wafer acceptance test, Wafer Acceptance Test) is an electrical measurement of the chip after the end of the process flow to check whether each process flow meets the standards. The test items include device characteristic test, capacitance test, contact resistance test, Breakdown test, etc.

With the development of semiconductor technology, the size of transistors continues to shrink, and the advanced logic chip technology has reached the process below the 28nm node. In the process below 28 nm, a metal gate with a high dielectric constant gate dielectric layer is usually used, which is usually abbreviated as HKMG, where HK represents a high dielectric constant (HK) gate dielectric layer, and MG represents a metal gate.

In the formation process of HKMG, a dummy gate structure is usually formed first, and the dummy gate structure usually adopts a structure formed by stacking a gate dielectric layer and a polysilicon gate. After the dummy gate structure is used to form process structures such as the source and drain regions of the NMOS device or the PMOS device, the dummy gate structure is removed, and then the HKMG structure is formed in the removed area of the dummy gate structure. However, the formed metal gate often suffers from poor stability. As shown in Figure 4, Figure 5 and Figure 6, the defects in the semiconductor device were tested by transmission electron microscopy (TEM), and it was found that there was polysilicon residue. The reason is that Due to the particularity of the structure of DDDMOS, STI will produce high defects in the metal gate preparation process, and the low STI will make it difficult to completely remove the electronic polysilicon, and it cannot be completely replaced with metal, and the metal gate replacement fails.

In order to check out the metal gate with poor stability and replacement failure, the present invention provides a specially designed metal gate test structure, which is very sensitive to the problem that the dummy gate cannot be completely replaced due to the low STI of the DDD MOS. In the WAT test before shipment, by testing the resistance value of the pattern, it can be judged whether there is a problem of poor replacement of the dummy gate in the wafer. The technical solutions of the present invention are further described below with reference to the accompanying drawings and through specific embodiments.

FIG. 7 is a schematic diagram illustrating a test structure of a metal gate according to an embodiment of the present invention. As shown in FIG. 7 , the test structure of the metal gate according to the embodiment of the present invention includes several active regions 11 spaced apart from each other, LDD regions 12 located at both ends of the active region 11 , and an LDD region 12 that spans the active region 11 and is in the active region 11 . A metal grid with a serpentine distribution.

In the embodiment of the present invention, the substrate includes a plurality of active regions 11 , and the greater the number of active regions 11 , the more conducive to improving the reliability of the test. The number of active regions 11 is not specifically limited. The active regions 11 are isolated by STI.

In the embodiment of the present invention, the active regions 11 are elongated and arranged in parallel from left to right, and the spacing 14 between the active regions 11 gradually increases from the minimum design rule. Here, the spacing between the active regions is continuously increasing, which is used to test the different performances of the polysilicon gate across the STI at different spacings when replacing the metal gate.

In the embodiment of the present invention, the metal gates distributed on the active region 11 are connected end to end to form a series structure, and the series structure is in a serpentine shape, which may also be called an S shape. The interval dimension 15 of the serpentine distribution is the minimum value allowed by the design rules. The first bonding pad and the second bonding pad are arranged on both ends of the series structure.

In this embodiment of the present invention, the metal gate structure is integrated into a series structure, which is distributed on the active region 11 in a serpentine shape, so that the pads can be easily drawn out for testing, and in the WAT test, testing with other parts does not affect each other. .

The test structure of the metal gate of the present invention can effectively monitor the replacement failure of the metal gate, and can test each wafer before shipment. Compared with the method of scanning defects, it can carry out long-term effective monitoring and improve the metal gate. device reliability.

FIG. 8 is a flowchart of a method for testing a metal gate according to an embodiment of the present invention. As shown in Figure 8, it includes the following steps:

Step 1: Connect the voltage source and the current acquisition unit between the first and second pads to form a test circuit.

Step 2: Apply the test voltage and collect the test current.

Step 3: Calculate the resistance value of the metal gate.

Step 4: Judge the stability of the metal gate according to the resistance value.

Step 5. In response to the resistance value being too large, the replacement of the metal gate fails.

The testing method for the metal gate according to the embodiment of the present invention further includes that the metal gate is successfully replaced in response to the smaller resistance value.

The test structure is particularly sensitive to the de-metal gate process. Therefore, after the wafer enters the WAT test process, test the resistance between the two pads of the test structure. If the resistance is small, it means that the metal gate process of the transistor is safe. If it is large, it means that there may be a problem with the metal gate process of the transistor, and it cannot be shipped to customers. Specifically, in the embodiment of the present invention, a voltage source and a current acquisition unit are connected between the first and second pads to form a test circuit, the voltage source is used to apply a test voltage to the test structure of the metal gate, and the current acquisition unit is used to collect current in the circuit. Calculate the resistance of the metal gate. If the test resistance is low, the process of the transistor is normal; if the test resistance is very large, it means that the process of the transistor may cause the replacement of the metal gate to fail.

The present invention can be used in all processes that are sensitive to the AA/STI step height during the formation of the metal gate, and is used to test whether the metal gate process is stable when the step height difference is too large. The test structure of the present invention can effectively test the metal gate, and test each wafer before shipment, thereby improving the reliability of the device.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (7)

1. A test structure for a metal gate, comprising:

a plurality of active regions arranged at intervals;

a metal gate spanning and serpentine-shaped over the active region;

LDD regions located at both ends of the active region; and

first and second pads.

2. The metal gate test structure of claim 1, wherein the active regions are strips and are arranged in parallel from left to right.

3. The test structure of metal gate of claim 2, wherein the spacing between the active regions is gradually larger from a design rule minimum.

4. The test structure of claim 1, wherein the metal gates distributed on the active region are connected end to form a series structure.

5. The test structure of metal gate of claim 1, wherein the pitch dimension of the serpentine distribution is a design rule minimum.

6. A method of testing a metal gate using the metal gate test structure of claims 1-5, comprising:

connecting a voltage source and a current acquisition unit between the first welding pad and the second welding pad to form a test circuit;

applying a test voltage and collecting a test current;

calculating the resistance value of the metal gate;

judging the stability of the metal gate according to the resistance value;

in response to the resistance value being too large, the metal gate replacement fails.

7. The method of claim 6, further comprising the metal gate replacement being successful in response to the resistance value being small.

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