CN114299863B

CN114299863B - Signal generation circuit, scanning circuit, display panel and display device

Info

Publication number: CN114299863B
Application number: CN202111669545.8A
Authority: CN
Inventors: 翟应腾
Original assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Current assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2023-07-28
Anticipated expiration: 2041-12-31
Also published as: CN114299863A

Abstract

The invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, wherein a voltage holding unit can reset and stabilize the charge and discharge capacity, and the stability of the signal generating circuit is improved. In the display panel provided by the invention, the initial time of the pulse width control voltage generated by at least one signal generating circuit in all the signal generating circuits is different from the initial time of the pulse width control voltage generated by the other signal generating circuits, so that all the pixel driving circuits of the display panel are not different from the initial time to light the light emitting elements, the situation that the voltage drop is overlarge on the signal lines connected with the pixel driving circuits when all the light emitting elements are lightened at the same initial time is avoided, the stability of the pixel driving circuits is further improved, and the display effect of the display panel is improved.

Description

Signal generation circuit, scanning circuit, display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a signal generating circuit, a scanning circuit, a display panel, and a display device.

Background

With the continuous improvement of display technology, the requirements of display devices are also continuously improved, and among various display technologies, self-luminous display devices have been widely used in various electronic devices including electronic products such as computers and mobile phones, because of their advantages of self-luminescence, thinness, low power consumption, high contrast, high color gamut, and capability of realizing flexible display. The self-luminous elements in the existing self-luminous display device are generally organic light-emitting diodes (Organic Light Emitting Diode, OLED), quantum dot light-emitting diodes (Quantum Dot Light Emitting Diodes, QLED), micro light-emitting diodes (Micro Light Emitting Diodes, micro LED), and the like; in actual display, the pixel driving circuit outputs a driving current to drive the light emitting element to emit light with reference to a pulse width control voltage which is a ramp voltage, so that the display device achieves the purpose of displaying a picture.

Disclosure of Invention

In view of the above, the present invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, which improve the stability of the signal generating circuit and the display effect of the display panel.

In order to achieve the above purpose, the technical scheme provided by the invention is as follows:

A signal generating circuit comprising: the device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacity;

the access unit is used for responding to the generation control signal and communicating the constant current source with the first polar plate of the charge-discharge capacity, the first polar plate of the charge-discharge capacity is electrically connected with the output end of the signal generation circuit, and the second polar plate of the charge-discharge capacity is electrically connected with the grounding end;

the voltage holding unit is used for responding to a holding control signal and electrically connecting a grounding terminal with the first polar plate of the charging and discharging capacity;

the charging unit is used for responding to a charging control signal and transmitting a charging voltage to the first polar plate of the charging and discharging capacity.

Optionally, the access unit includes an access transistor, a first end of the access transistor is electrically connected with the constant current source, a second end of the access transistor is electrically connected with the first polar plate of the charging/discharging capacity, and a gate of the access transistor is accessed to the generation control signal;

the voltage holding unit comprises at least one holding transistor, a first end of the holding transistor is electrically connected with a grounding end, a second end of the holding transistor is electrically connected with a first polar plate of the charging and discharging capacity, and a grid electrode of the holding transistor is connected with the holding control signal;

The charging unit comprises a charging transistor, a first end of the charging transistor is connected with the charging voltage, a second end of the charging transistor is electrically connected with the first polar plate of the charging and discharging capacity, and a grid electrode of the charging transistor is connected with the charging control signal.

Optionally, the signal generating circuit further includes: and the voltage stabilizing unit is electrically connected between the first polar plate of the charge-discharge capacity and the output end of the signal generating circuit.

Optionally, the voltage stabilizing unit includes an operational amplifier, the in-phase end of the operational amplifier is electrically connected with the first polar plate of the charging/discharging capacity, and the inverting end of the operational amplifier and the output end of the operational amplifier are both electrically connected with the output end of the signal generating circuit.

Correspondingly, the invention also provides a scanning circuit, which comprises: any one of the first to nth signal generating circuits is the signal generating circuit described above, N being an integer greater than or equal to 2;

wherein, in the first signal generating circuit to the Nth signal generating circuit, the initial time of the signal generating circuit accessing the effective level of the generated control signal is different from the initial time of the other signal generating circuits accessing the effective level of the generated control signal.

Correspondingly, the invention also provides a display panel, which comprises:

a plurality of pixel driving circuit groups including a signal generating circuit and a pixel driving circuit;

the pixel circuit driving circuit comprises a pulse width modulation unit, a first light emitting control unit and a driving transistor; the pulse width modulation unit is used for outputting a pulse width setting signal by referring to a pulse width control voltage; the first light emitting control unit is used for responding to a first light emitting control signal and transmitting the pulse width setting signal to the grid electrode of the driving transistor;

the signal generating circuit is used for responding to the first light emitting control signal to generate the pulse width control voltage; wherein the initial time of the pulse width control voltage generated by at least one of the signal generating circuits is different from the initial time of the pulse width control voltages generated by the rest of the signal generating circuits.

Optionally, the signal generating circuit includes: the device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacity;

the access unit is used for responding to the first luminous control signal and communicating the constant current source with the first polar plate of the charge-discharge capacity, the first polar plate of the charge-discharge capacity is electrically connected with the output end of the signal generating circuit, and the second polar plate of the charge-discharge capacity is electrically connected with the grounding end;

Optionally, the access unit includes an access transistor, a first end of the access transistor is electrically connected with the constant current source, a second end of the access transistor is electrically connected with the first polar plate of the charging/discharging capacity, and a gate of the access transistor is accessed to the first light emitting control signal;

Optionally, the pulse width modulation unit is connected to a first control signal, a second control signal and the first light emitting control signal, and is used for responding to the first control signal to be connected to a reset voltage, responding to the second control signal to be connected to a first data voltage, and responding to the first light emitting control signal to be connected to a turn-off voltage;

the display panel comprises N rows of pixel driving circuits, wherein the first control signals of the pixel circuits of the (i+1) th row and the second control signals of the pixel circuits of the (i) th row are the same control signals, N is an integer larger than or equal to 2, and i is a positive integer smaller than N.

Optionally, the signal generating circuit includes the constant current source, the access unit, the voltage holding unit, the charging unit, and the charging/discharging capacity, the access unit includes the access transistor, the voltage holding unit includes at least one of the holding transistors, and the charging unit includes the charging transistor;

The pixel driving circuit group comprises M rows of pixel driving circuits, wherein the voltage holding unit comprises first holding transistors to M+1th holding transistors, the holding control signals comprise first sub-holding control signals to M+1th sub-holding control signals, the grid electrode of the j-th holding transistor is connected with the j-th sub-holding control signal, M is an integer larger than or equal to 1, and j is a positive integer smaller than or equal to M+1.

Alternatively, when M is equal to 1, or when M is greater than 1 and the pixel driving circuits of M rows are adjacent rows:

the k-th sub-holding control signal and the first control signal of the pixel driving circuit of the k-th row are the same signal, the M+1-th sub-holding control signal and the second control signal of the pixel driving circuit of the M-th row are the same signal, and k is a positive integer less than or equal to M;

and the charge control signal of the current pixel driving circuit group and the second control signal of the pixel driving circuit of the next pixel driving circuit group and the adjacent first row are the same signal.

Optionally, M is greater than 1 and at least one of the pixel driving circuits of M rows is located in a different row from the rest of the pixel driving circuits.

Optionally, the pixel driving circuit includes a light emitting element and further includes a light emitting reset unit for transmitting the reset voltage to the light emitting element in response to the second control signal.

Correspondingly, the invention also provides a display device which comprises the display panel.

Compared with the prior art, the technical scheme provided by the invention has at least the following advantages:

the invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, comprising: the device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacity; the access unit is used for responding to the generation control signal and communicating the constant current source with the first polar plate of the charge-discharge capacity, the first polar plate of the charge-discharge capacity is electrically connected with the output end of the signal generation circuit, and the second polar plate of the charge-discharge capacity is electrically connected with the grounding end; the voltage holding unit is used for responding to a holding control signal and electrically connecting a grounding terminal with the first polar plate of the charging and discharging capacity; the charging unit is used for responding to a charging control signal and transmitting a charging voltage to the first polar plate of the charging and discharging capacity. The signal generating circuit provided by the invention firstly resets and stabilizes the charge and discharge capacity through the voltage holding unit, then charges the charge and discharge capacity through the charging unit, and finally the access unit communicates the constant current source with the first polar plate of the charge and discharge capacity, and acts with the discharge process of the charge and discharge capacity to generate the slope voltage. Therefore, the voltage holding unit provided by the invention can reset and stabilize the charge and discharge capacity, and improves the stability of the signal generating circuit.

In the display panel provided by the invention, the initial time of the pulse width control voltage generated by at least one signal generating circuit in all the signal generating circuits is different from the initial time of the pulse width control voltage generated by the other signal generating circuits, so that all the pixel driving circuits of the display panel are not different from the initial time to light the light emitting elements, the situation that the voltage drop is overlarge on the signal lines connected with the pixel driving circuits when all the light emitting elements are lightened at the same initial time is avoided, the stability of the pixel driving circuits is further improved, and the display effect of the display panel is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a signal generating circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another signal generating circuit according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a signal generating circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a constant current source according to an embodiment of the present invention;

fig. 5 is a timing chart of a constant current source according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a signal generating circuit according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of a signal generating circuit according to another embodiment of the present invention;

fig. 8 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of another pixel driving circuit according to an embodiment of the present invention;

FIG. 12 is a timing diagram of a pixel driving circuit according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a pixel driving circuit set according to an embodiment of the present invention;

FIG. 14 is a timing diagram of a pixel driving circuit set according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of two adjacent pixel driving circuit groups according to an embodiment of the present invention;

FIG. 16 is a timing diagram of two adjacent pixel driving circuit sets according to an embodiment of the present invention;

Fig. 17 is a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the present invention;

fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As described in the background art, with the increasing display technology, the demands of people for display devices are increasing, and among various display technologies, self-luminous display devices have been widely used in various electronic devices including computers, mobile phones, and other electronic products, because they have advantages of self-luminescence, thinness, low power consumption, high contrast, high color gamut, and capability of realizing flexible display. The self-luminous elements in the existing self-luminous display device are generally organic light-emitting diodes, quantum dot light-emitting diodes, micro light-emitting diodes and the like; in actual display, the pixel driving circuit outputs a driving current to drive the light emitting element to emit light with reference to a pulse width control voltage which is a ramp voltage, so that the display device achieves the purpose of displaying a picture.

Based on the above, the embodiment of the invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, which improve the stability of the signal generating circuit and the display effect of the display panel.

In order to achieve the above objective, the technical solutions provided by the embodiments of the present invention are described in detail below, with reference to fig. 1 to 18. For convenience of explanation, the transistors in each circuit structure provided in the following embodiments of the present invention will be described by taking P-type transistors as examples.

Referring to fig. 1, a schematic structural diagram of a signal generating circuit according to an embodiment of the present invention is shown, where the signal generating circuit according to the embodiment of the present invention includes:

constant current source 110, access unit 120, voltage holding unit 130, charging unit 140, and charging/discharging capacity 150.

The access unit 120 is configured to communicate the constant current source 110 with a first electrode plate of the charge/discharge cell 150 in response to generating the control signal Kj, the first electrode plate of the charge/discharge cell 150 is electrically connected to the output terminal OUT of the signal generating circuit, and a second electrode plate of the charge/discharge cell 150 is electrically connected to the ground terminal GND.

The voltage holding unit 130 is configured to electrically connect the ground GND to the first plate of the charge/discharge cell 150 in response to a holding control signal Kb.

The charging unit 140 is configured to transmit a charging voltage Vc to the first electrode plate of the charging/discharging capacity 150 in response to the charging control signal Kc, where the charging voltage Vc is greater than the voltage of the ground GND, for example, the voltage of the ground GND is 0V, and the voltage of the charging/discharging voltage Vc may be 6V.

The working process of the signal generating circuit provided by the embodiment of the invention is as follows: first, the holding control signal Kb controls the operation of the voltage holding unit 130, and connects the ground terminal GND to the first electrode plate of the charge/discharge cell 150, and since the second electrode plate of the charge/discharge cell 150 is electrically connected to the ground terminal GND, the voltage holding unit 130 can perform resetting and voltage stabilizing processes on the charge/discharge cell 150; at this time, both the charging unit 140 and the access unit 120 are in a non-operating state. Then, the voltage holding unit 130 stops operating, and the charging control signal Kc controls the charging unit 140 to transmit the charging voltage Vc to the first electrode plate of the charging/discharging capacity 150 to charge the charging/discharging capacity 150; the access unit 120 is in a non-operating state at this time. Finally, the voltage holding unit 130 and the charging unit 140 both maintain the non-operating state, and generate the control signal Kj to control the access unit 120 to communicate the constant current source 110 with the first electrode plate of the charge/discharge vessel 150, so as to operate simultaneously with the discharge process of the charge/discharge vessel 150, so that the output terminal OUT outputs the ramp voltage. Therefore, the embodiment of the invention provides a technical solution, and the voltage holding unit 130 can reset and stabilize the charge/discharge cell 150 before generating the ramp voltage, so as to improve the stability of the signal generating circuit.

Referring to fig. 2, a schematic structural diagram of another signal generating circuit according to an embodiment of the present invention is shown, where the access unit 120 according to an embodiment of the present invention includes an access transistor Mj, a first end of the access transistor Mj is electrically connected to the constant current source 110, a second end of the access transistor Mj is electrically connected to the first polar plate of the charge/discharge cell 150, and a gate of the access transistor Mj is connected to the generation control signal Kj.

The voltage holding unit 130 includes at least one holding transistor Mb, a first terminal of which is electrically connected to the ground GND, a second terminal of which is electrically connected to the first electrode plate of the charge/discharge cell 150, and a gate of which is connected to the holding control signal Kb.

The charging unit 140 includes a charging transistor Mc, a first end of the charging transistor Mc is connected to the charging voltage Vc, a second end of the charging transistor Mc is electrically connected to the first electrode plate of the charging/discharging capacitor 150, and a gate of the charging transistor Mc is connected to the charging control signal Kc.

In an embodiment of the present invention, the access transistor Mj, the holding transistor Mb and the charging transistor Mc provided in the present invention may be all N-type transistors, or all P-type transistors or part of the transistors may be N-type transistors and part of the transistors may be P-type transistors. The operation of the signal generating circuit according to the embodiment of the present invention will be described in more detail with reference to the accompanying drawings. As shown in fig. 3, a timing diagram of a signal generating circuit according to an embodiment of the present invention is provided, wherein the signal generating circuit includes a first stage S11, a second stage S12, and a third stage S13. In the first stage S11, the hold control signal Kb is low, and the hold transistor Mb is controlled to be turned on, so that the ground GND is connected to the first plate of the charge/discharge cell 150, and the charge/discharge cell 150 is reset and stabilized. In the second stage S12, the charge control signal Kc is low, and controls the charge transistor Mc to be turned on, so as to transmit the charge voltage Vc to the first electrode of the charge/discharge cell 150, so as to charge the charge/discharge cell 150. In the third stage S13, the control signal Kj is generated to control the access transistor Mj to be turned on, so that the constant current source 110 is connected to the first electrode of the charge/discharge cell 150, and at the same time, the charge/discharge cell 150 starts to discharge, so that the output terminal OUT outputs the ramp voltage.

Referring to fig. 4, a schematic structural diagram of a constant current source according to an embodiment of the present invention is shown, where the constant current source includes a first constant current transistor M1, a second constant current transistor M2, a third constant current transistor M3, a fourth constant current transistor M4, a fifth constant current transistor M5, a sixth constant current transistor M6, and a holding capacitor C, where a first end of the first constant current transistor M1 is electrically connected to a second end of the fifth constant current transistor M5 and a first end of the third constant current transistor M3, a second end of the first constant current transistor M1 is electrically connected to a second end of the fourth constant current transistor M4 and a first end of the sixth constant current transistor M6, and a gate of the first constant current transistor M1 is electrically connected to a second end of the third constant current transistor M3, a first end of the holding capacitor C, and a second end of the second constant current transistor M2; the first end of the second constant current transistor M2 is connected with a reference voltage Vre, and the grid electrode of the second constant current transistor M2 is connected with a first constant current control signal L1; the grid electrode of the third constant current transistor M3 is connected with the second constant current control signal L2, the first end of the fourth constant current transistor M4 is connected with the limiting voltage Vds, the grid electrode of the fourth constant current transistor M4 is connected with the second constant current control signal L2, and the first end of the fifth constant current transistor M5 is connected with the voltage Vs, wherein the voltage Vs is smaller than the limiting voltage Vds, and the voltage Vs and the limiting voltage Vds are smaller than the GND voltage of the grounding end in the panel; the gate access of the fifth constant current transistor M5 generates the control signal Kj, the second terminal of the sixth constant current transistor M6 is the output terminal OUT1 of the constant current source, and the gate access of the sixth constant current transistor M6 generates the control signal Kj.

It will be appreciated that the constant current source is used to output a current to the output terminal OUT of the signal generating circuit when the switching unit 120 is operated in the signal generating circuit, so that the operation of the constant current source includes the same first, second and third stages S11, S12 and S13 as the signal generating circuit. As shown in the timing chart of fig. 5, in the first stage S11, the first constant current control signal L1 controls the second constant current transistor M2 to be turned on, and the reference voltage Vre is transmitted to the gate of the first constant current transistor M1 to perform the reset process; then in the second stage S12, the second constant current control signal L2 controls the third constant current transistor M3 and the fourth constant current transistor M4 to be turned on, so as to maintain the on state of the first constant current transistor M1; finally, in the third stage S13, the control signal Kj is generated to control the fifth constant current transistor M5 and the sixth constant current transistor M6 to be turned on, so as to form a path from the voltage Vs to the output terminal OUT1 for outputting the current.

It should be noted that, the embodiment of the present invention does not limit the conduction type of the transistor included in the constant current source, and the transistor may be an N-type transistor or a P-type transistor; and at least one of the transistors included in the constant current source can be a double-gate transistor, so that the response speed of the transistor is improved, the leakage current of the transistor is reduced, and the performance of the constant current source is improved. In the embodiment of the invention, the P-type transistors are taken as examples of all transistors included in the constant current source; in other embodiments of the present invention, all the transistors included in the constant current source may be N-type transistors; in other embodiments of the present invention, the circuit structure of the constant current source may be of other types, and specific design is required according to practical applications.

Referring to fig. 6, a schematic structural diagram of a signal generating circuit according to an embodiment of the present invention is shown, where the signal generating circuit according to the embodiment of the present invention further includes: and a voltage stabilizing unit 160 electrically connected between the first electrode plate of the charge/discharge cell 150 and the output terminal OUT of the signal generating circuit. Further, the voltage of the ramp voltage output from the output terminal OUT is stabilized by the voltage stabilizing unit 160 and then output, so that the performance of the signal generating circuit is improved.

The voltage stabilizing unit provided by the embodiment of the invention can comprise an operational amplifier. Referring to fig. 7, a schematic structural diagram of a signal generating circuit according to an embodiment of the present invention is shown, wherein the voltage stabilizing unit 160 according to an embodiment of the present invention includes an operational amplifier OP, the non-inverting terminal of the operational amplifier OP is electrically connected to the first electrode plate of the charge/discharge cell 150, and the inverting terminal of the operational amplifier OP and the output terminal of the operational amplifier OP are electrically connected to the output terminal OUT of the signal generating circuit.

Correspondingly, the embodiment of the invention also provides a scanning circuit. Referring to fig. 8, a schematic structural diagram of a scan circuit according to an embodiment of the present invention is shown, where the scan circuit includes: any one of the first signal generating circuit 101 to the nth signal generating circuit 10N is the signal generating circuit provided in any one of the above embodiments, and N is an integer greater than or equal to 2.

Among the first to nth signal generating circuits 101 to 10N, an initial time at which at least one of the signal generating circuits accesses the active level of the generated control signal is different from an initial time at which the other signal generating circuits access the active level of the generated control signal.

It can be understood that the effective level of the generated control signal provided by the embodiment of the invention is the corresponding control level of the control access unit for accessing the constant current source to the output end of the signal generation circuit; that is, the control signal generating circuit generates the control level of the ramp voltage. The initial time of the at least one signal difference generating circuit connected to the effective level of the generated control signal is different from other time points, which indicates that the initial time of the at least one signal generating circuit outputting the slope voltage is different. As shown in fig. 8, the first signal generating circuits 101 to the nth signal generating circuit 10N according to the embodiment of the present invention may be connected to the active level of the generation control signal one by one at regular intervals, so that the first signal generating circuits 101 to the nth signal generating circuit 10N may have a dislocation at the initial time of the ramp voltage output by the first signal generating circuits 101 to the nth signal generating circuit 10N, and the first signal generating circuits 101 to the nth signal generating circuit 10N sequentially output the ramp voltage. The broken line as shown in fig. 8 indicates the initial timing of the ramp voltage, and the first signal generating circuit 101 to the nth signal generating circuit 10N sequentially output the ramp voltage at regular intervals.

Correspondingly, the embodiment of the invention also provides a display panel. Referring to fig. 9 and fig. 10, fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 10 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention, where the display panel includes a display area AA and a non-display area NA located at a periphery of the display area AA, and the display panel includes:

the pixel driving circuit group 10 includes a signal generating circuit 100 and a pixel driving circuit 200, and the pixel driving circuit 200 may be located in the display area AA while the signal generating circuit 100 may be located in the non-display area NA.

The pixel circuit driving circuit 200 includes a pulse width modulation unit 210, a first light emitting control unit 231, and a driving transistor T0; the pwm unit 210 is configured to output a pulse width setting signal with reference to the pulse width control voltage Sweep; the first light emitting control unit 231 is configured to transmit the pulse width setting signal to the gate of the driving transistor T0 in response to the first light emitting control signal K1.

The signal generating circuit 100 is configured to generate the pulse width control voltage Sweep in response to the first light emitting control signal K1; wherein the initial time of the pulse width control voltage Sweep generated by at least one of the signal generating circuits 100 is different from the initial time of the pulse width control voltages Sweep generated by the rest of the signal generating circuits 100.

As shown in fig. 10, the pixel driving circuit 200 according to the embodiment of the invention further includes: an amplitude modulation unit 220, a second light emission control unit 232, and a light emitting element 240. The amplitude modulation unit 220 is configured to output an amplitude setting signal to the gate of the driving transistor T0. The driving transistor T0 is used to generate a driving current with reference to the amplitude setting signal and the pulse width setting signal. The second light emission control unit 232 is used to transmit the driving current generated by the driving transistor T0 to the light emitting element 240. The light emitting element 240 emits light in response to the driving current.

It can be understood that the pulse width control voltage Sweep provided by the embodiment of the present invention is a ramp voltage, which is used to control the pulse width modulation unit 210 to generate the pulse width setting signal, and the pulse width setting signal is used to control the duration of the driving transistor T0 generating the driving current, that is, the duration of the light emitting element connected to the pixel driving circuit. Since the signal generating circuit 100 generates the pulse width control voltage sleep in response to the first light emitting control signal K1 and the first light emitting control unit 231 is configured to transmit the pulse width setting signal to the gate of the driving transistor T0 in response to the first light emitting control signal K1, the generation time of the pulse width control voltage sleep and the time of the pulse width setting signal transmitted to the gate of the driving transistor T0 are synchronized.

Therefore, in the embodiment of the present invention, the initial time of the pulse width control voltage Sweep generated by at least one of the signal generating circuits 100 is set to be different from the initial time of the pulse width control voltage Sweep generated by the other signal generating circuits 100, which is equivalent to the initial time of at least one of the pulse width setting signals transmitted to the gate of the corresponding driving transistor T0 and the initial time of the other pulse width setting signals transmitted to the gate of the corresponding driving transistor T0, so that all the pixel driving circuits of the display panel light the light emitting elements at different initial times, thereby avoiding the occurrence of the situation that the voltage drop is excessively large for the signal lines connected to the pixel driving circuits when all the light emitting elements light at the same initial time, further improving the stability of the pixel driving circuits and the display effect of the display panel.

The specific structure of the signal generating circuit in the display panel according to the embodiment of the present invention will be described below with reference to the accompanying drawings, where the signal generating circuit in the display panel according to the present invention may have the same composition structure as the signal generating circuit according to any of the embodiments described above, but since the signal generating circuit according to the present invention is specifically applied to the display panel, the difference is that the control signals connected to some of the constituent units are different. Referring specifically to fig. 1, the signal generating circuit of the display panel according to an embodiment of the present invention includes: constant current source 110, access unit 120, voltage holding unit 130, charging unit 140, and charging/discharging capacity 150.

The access unit 120 is configured to connect the constant current source 110 to the first electrode plate of the charge/discharge cell 150 in response to the first light emitting control signal K1, the first electrode plate of the charge/discharge cell 150 is electrically connected to the output terminal OUT of the signal generating circuit, and the second electrode plate of the charge/discharge cell 150 is electrically connected to the ground terminal GND. The voltage holding unit 130 is configured to electrically connect the ground GND to the first plate of the charge/discharge cell 150 in response to a holding control signal Kb. The charging unit 140 is configured to transmit a charging voltage Vc to the first electrode plate of the charging/discharging capacity 150 in response to the charging control signal Kc, where the charging voltage Vc is greater than the voltage of the ground GND, for example, the voltage of the ground GND is 0V, and the voltage of the charging/discharging voltage Vc may be 6V.

Referring to fig. 2, in the signal generating circuit of the display panel according to the embodiment of the invention, the access unit 120 includes an access transistor Mj, a first end of the access transistor Mj is electrically connected to the constant current source 110, a second end of the access transistor Mj is electrically connected to the first polar plate of the charge/discharge cell 150, and a gate of the access transistor Mj is connected to the first light emitting control signal K1. The voltage holding unit 130 includes at least one holding transistor Mb, a first terminal of which is electrically connected to the ground GND, a second terminal of which is electrically connected to the first electrode plate of the charge/discharge cell 150, and a gate of which is connected to the holding control signal Kb. The charging unit 140 includes a charging transistor Mc, a first end of the charging transistor Mc is connected to the charging voltage Vc, a second end of the charging transistor Mc is electrically connected to the first electrode plate of the charging/discharging capacitor 150, and a gate of the charging transistor Mc is connected to the charging control signal Kc.

Referring to fig. 6, the signal generating circuit of the display panel according to the embodiment of the present invention further includes: and a voltage stabilizing unit 160 electrically connected between the first electrode plate of the charge/discharge cell 150 and the output terminal OUT of the signal generating circuit. Further, the voltage stabilizing unit 160 stabilizes the ramp voltage (i.e., the pulse width control voltage Sweep) output from the output terminal OUT and outputs the stabilized voltage, thereby improving the performance of the signal generating circuit. Referring to fig. 7 specifically, in the signal generating circuit of the display panel provided by the embodiment of the invention, the voltage stabilizing unit includes an operational amplifier, the voltage stabilizing unit 160 includes an operational amplifier OP, the in-phase end+ of the operational amplifier OP is electrically connected to the first polar plate of the charge/discharge cell 150, and the inverting end of the operational amplifier OP and the output end of the operational amplifier OP are electrically connected to the output end OUT of the signal generating circuit.

Referring to fig. 11, a schematic diagram of a structure of another pixel driving circuit according to an embodiment of the present invention is shown, in which the pulse width modulation unit 210 according to an embodiment of the present invention is connected to a first control signal S1, a second control signal S2 and the first light emitting control signal K1, the pulse width modulation unit 210 is used for connecting to a reset voltage Vref in response to the first control signal S1, connecting to a first data voltage D1 in response to the second control signal S2, and connecting to a turn-off voltage Voff in response to the first light emitting control signal K1. The amplitude modulation unit 220 is connected to the first control signal S1 and the second control signal S2, and the amplitude modulation unit 220 is configured to connect to the reset voltage Vref in response to the first control signal S1 and to connect to the second data voltage D2 in response to the second control signal S2.

As shown in fig. 11, the pulse width modulation unit 210 provided in the embodiment of the invention includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1. The first light emitting control unit 231 includes a sixth transistor T6. The amplitude modulation unit 220 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2. And the second light emission control unit 232 includes a tenth transistor T10 and an eleventh transistor T11.

The first end of the first transistor T1 is connected to the reset voltage Vref, the second end of the first transistor T1 is electrically connected to the gate of the second transistor T2, the second end of the fourth transistor T4 and the second end of the first capacitor C1, the gate of the first transistor T1 is connected to the first control signal S1, and the first end of the first capacitor C1 is connected to the pulse width control voltage Sweep, where the pulse width control voltage Sweep is a linearly decreasing voltage. And, the first end of the second transistor T2 is electrically connected to the second end of the third transistor T3 and the second end of the fifth transistor T5, the second end of the second transistor T2 is electrically connected to the first end of the fourth transistor T4 and the first end of the sixth transistor T6, the first end of the third transistor T3 is connected to the first data voltage D1, the gate of the third transistor T3 is connected to the second control signal S2, the first end of the fifth transistor T5 is connected to the off voltage Voff, the gate of the fifth transistor T5 is connected to the first light emitting control signal K1, the second end of the sixth transistor T6 is electrically connected to the gate of the driving transistor T0, and the gate of the sixth transistor T6 is connected to the first light emitting control signal K1.

The first end of the seventh transistor T7 is connected to the reset voltage Vref, the second end of the seventh transistor T7 is electrically connected to the gate of the driving transistor T0, the second end of the eighth transistor T8 and the second end of the second capacitor C2, the gate of the seventh transistor T7 is connected to the first control signal S1, the first end of the eighth transistor T8 is electrically connected to the second end of the driving transistor T0, the gate of the eighth transistor T8 is connected to the second control signal S2, and the first end of the second capacitor C2 is connected to the first power voltage V1. And, the first end of the ninth transistor T9 is connected to the second data voltage D2, the second end of the ninth transistor T9 is electrically connected to the first end of the driving transistor T0, and the gate of the ninth transistor T9 is connected to the second control signal S2.

The first end of the tenth transistor T10 is connected to the first power voltage V1, the second end of the tenth transistor T10 is electrically connected to the first end of the driving transistor T0, and the gate of the tenth transistor T10 is connected to the second light emission control signal K2. And, the first end of the eleventh transistor T11 is electrically connected to the second end of the driving transistor T0, the second end of the eleventh transistor T11 is electrically connected to the first end of the light emitting element 240, the gate of the eleventh transistor T11 is connected to the second light emitting control signal K2, and the second end of the light emitting element 240 is connected to the second power voltage V2, and the first power voltage V1 is greater than the second power voltage V2.

In an embodiment of the present invention, the display panel includes N rows of the pixel driving circuits scanned line by line, the first control signal of the pixel circuit of the i+1th row and the second control signal of the pixel circuit of the i row are the same control signal, N is an integer greater than or equal to 2, and i is a positive integer less than N. And further, the transmission lines corresponding to the control signals can be reduced, and the circuit wiring structure is simplified.

Referring to fig. 12, a timing diagram of a pixel driving circuit according to an embodiment of the present invention includes a signal generating stage S101 and a light emitting controlling stage S102 sequentially performed.

The signal generation stage S101 includes a first sub-signal generation stage S111 and a second sub-signal generation stage S112 that are sequentially performed; wherein the second light emission control signal K2 and the first light emission control signal K1 are at a high level at the signal generation stage S11, and the connected transistors are controlled to be turned off. In the first sub-signal generation stage S111, the first control signal S1 is low and the second control signal S2 is high; at this time, the first control signal S1 controls the first transistor T1 and the seventh transistor T7 to be turned on, and thus, the reset voltage Vref is transmitted to the gate of the second transistor T2 and the gate of the driving transistor T0 to reset the second transistor T2 and the driving transistor T0; and the transistor with the gate connected to the second control signal S2 is turned off at this time.

Then, in the second sub-signal generating stage S112, the first control signal S1 is at a high level, and the second control signal S2 is at a low level; at this time, the second control signal S2 controls the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 to be turned on, the first data voltage D1 is transmitted to the gate of the second transistor T2 through the third transistor T3, the second transistor T2 and the fourth transistor T4, and the writing of the first data voltage D1 is completed, that is, the generating process of the pulse width setting signal is completed; and the second data voltage D2 is transmitted to the gate of the driving transistor T0 through the ninth transistor T9, the driving transistor T0 and the eighth transistor T8, and the writing of the second data voltage D2 is completed, that is, the transmission of the amplitude setting signal to the gate of the driving transistor T0 is completed.

And, the control lighting stage S102 includes a lighting sub-stage S121 and a turning-off sub-stage S122 which are sequentially performed; wherein in the control lighting phase S102, the first control signal S1 and the second control signal S2 are high, and the connected transistors are controlled to be turned off. In the light emitting sub-stage S121, the first light emitting control signal K1 and the second light emitting control signal K2 are both low level, and the fifth transistor T5, the sixth transistor T6, the tenth transistor T10 and the eleventh transistor T11 are controlled to be turned on; at this time, the pulse width control voltage Sweep controls the second transistor T2 to be turned off through the first capacitor C1, and the fifth transistor T5 is turned on, but the off voltage Voff cannot be transmitted to the gate of the driving transistor T0 through the second transistor T2, and at this time, the pulse width setting signal transmitted by the sixth transistor T6 is substantially a floating signal; the tenth transistor T0 and the eleventh transistor T11 are turned on to turn on paths of the first power supply voltage V1 to the second power supply voltage V2, and the driving current generated by the driving transistor T0 is transmitted to the light emitting element 240.

Then in the off sub-stage S122, the light emission control signal K1 and the pulse width control signal K2 are low level, and the corresponding transistors are controlled to be turned on; and, the pulse width control voltage Sweep is a ramp voltage of a linearly decreasing voltage, which decreases to the lowest level and cannot be controlled to be in an on state by maintaining the second transistor T2 to be turned off through the first capacitor C1, and the off voltage Voff is transmitted to the gate of the driving transistor T0 through the fifth transistor T5, the second transistor T2 and the sixth transistor T6 to control the driving transistor T0 to be turned off, and at this time, the driving transistor T0 no longer generates a driving current, so that the light emitting element 240 remains turned off.

Alternatively, in other embodiments of the present invention, when the sub-stage is turned off, the ramp voltage, in which the pulse width control voltage is a linearly decreasing voltage, is reduced to the lowest while the first light emission control signal and the second light emission control signal are converted to the high level, and the five transistor, the sixth transistor, the tenth transistor and the eleventh transistor are controlled to be turned off, thereby completing the extinction control of the light emitting element, which is not particularly limited.

In an embodiment of the present invention, the control signal in the signal generating circuit provided by the present invention may multiplex the control signal in the pixel driving circuit, so as to reduce the signal ports and the corresponding lines. As shown in fig. 13, a schematic diagram of a pixel driving circuit group according to an embodiment of the present invention is illustrated, in which the pixel driving circuit group includes two rows of pixel driving circuits 11 and 12 (only one pixel driving circuit is shown in each row). Wherein the signal generating circuit 100 includes the constant current source 110, the access unit 120, the voltage holding unit 130, the charging unit 140, and the charging/discharging capacity 150, the access unit 120 includes the access transistor Mj, the voltage holding unit 130 includes at least one of the holding transistors, and the charging unit 140 includes the charging transistor Mc.

The pixel driving circuit group includes pixel driving circuits (first row 11 and second row 12) of M rows, wherein the voltage holding unit 130 includes first to m+1th holding transistors (first to third holding transistors Mb1 to Mb 3), the holding control signals include first to m+1th sub-holding control signals (first to third sub-holding control signals Kb1 to Kb 3), and a gate of the jth holding transistor is connected to the jth sub-holding control signal, M is an integer greater than or equal to 1, and j is a positive integer less than or equal to m+1.

When M is equal to 1, or when M is greater than 1 and the pixel driving circuits of M rows are adjacent rows (e.g., the first row 11 and the second row 12 adjacent to each other in fig. 13), provided in the embodiment of the present invention: the k-th sub-holding control signal and the first control signal of the pixel driving circuit of the k-th row are the same signal, the M+1-th sub-holding control signal and the second control signal of the pixel driving circuit of the M-th row are the same signal, and k is a positive integer less than or equal to M. And the charge control signal of the current pixel driving circuit group and the second control signal of the pixel driving circuit of the next pixel driving circuit group and the adjacent first row are the same signal. Specifically, in conjunction with the timing diagram of one pixel driving circuit group shown in fig. 14, S101 is a signal generation stage of the pixel driving circuit of the first row 11, and S101' is a signal generation stage of the pixel driving circuit of the second row 11; the charge control signal Kc of the current pixel driving circuit group provided in the embodiment of the invention is the same signal as the second control signal of the pixel driving circuit of the next pixel driving circuit group and the adjacent first row, so that the charge phase of the charge/discharge cell 150 of the signal generating circuit 100 (i.e., the second sub-signal generating phase of the pixel driving circuit of the next row adjacent to the current pixel driving circuit group) is entered after the pixel driving circuit of the second row 12 completes the operation of the signal generating phase S101'. After the charging of the charge/discharge cell 150 of the input signal generating circuit 100 is completed, the first light emission control signal K1 and the second light emission control signal K2 control all the pixel driving circuits in the first row 11 and the second row 12 to generate driving currents to control the light emitting elements 240 to emit light.

In an embodiment of the present invention, when the pixel driving circuit group includes a plurality of rows of pixel driving circuits, at least one row of pixel driving circuits may be not adjacent to the other rows of pixel circuits, i.e., M is greater than 1 and at least one of the pixel driving circuits in M rows is located in a different row from the other pixel driving circuits. Optionally, when the pixel driving circuit group includes one or more rows of pixel driving circuits and the pixel driving circuits are adjacent or not adjacent, the control signal in the signal generating circuit may also be provided by an independent driving chip, which is not particularly limited in the present invention.

The operation of the different pixel driving circuit groups according to the embodiment of the present invention will be described in further detail with reference to fig. 15 and 16. Referring to fig. 15, a schematic structural diagram of two adjacent pixel driving circuit groups according to an embodiment of the present invention is shown, and fig. 16 is a timing chart of two adjacent pixel driving circuit groups according to an embodiment of the present invention. Two adjacent pixel driving circuit groups are defined as a first pixel driving circuit group 1001 and a second pixel driving circuit group 1002. As shown in fig. 16:

in the stage S1001, the first control signal S1 of the first pixel driving circuit group 1001 is at a low level, and controls the first transistor T1 and the seventh transistor T7 to be turned on, and the reset voltage Vref is transmitted to the gate of the second transistor T2 and the gate of the driving transistor T0 to reset the second transistor T2 and the driving transistor T0. Meanwhile, the first holding transistor Mb1 in the first pixel driving circuit group 1001 is turned on, and electrically connects the ground terminal GND to the first plate of the charge/discharge cell 150.

In the step S1002, the second control signal S1 of the first pixel driving circuit set 1001 is at a low level, and controls the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 to be turned on, and the first data voltage D1 is transmitted to the gate of the second transistor T2 through the third transistor T3, the second transistor T2 and the fourth transistor T4, so as to complete the writing of the first data voltage D1, that is, complete the generation process of the pulse width setting signal; and the second data voltage D2 is transmitted to the gate of the driving transistor T0 through the ninth transistor T9, the driving transistor T0 and the eighth transistor T8, and the writing of the second data voltage D2 is completed, that is, the transmission of the amplitude setting signal to the gate of the driving transistor T0 is completed. The second holding transistor Mb2 in the first pixel driving circuit group 1001 is turned on, and electrically connects the ground terminal GND to the first electrode of the charge/discharge cell 150. Meanwhile, the first control signal S1 of the second pixel driving circuit group 1002 is at a low level, controlling the first transistor T1 and the seventh transistor T7 to be turned on, and the reset voltage Vref is transmitted to the gate of the second transistor T2 and the gate of the driving transistor T0 to reset the second transistor T2 and the driving transistor T0. Meanwhile, the first holding transistor Mb1 in the second pixel driving circuit group 1002 is turned on, and electrically connects the ground terminal GND with the first electrode of the charge/discharge cell 150.

In the stage S1003, the second control signal S1 of the second pixel driving circuit group 1002 is at a low level, and controls the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 to be turned on, the first data voltage D1 is transmitted to the gate of the second transistor T2 through the third transistor T3, the second transistor T2 and the fourth transistor T4, and the writing of the first data voltage D1 is completed, that is, the generation process of the pulse width setting signal is completed; and the second data voltage D2 is transmitted to the gate of the driving transistor T0 through the ninth transistor T9, the driving transistor T0 and the eighth transistor T8, and the writing of the second data voltage D2 is completed, that is, the transmission of the amplitude setting signal to the gate of the driving transistor T0 is completed. The second holding transistor Mb2 in the second pixel driving circuit group 1002 is turned on, and electrically connects the ground terminal GND to the first electrode of the charge/discharge cell 150. Meanwhile, the charge control signal Kc of the first pixel driving circuit group 1001 is low level to control the charge transistor Mc to be turned on, so as to charge the charge/discharge cell 150.

In the stage S1004, the first light emitting control signal K1 and the second light emitting control signal K2 of the first pixel driving circuit group 1001 are at low level, and the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11 and the access transistor Mj are controlled to be turned on, and the signal generating circuit 100 outputs the pulse width control voltage Sweep to control the pulse width modulation unit 210 to generate the pulse width setting signal and transmit to the gate of the driving transistor T0; the tenth transistor T0 and the eleventh transistor T11 are turned on to turn on paths of the first power supply voltage V1 to the second power supply voltage V2, and the driving current generated by the driving transistor T0 is transmitted to the light emitting element 240. Meanwhile, the charge control signal Kc of the second pixel driving circuit group 1002 is low level to control the charge transistor Mc to be turned on, so as to charge the charge/discharge cell 150.

In the stage S1005, the first light emitting control signal K1 and the second light emitting control signal K2 of the second pixel driving circuit group 1002 are low, and the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11 and the access transistor Mj are controlled to be turned on, and the signal generating circuit 100 outputs the pulse width control voltage Sweep to control the pulse width modulation unit 210 to generate the pulse width setting signal and transmit to the gate of the driving transistor T0; the tenth transistor T0 and the eleventh transistor T11 are turned on to turn on paths of the first power supply voltage V1 to the second power supply voltage V2, and the driving current generated by the driving transistor T0 is transmitted to the light emitting element 240.

As can be seen from the above description, according to the technical solution provided by the embodiment of the present invention, the light emitting elements of the first pixel driving circuit group 1001 are turned on at the initial time of the stage S1003, and the light emitting elements of the second pixel driving circuit group 1002 are turned on at the initial time of the stage S1004, so that the light emitting elements 240 in the first pixel driving circuit group 1001 and the light emitting elements 240 in the second pixel driving circuit group 1002 are prevented from being turned on at the same time, and further, the situation that the voltage drop on the signal line shared by the pixel driving circuit groups is too large is avoided, the stability of the pixel driving circuits is improved, and the display effect of the display panel is improved.

Referring to fig. 17, a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention is provided, wherein the pixel driving circuit includes a light emitting element 240 and further includes a light emitting reset unit 250, and the light emitting reset unit 250 is configured to transmit the reset voltage Vref to the light emitting element 240 in response to the second control signal S2. Optionally, the light-emitting reset unit 250 includes a twelfth transistor T12, a first terminal of the twelfth transistor T12 is connected to the reset voltage Vref, a second terminal of the twelfth transistor M12 and a first terminal of the light-emitting element 240, a gate of the twelfth transistor M12 is connected to the second control signal S2, and the second control signal S2 controls the twelfth transistor M12 to transmit the reset voltage Vref to the light-emitting element 240 so as to reset the light-emitting element 240.

Correspondingly, the invention also provides a display device, which comprises the display panel provided by any embodiment.

Referring to fig. 18, a display device 1000 provided in an embodiment of the present invention may be a mobile terminal, where the mobile terminal includes a display panel provided in any one of the above embodiments.

It should be noted that, the display device provided in the embodiment of the present invention may also be a notebook, a tablet computer, a wearable device, etc., which is not particularly limited.

The embodiment of the invention provides a signal generating circuit, a scanning circuit, a display panel and a display device, which comprise the following components: the device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacity; the access unit is used for responding to the generation control signal and communicating the constant current source with the first polar plate of the charge-discharge capacity, the first polar plate of the charge-discharge capacity is electrically connected with the output end of the signal generation circuit, and the second polar plate of the charge-discharge capacity is electrically connected with the grounding end; the voltage holding unit is used for responding to a holding control signal and electrically connecting a grounding terminal with the first polar plate of the charging and discharging capacity; the charging unit is used for responding to a charging control signal and transmitting a charging voltage to the first polar plate of the charging and discharging capacity. The signal generating circuit provided by the embodiment of the invention firstly resets and stabilizes the charge and discharge capacity through the voltage holding unit, then charges the charge and discharge capacity through the charging unit, and finally the access unit communicates the constant current source with the first polar plate of the charge and discharge capacity, and simultaneously acts with the discharge process of the charge and discharge capacity to generate the slope voltage. Therefore, the voltage holding unit provided by the embodiment of the invention can reset and stabilize the charge and discharge capacity, and improves the stability of the signal generating circuit.

In the display panel provided by the embodiment of the invention, the initial time of the pulse width control voltage generated by at least one signal generating circuit in all the signal generating circuits is different from the initial time of the pulse width control voltage generated by the other signal generating circuits, so that all the pixel driving circuits of the display panel are not different from the initial time to light the light emitting elements, the condition that the voltage drop is overlarge to the signal lines connected with the pixel driving circuits when all the light emitting elements are lighted at the same initial time is avoided, the stability of the pixel driving circuits is further improved, and the display effect of the display panel is improved.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A signal generating circuit, comprising: the device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacity;

the charging unit is used for responding to a charging control signal and transmitting a charging voltage to the first polar plate of the charging and discharging capacity;

the output end of the signal generating circuit is used for outputting a slope voltage.

2. The signal generating circuit according to claim 1, wherein the access unit includes an access transistor, a first end of the access transistor is electrically connected to the constant current source, a second end of the access transistor is electrically connected to the first electrode plate of the charge/discharge cell, and a gate of the access transistor is connected to the generation control signal;

3. The signal generating circuit of claim 1, wherein the signal generating circuit further comprises: and the voltage stabilizing unit is electrically connected between the first polar plate of the charge-discharge capacity and the output end of the signal generating circuit.

4. The signal generating circuit according to claim 3, wherein the voltage stabilizing unit comprises an operational amplifier, a non-inverting terminal of the operational amplifier is electrically connected to the first electrode plate of the charge/discharge cell, and an inverting terminal of the operational amplifier and an output terminal of the operational amplifier are electrically connected to the output terminal of the signal generating circuit.

5. A scanning circuit, the scanning circuit comprising: a first signal generating circuit to an nth signal generating circuit, any one of the signal generating circuits being the signal generating circuit according to any one of claims 1 to 4, N being an integer greater than or equal to 2;

6. A display panel, comprising:

the pixel driving circuit comprises a pulse width modulation unit, a first light emitting control unit and a driving transistor; the pulse width modulation unit is used for outputting a pulse width setting signal by referring to a pulse width control voltage; the first light emitting control unit is used for responding to a first light emitting control signal and transmitting the pulse width setting signal to the grid electrode of the driving transistor;

7. The display panel according to claim 6, wherein the signal generating circuit comprises: the device comprises a constant current source, an access unit, a voltage holding unit, a charging unit and a charging and discharging capacity;

8. The display panel according to claim 7, wherein the access unit includes an access transistor, a first end of the access transistor is electrically connected to the constant current source, a second end of the access transistor is electrically connected to the first electrode plate of the charge/discharge cell, and a gate of the access transistor is connected to the first light emission control signal;

9. The display panel of claim 7, wherein the signal generation circuit further comprises: and the voltage stabilizing unit is electrically connected between the first polar plate of the charge-discharge capacity and the output end of the signal generating circuit.

10. The display panel according to claim 9, wherein the voltage stabilizing unit includes an operational amplifier, a non-inverting terminal of the operational amplifier is electrically connected to the first electrode plate of the charge/discharge cell, and an inverting terminal of the operational amplifier and an output terminal of the operational amplifier are electrically connected to the output terminal of the signal generating circuit.

11. The display panel according to any one of claims 6 to 10, wherein the pulse width modulation unit is connected to a first control signal, a second control signal, and the first light emission control signal, the pulse width modulation unit is configured to connect to a reset voltage in response to the first control signal, to connect to a first data voltage in response to the second control signal, and to connect to a turn-off voltage in response to the first light emission control signal;

12. The display panel according to claim 11, wherein the signal generating circuit includes a constant current source, an access unit, a voltage holding unit, a charging unit, and a charging and discharging capacity, the access unit includes an access transistor, the voltage holding unit includes at least one holding transistor, and the charging unit includes a charging transistor:

13. The display panel of claim 12, wherein when M is equal to 1, or when M is greater than 1 and the pixel driving circuits of M rows are adjacent rows:

14. The display panel of claim 12, wherein M is greater than 1 and at least one of the M rows of pixel drive circuits is located in a different row than the remaining pixel drive circuits.

15. The display panel according to claim 11, wherein the pixel driving circuit includes a light emitting element and further includes a light emission reset unit for transmitting the reset voltage to the light emitting element in response to the second control signal.

16. A display device comprising the display panel of any one of claims 6-15.