CN114295955A - Chip screening method and device and chip screening equipment - Google Patents

Abstract

The present application provides a chip screening method, device, and screening device, the method includes: performing board-level testing on a plurality of sample chips, which will work normally under extreme temperatures and have a junction temperature value within a first predetermined range. The sample chip is determined as the first target chip, the quiescent current value and oscillation frequency value of a plurality of first target chips are obtained, and the quiescent current threshold value and the oscillation frequency threshold value are determined; The first target chip whose junction temperature rise value is within the second predetermined range is determined as the second target chip; the board-level test is performed on the second target chip, and the second target chip that works normally under the extreme temperature is determined as the third target chip , obtain the junction temperature rise value of the third target chip in the FT test, and obtain the junction temperature rise threshold; screen the chip to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold to solve the power consumption of the screen. Low constraints lead to low chip yield issues.

Description

Chip sieving method, device and sieving equipment

technical field

The present application relates to the technical field of chip testing, and in particular, to a chip screening method, device, and screening equipment.

Background technique

As the power consumption problem faced by chips becomes more and more serious, excessive chip power consumption is one of the main reasons for the loss of chip mass production yield. Between different wafers and different batches, the parameters of MOSFETs vary widely due to external factors such as doping, etching, and temperature. In order to reduce the difficulty of design, it is necessary to limit the device performance to a certain range and scrap it. For chips beyond this range, the sieves mainly limit power consumption from two aspects during the mass production of chips, one of which is the upper limit of the quiescent current at room temperature, and the other is the OSC oscillation circuit loop integrated on the chip to monitor the speed of the process. Based on these two tests alone, there will be some chips with high temperature inversion near the power consumption boundary value, that is, some chips within the power consumption limit have abnormal high temperature power consumption. The specific manifestation is that the junction temperature of the chip exceeds the preset value during operation. The value or the upper limit of the chip junction temperature specified by the manufacturer, some chips outside the power consumption limit perform normally at high temperature. In order to prevent chips with high temperature inversion within the power consumption limit from entering the market, it is necessary to continue to reduce the power consumption limit, which will cause a huge loss to the yield of mass-produced chips.

Therefore, a new chip screening method is urgently needed to solve the problem of low chip yield due to low power consumption limitation in the process of mass production of chips.

SUMMARY OF THE INVENTION

The main purpose of the present application is to provide a chip screening method, device and screening equipment, so as to solve the problem of low chip yield due to low power consumption limitation of the screening method in the prior art.

According to an aspect of the embodiments of the present invention, a method for screening chips is provided, the screening method includes: performing a board-level test on a plurality of sample chips, and the ambient temperature of the board-level test is a limit temperature, which will satisfy the The sample chip under the first predetermined condition is determined as the first target chip, a plurality of static current values and oscillation frequency values of the first target chips are obtained, and the static current threshold value and the oscillation frequency threshold value are determined, and the limit temperature is set as the limit temperature. The highest ambient temperature of the application scenario of the sample chip, the first predetermined condition is that the test chip works normally and the junction temperature value is within the first predetermined range; FT test on the first target chip will satisfy the second predetermined condition The first target chip is determined as the second target chip, and the second predetermined condition is that the junction temperature rise value of the test chip within a predetermined time is within the second predetermined range; the board-level test is performed on the second target chip , the ambient temperature of the board-level test is the limit temperature, the second target chip that satisfies the first predetermined condition and the second predetermined condition is determined as the third target chip, and the third target chip is obtained at The junction temperature rise value in the FT test determines the junction temperature rise threshold; according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, the chips to be tested are screened, and the chips to be tested are screened. The same type of chip as the sample chip.

Optionally, before the FT test is performed on the first target chip, and the first target chip that satisfies the second predetermined condition is determined as the second target chip, the method further includes: performing an FT test on a plurality of the first target chips. The target chip is tested at the board level, the ambient temperature of the board level test is the limit temperature, and when the junction temperature value of the first target chip is detected as the predetermined temperature, the first target chip is at the predetermined time. The first junction temperature rise value is obtained; the second predetermined range is determined according to the first junction temperature rise value.

Optionally, performing an FT test on the first target chip, and determining the first target chip that satisfies the second predetermined condition as the second target chip, including: setting the test temperature to a set temperature and a test excitation to a set temperature In the case of test excitation, the junction temperature rise value of the first target chip at the predetermined time is detected, and the second junction temperature rise value is obtained, and the test temperature is the temperature of the FT test on the first target chip. The ambient temperature, the test excitation is the excitation for performing the FT test on the first target chip; the set temperature and the set test excitation are adjusted until the second target chip is obtained.

Optionally, sifting the chip to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, including: in the case that the ambient temperature is a production temperature, obtaining the to-be-tested chip. The quiescent current value of the chip and the oscillating frequency value of the oscillation circuit of the chip to be tested are obtained to obtain the target quiescent current value and the target oscillating frequency value, and the production temperature is the temperature of the environment where the chip to be tested is produced; In the case that the junction temperature value of the chip to be tested is the predetermined temperature, the junction temperature rise value of the chip to be tested within the predetermined time is detected to obtain a target junction temperature rise value; When the value is less than or equal to the quiescent current threshold, the target oscillation frequency value is less than or equal to the oscillation frequency threshold, and the target junction temperature rise value is less than or equal to the junction temperature rise threshold, it is determined that the The chip to be tested is qualified.

Optionally, the predetermined temperature is between 110°C and 120°C.

Optionally, the predetermined time is greater than or equal to 100ms.

Optionally, the first predetermined range is 115°C to 125°C.

Optionally, the minimum value of the second predetermined range is the first temperature rise value, the maximum value of the second predetermined range is the second temperature rise value, and the first temperature rise value is the first junction temperature rise value. 70% to 90%, and the second temperature rise value is 110% to 130% of the first junction temperature rise value.

According to another aspect of the embodiments of the present invention, there is provided a chip screening device, the device includes: a first testing unit for performing board-level testing on a plurality of sample chips, and the ambient temperature of the board-level testing is In order to limit the temperature, the sample chip that satisfies the first predetermined condition is determined as the first target chip, the quiescent current value and oscillation frequency value of a plurality of the first target chips are obtained, and the quiescent current threshold value and the oscillation frequency threshold value are determined, The limit temperature is the highest ambient temperature of the application scenario of the sample chip, the first predetermined condition is that the test chip works normally and the junction temperature value is within the first predetermined range; the second test unit is used for A target chip is subjected to an FT test, and the first target chip that satisfies a second predetermined condition is determined as the second target chip, and the second predetermined condition is that the junction temperature rise value of the test chip within a predetermined time is within a second predetermined range inside; a third test unit, used to perform board-level testing on the second target chip, the ambient temperature of the board-level testing is an extreme temperature, and will satisfy all the first predetermined conditions and the second predetermined conditions. The second target chip is determined as the third target chip, the junction temperature rise value of the third target chip in the FT test is obtained, and the junction temperature rise threshold value is determined; the judgment unit is used for according to the static current threshold value, The oscillation frequency threshold and the junction temperature rise threshold are screened for the chip to be tested, and the chip to be tested and the sample chip are chips of the same type.

According to yet another aspect of the embodiments of the present invention, a screening device is also provided, the screening device includes a processor and a memory, and the processor is used for running a program, wherein, when the program is running, any one of the foregoing is executed The sieve method.

In the embodiment of the present invention, the above-mentioned chip sifting method performs board-level testing on a plurality of sample chips under the extreme temperature, and selects the chips that can work normally under the extreme temperature and whose junction temperature value is within the first predetermined range, that is, For the first target chip, obtain the static current value and oscillation frequency value of multiple first target chips, and obtain the static current threshold value and the oscillation frequency threshold value; then perform FT test on the multiple first target chips, and select the The chip whose junction temperature rise value is within the second predetermined range is determined as the second target chip; then the board-level test under the extreme temperature is performed on the second target chip, and it will work normally under the extreme temperature, and the junction temperature value is in the first The second target chip that is within the predetermined range and the junction temperature rise value within the predetermined time is within the second predetermined range is determined as the third target chip, and the junction temperature rise value of the third target chip in the above-mentioned FT test is obtained. Junction temperature temperature rise threshold; sieving through three screen conditions: static current threshold, oscillation frequency threshold and junction temperature temperature rise threshold, can avoid high temperature reversal phenomenon of chips that meet the power consumption limit conditions, so it is not necessary to reduce power consumption Limitation, that is, the quiescent current threshold and the oscillation frequency threshold do not need to be lowered, thereby improving the chip yield and solving the problem of low chip yield caused by low power consumption limitation of the screening method in the prior art.

Description of drawings

The accompanying drawings that form a part of the present application are used to provide further understanding of the present application, and the schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute improper limitations on the present application. In the attached image:

1 shows a flowchart of a method for sieving a chip according to an embodiment of the present application;

FIG. 2 shows a schematic diagram of a screen device of a chip according to an embodiment of the present application.

Detailed ways

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order to make those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only The embodiments are part of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the scope of protection of the present application.

It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the application described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element or "connected" to the other element through a third element.

For the convenience of description, some nouns or terms involved in the embodiments of the present application are described below:

Board-level testing is mainly used in functional testing. It uses PCB board + chip to build a "simulated" chip working environment, pulls out the interface of the chip, detects the function of the chip, or checks whether the chip is normal in various harsh environments. Work. The equipment that needs to be applied is mainly instrumentation, and the main thing that needs to be made is the EVB evaluation board.

CP test: English full name is Circuit Probing\Chip Probing, also known as wafer test, the test object is for each die in the whole wafer, the purpose is to ensure that each die in the whole wafer can basically Meeting device characteristics or design specifications, usually including verification of voltage, current, timing, and function.

FT test: The full name in English is Final Test, which is the last interception before the chip leaves the factory. The test object is for the packaged chip. The FT test is generally divided into two steps: 1) automatic test equipment; 2) system level test.

As mentioned in the background art, the high temperature inversion phenomenon occurs within the power consumption limit in the screening method in the prior art, which leads to the need to reduce the power consumption limit, resulting in low chip yield. In order to solve the above problems, the present application provides A chip screening method, device and screening equipment.

According to an embodiment of the present application, a method for sieving a chip is provided.

FIG. 1 is a flowchart of a method for sieving a chip according to an embodiment of the present application. As shown in Figure 1, the method includes the following steps:

In step S101, board-level testing is performed on a plurality of sample chips. The ambient temperature of the board-level testing is an extreme temperature, and the sample chips that meet the first predetermined condition are determined as the first target chips, and the data of the plurality of first target chips are obtained. The quiescent current value and the oscillation frequency value, and determine the quiescent current threshold value and the oscillation frequency threshold value, the above-mentioned limit temperature is the highest ambient temperature of the application scenario of the above-mentioned sample chip, and the above-mentioned first predetermined condition is that the test chip works normally and the junction temperature value is within the first within the predetermined range;

Step S102, FT test is performed on the above-mentioned first target chip, and the above-mentioned first target chip that satisfies the second predetermined condition is determined as the second target chip, and the above-mentioned second predetermined condition is that the junction temperature rise value of the test chip within a predetermined time is within within the second predetermined range;

Step S103, performing a board-level test on the second target chip, the ambient temperature of the board-level test being the limit temperature, and determining the second target chip that satisfies the first predetermined condition and the second predetermined condition as the third target chip , obtain the junction temperature rise value of the third target chip in the above FT test, and determine the junction temperature rise threshold;

In step S104, the chip to be tested is screened according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold. The chip to be tested and the sample chip are of the same type.

The screening method performs board-level testing on a plurality of sample chips at an extreme temperature, and selects a chip that can work normally at the extreme temperature and whose junction temperature value is within a first predetermined range, that is, the first target chip, and obtains a plurality of chips. The quiescent current value and oscillation frequency value of the first target chip are obtained to obtain the quiescent current threshold value and the oscillation frequency threshold value; then FT test is performed on a plurality of first target chips, and the junction temperature rise value within a predetermined time is selected within the second predetermined range The chip inside is determined as the second target chip; then the board-level test under the extreme temperature is performed on the second target chip, and it will work normally under the extreme temperature, and the junction temperature value is within the first predetermined range and within the predetermined time. The second target chip whose junction temperature rise value is within the second predetermined range is determined as the third target chip, and the junction temperature rise value of the third target chip in the above-mentioned FT test is obtained to obtain the junction temperature rise threshold; The threshold value, the oscillation frequency threshold value and the junction temperature rise threshold value are screened under three screen conditions, so as to avoid the high temperature inversion phenomenon of the chips that meet the power consumption limit conditions, so that the power consumption limit does not need to be reduced, that is, the quiescent current threshold value and the quiescent current threshold value are not reduced. The oscillation frequency threshold is increased, thereby improving the chip yield, and solving the problem of low chip yield caused by the low power consumption limitation of the screening method in the prior art.

Specifically, because the quiescent current value and the oscillation frequency value are obtained in the CP test stage, after obtaining the first target chip in the board-level test under extreme temperature, the quiescent current value and oscillation frequency of these first target chips can be directly read through OTP. value, the quiescent current threshold value and the oscillating frequency threshold value can be determined according to the quiescent current value and oscillating frequency value of these first target chips. In a specific embodiment, when there are multiple first target chips, the quiescent current threshold may be the quiescent current value of any first target chip, or the quiescent current value of multiple first target chips The above-mentioned oscillation frequency threshold may be the oscillation frequency value of the oscillation circuit of any one first target chip, or may be the average or maximum value of the oscillation frequency values of the oscillation circuits of a plurality of first target chips, In the case where there are multiple third target chips, the junction temperature temperature rise threshold may be the junction temperature rise value of any third target chip in the FT test, or may be the junction temperature rise value of a plurality of third target chips in the FT test The average or maximum value of the junction temperature rise.

Preferably, the quiescent current threshold value is the maximum value of the quiescent current values of the plurality of first target chips, the oscillation frequency threshold value is the maximum value of the oscillation frequency values of the oscillating circuits of the plurality of the first target chips, and the junction temperature The rise threshold is the maximum value of the junction temperature rise values of the plurality of third target chips in the FT test. Specifically, there are multiple first target chips and third target chips, the quiescent current threshold and the oscillation frequency threshold both take the maximum value of the quiescent current and oscillation frequency of the multiple first target chips, and the junction temperature rises. The threshold value is the maximum value of the junction temperature rise value of the plurality of third target chips in the FT test, so as to further improve the chip yield.

It should also be noted that the steps shown in the flowcharts of the accompanying drawings may be performed in a computer system, such as a set of computer-executable instructions, and that although a logical sequence is shown in the flowcharts, in some cases , steps shown or described may be performed in an order different from that herein.

In an embodiment of the present application, before the FT test is performed on the first target chip, and the first target chip that satisfies the second predetermined condition is determined as the second target chip, the method further includes: performing an FT test on a plurality of the first target chips. A target chip is subjected to a board-level test, the ambient temperature of the board-level test is the limit temperature, and when the junction temperature of the first target chip is detected as the predetermined temperature, the junction temperature of the first target chip within the predetermined time The temperature rise value is obtained to obtain the first junction temperature rise value; the second predetermined range is determined according to the first junction temperature rise value.

Specifically, the junction temperature rise value of the first target chip within the predetermined time period is detected to obtain a first junction temperature rise value, and an appropriate second predetermined range is determined by taking the first junction temperature rise value as a standard.

In an embodiment of the present application, the FT test is performed on the first target chip, and the first target chip that satisfies the second predetermined condition is determined as the second target chip, including: the test temperature is a set temperature and a test excitation In the case of setting the test excitation, the junction temperature rise value of the first target chip at the predetermined time is detected, and the second junction temperature rise value is obtained, and the test temperature is the ambient temperature for performing the FT test on the first target chip. , the above-mentioned test excitation is an excitation for performing the above-mentioned FT test on the above-mentioned first target chip; the above-mentioned set temperature and the above-mentioned set test excitation are adjusted until the above-mentioned second target chip is obtained.

Specifically, by continuously adjusting the set test temperature and set test excitation, the cyclic calibration method makes the second junction temperature rise value continuously approach the second predetermined range, until the second junction temperature rise value is screened out to be in the second predetermined range The chip, that is, the second target chip, the test excitation is the test information input to the chip to be tested in the FT test, and different test information can make the chip run in different working states.

In an embodiment of the present application, sieving the chip to be tested according to the above-mentioned static current threshold, the above-mentioned oscillation frequency threshold and the above-mentioned junction temperature rise threshold includes: in the case that the above-mentioned ambient temperature is the production temperature, obtaining the above-mentioned to-be-tested temperature The quiescent current value of the chip and the oscillating frequency value of the oscillation circuit of the above-mentioned chip to be tested are obtained to obtain the target quiescent current value and the target oscillating frequency value, and the above-mentioned production temperature is the temperature of the environment in which the above-mentioned chip to be tested is produced; When the junction temperature value of the test chip is the above predetermined temperature, the junction temperature rise value of the chip to be tested within the above predetermined time is detected to obtain the target junction temperature rise value; when the above target static current value is less than or equal to the above static current threshold value . When the above target oscillation frequency value is less than or equal to the above-mentioned oscillation frequency threshold value and the above-mentioned target junction temperature rise value is less than or equal to the above-mentioned junction temperature temperature rise threshold value, it is determined that the above-mentioned chip to be tested is qualified.

Specifically, the quiescent current of the chip to be tested, the oscillation frequency of the oscillation circuit of the above-mentioned chip to be tested, and the temperature rise of the junction temperature within the predetermined time at a predetermined temperature are detected to obtain the target quiescent current, target oscillation frequency and target junction temperature The value is increased, and the screen is screened according to the three screen conditions of static current threshold, oscillation frequency threshold and junction temperature rise threshold, that is, when the chip to be tested satisfies that the above target static current is less than or equal to the above static current threshold, the above target oscillation frequency is less than or equal to If the above-mentioned oscillation frequency threshold and the above-mentioned target junction temperature rise value are less than or equal to the above-mentioned junction temperature rise threshold, the chips to be tested are qualified, and the high temperature inversion phenomenon of the chips that meet the power consumption limit conditions can be avoided, so it is not necessary to reduce the power consumption limit , that is, without lowering the quiescent current threshold and the oscillation frequency threshold, thereby improving the chip yield.

In an embodiment of the present application, the predetermined temperature is between 110°C and 120°C.

Specifically, the upper limit of the junction temperature that the chip can work normally is 125°C, and the above predetermined temperature is set within the above range, and a certain junction temperature rise space is reserved to avoid damage to the chip when the junction temperature exceeds the upper limit in the process of detecting the junction temperature rise. , and the high temperature inversion phenomenon may occur after the chip junction temperature value reaches a predetermined temperature, preferably, the predetermined temperature can be set to 110°C. The second predetermined range is set according to the junction temperature rise value when the chip junction temperature value reaches the predetermined time of the predetermined temperature detection, so as to screen out the second target chip according to the second predetermined range, so that the junction temperature rise obtained by detecting the second target chip The threshold value can screen out chips that may have high temperature inversion, and ensure the quality of the chips.

In an embodiment of the present application, the predetermined time is greater than or equal to 100 ms.

Specifically, because the FT test is expensive, in order to save costs, the predetermined time can be set to 100ms. Of course, the longer the predetermined time is, the smaller the error of the obtained junction temperature rise value is, and the predetermined time can be greater than 100ms to further improve the screen. yield rate.

In an embodiment of the present application, the above-mentioned first predetermined range is 115°C to 125°C.

Specifically, since the upper limit of the junction temperature for the normal operation of the chip is 125°C, the first predetermined range is set to 115°C to 125°C, and the junction temperature that can work normally at the extreme temperature can be screened out and the junction temperature is at the above-mentioned first predetermined range. The sample chip within the predetermined range is used as the first target chip, which improves the accuracy of the measurement of the junction temperature temperature rise threshold and further improves the yield.

In an embodiment of the present application, the minimum value of the second predetermined range is the first temperature rise value, the maximum value of the second predetermined range is the second temperature rise value, and the first temperature rise value is the first junction temperature rise value. 70%-90% of the above-mentioned second temperature rise value is between 110%-130% of the above-mentioned first junction temperature rise value.

Specifically, the first temperature rise value and the second temperature rise value can be selected according to actual conditions. Preferably, the first temperature rise value is set to 80% of the first junction temperature rise value, and the second temperature rise value is set to the third A junction temperature rise of 120% is because the upper limit of the junction temperature for the chip to work normally is 125°C, and the predetermined temperature is set between 110°C and 120°C. Too high and too low may cause the test to fail. Therefore, the second predetermined range is set to be closer to the first junction temperature rise value, so as to improve the yield rate of chip mass production.

The embodiment of the present application further provides a chip screening device. It should be noted that the chip screening device of the embodiment of the present application can be used to perform the chip screening method provided by the embodiment of the present application. The sieve device for chips provided in the embodiments of the present application will be introduced below.

FIG. 2 is a schematic diagram of a screen device of a chip according to an embodiment of the present application. As shown in Figure 2, the device includes:

The first testing unit 10 is configured to perform board-level testing on a plurality of sample chips. The ambient temperature of the board-level testing is an extreme temperature, and the sample chip that meets the first predetermined condition is determined as the first target chip, and a plurality of the above-mentioned sample chips are obtained. The quiescent current value and oscillation frequency value of the first target chip, and determine the quiescent current threshold value and oscillation frequency threshold value, the above-mentioned limit temperature is the highest ambient temperature of the application scene of the above-mentioned sample chip, and the above-mentioned first predetermined condition is that the test chip is working normally and junction. The temperature value is within the first predetermined range;

The second testing unit 20 is configured to perform an FT test on the first target chip, and determine the first target chip that satisfies a second predetermined condition as the second target chip, where the second predetermined condition is the test chip within a predetermined time. The junction temperature rise value is within the second predetermined range;

The third testing unit 30 is configured to perform a board-level test on the second target chip. The ambient temperature of the board-level test is an extreme temperature, and the second target chip that satisfies the first predetermined condition and the second predetermined condition is determined. For the third target chip, obtain the junction temperature rise value of the third target chip in the above-mentioned FT test, and determine the junction temperature rise threshold;

The judging unit 40 is configured to screen the chip to be tested according to the static current threshold, the oscillation frequency threshold and the junction temperature rise threshold, and the chip to be tested and the sample chip are of the same type.

The screening device performs board-level testing on multiple sample chips under extreme temperature, selects chips that can work normally under extreme temperature and whose junction temperature value is within a first predetermined range, that is, the first target chip, and obtains a plurality of chips. The quiescent current value and oscillation frequency value of the first target chip are obtained to obtain the quiescent current threshold value and the oscillation frequency threshold value; then FT test is performed on a plurality of first target chips, and the junction temperature rise value within a predetermined time is selected within the second predetermined range The chip inside is determined as the second target chip; then the board-level test under the extreme temperature is performed on the second target chip, and it will work normally under the extreme temperature, and the junction temperature value is within the first predetermined range and within the predetermined time. The second target chip whose junction temperature rise value is within the second predetermined range is determined as the third target chip, and the junction temperature rise value of the third target chip in the above-mentioned FT test is obtained to obtain the junction temperature rise threshold; The threshold value, the oscillation frequency threshold value and the junction temperature rise threshold value are screened under three screen conditions, so as to avoid the high temperature inversion phenomenon of the chips that meet the power consumption limit conditions, so that the power consumption limit does not need to be reduced, that is, the quiescent current threshold value and the quiescent current threshold value are not reduced. The oscillation frequency threshold is increased, thereby improving the chip yield, and solving the problem of low chip yield caused by the low power consumption limitation of the screening method in the prior art.

In an embodiment of the present application, the above-mentioned apparatus further includes a fourth test unit, and the above-mentioned fourth test unit includes a first detection module and a first determination module.

The first detection module is used to perform board-level testing on a plurality of the first target chips, the ambient temperature of the board-level testing is the limit temperature, and when the junction temperature of the detected first target chips is the predetermined temperature, the first detection module A first junction temperature rise value is obtained from the junction temperature rise value of a target chip within the predetermined time period; the first determination module is configured to determine the second predetermined range according to the first junction temperature rise value.

In an embodiment of the present application, the above-mentioned second test unit further includes a second detection module and an adjustment module.

The second detection module is configured to detect the junction temperature rise value of the first target chip at the predetermined time when the test temperature is the set temperature and the test excitation is the set test excitation, and obtain the second junction temperature rise value, the above The test temperature is the ambient temperature for performing the above-mentioned FT test on the above-mentioned first target chip, and the above-mentioned test excitation is the excitation for performing the above-mentioned FT test on the above-mentioned first target chip; the adjustment module is used to adjust the above-mentioned set temperature and the above-mentioned set test excitation, until the above-mentioned second target chip is obtained.

In an embodiment of the present application, the above judgment unit includes a third detection module, a fourth detection module, and a second determination module.

The third detection module is used to obtain the static current value of the chip to be tested and the oscillation frequency value of the oscillation circuit of the chip to be tested, and obtain the target static current value and the target oscillation frequency value when the ambient temperature is the production temperature, The above-mentioned production temperature is the temperature of the environment in which the above-mentioned chip to be tested is produced.

The fourth detection module is configured to detect the junction temperature rise value of the chip to be tested within the predetermined time when the junction temperature value of the chip to be tested is the predetermined temperature to obtain a target junction temperature rise value.

The second determination module is configured to be established when the target static current value is less than or equal to the static current threshold value, the target oscillation frequency value is less than or equal to the oscillation frequency threshold value, and the target junction temperature rise value is less than or equal to the junction temperature rise threshold value. In the case of , it is determined that the above-mentioned chips to be tested are qualified.

In an embodiment of the present application, the predetermined temperature is between 110°C and 120°C.

In an embodiment of the present application, the predetermined time is greater than or equal to 100 ms.

In an embodiment of the present application, the minimum value of the second predetermined range is the first temperature rise value, the maximum value of the second predetermined range is the second temperature rise value, and the first temperature rise value is the first junction temperature rise value. 70%-90% of the above-mentioned second temperature rise value is between 110%-130% of the above-mentioned first junction temperature rise value.

In an embodiment of the present application, the above-mentioned first predetermined range is 115°C to 125°C.

The sieve device of the above-mentioned chip includes a processor and a memory, and the above-mentioned first test unit 10, second test unit 20, third test unit 30 and judgment unit 40 are all stored in the memory as program units, and are executed by the processor and stored in the memory. The above program units in the memory implement the corresponding functions.

The processor includes a kernel, and the kernel calls the corresponding program unit from the memory. One or more kernels can be set, and the problem of low chip yield caused by low power consumption limitation of the screening method in the prior art can be solved by adjusting kernel parameters.

Memory may include non-persistent memory in computer readable media, random access memory (RAM) and/or non-volatile memory, such as read only memory (ROM) or flash memory (flash RAM), the memory including at least one memory chip.

The embodiment of the present invention provides a screening device, which includes a processor, a memory, and a program stored in the memory and running on the processor. When the processor executes the program, any one of the above screening methods is implemented:

The sieve equipment in this article can be electronic equipment such as servers, PCs, PADs, and mobile phones.

In the above-mentioned embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In order to make the technical solutions and technical effects of the present application more clear to those skilled in the art, the following description will be combined with specific embodiments.

Example 1

The chip to be tested is required to work normally below 50°C, that is, the limit temperature is 50°C. The sieving method of the chip in this embodiment includes the following steps:

Step 1: Perform board-level testing on multiple sample chips at an ambient temperature of 50°C. The sample chips that can work normally at a temperature of 50°C and whose junction temperature is within the first predetermined range are recorded as the first. For the target chip, obtain static current values and oscillation frequency values of a plurality of first target chips, take the maximum value of the plurality of static current values as the static current threshold value, and take the maximum value of the plurality of oscillation frequency values as the oscillation frequency threshold value;

Step 2: monitor the temperature sensor inside the chip by the CPU, test the junction temperature rise value of the first target chip at a predetermined temperature of 110°C and a predetermined time of 100ms, and obtain the first junction temperature rise value;

Step 3: perform an FT test on the first target chip, and detect the junction temperature rise value of the first target chip within a predetermined time of 100ms through the temperature sensor inside the chip in the FT test to obtain a second junction temperature rise value;

Step 4: change the set temperature of the FT test and set the test excitation, so that the temperature rise value of the second junction temperature is close to the temperature rise value of the first junction temperature;

Step 5: Repeat Step 4 until the first target chip whose second junction temperature rise value is between 80% and 120% of the above-mentioned first junction temperature rise value is selected to obtain a second target chip;

Step 6: Perform board-level testing on multiple second target chips at an ambient temperature of 50°C, and detect the junction temperature value and the third junction temperature rise value within a predetermined time of 100ms. The second target chip with normal operation, the junction temperature value is within the first predetermined range, and the third junction temperature rise value is between 80% and 120% of the first junction temperature rise value is recorded as the third target chip, and a plurality of The second junction temperature rise value of the third target chip, the maximum value is the junction temperature rise threshold;

Step 7: Finally, the above-mentioned static current threshold, the above-mentioned oscillation frequency threshold and the above-mentioned junction temperature rise threshold are used as the upper limit of the screening conditions, and the to-be-tested chip is screened.

In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the above-mentioned units may be a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of units or modules, and may be in electrical or other forms.

The units described above as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

If the above-mentioned integrated units are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable computer-readable storage medium. Based on such understanding, the technical solution of the present invention essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a computer-readable The storage medium includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the above-mentioned methods of the various embodiments of the present invention. The aforementioned computer-readable storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other various programs that can store programs medium of code.

From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

The sieving method, sieving device, and sieving device of the present application perform board-level tests on multiple sample chips, and select sample chips that can work normally under the maximum ambient temperature of the application scene through the extreme temperature test and have a junction temperature value in the The chip within the first predetermined range is the first target chip, and the quiescent current and the corresponding oscillation frequency under the extreme temperature of the first target chip are detected, and the quiescent current threshold and the oscillation frequency threshold are obtained, and then the FT is performed on the first target chip. Test, select the first target chip whose junction temperature rise value is within the second predetermined range within the predetermined time during the above-mentioned FT test process, obtain the second target chip, and perform the board-level test on the above-mentioned second target chip. In the case where the junction temperature value of the second target chip is a predetermined temperature, the junction temperature rise value of the second target chip within the predetermined time period can be detected to obtain the junction temperature rise threshold value. Through the static current threshold value and the oscillation frequency threshold value Screening with the three screening conditions of the junction temperature temperature rise threshold can avoid the high temperature inversion phenomenon of the chips that meet the power consumption constraints, so that the power consumption limit does not need to be reduced, that is, the quiescent current threshold and the oscillation frequency threshold do not need to be reduced. The chip yield is improved, and the phenomenon of high temperature reversal occurring within the power consumption limit range in the screening method in the prior art is solved, resulting in the need to reduce the power consumption limit and the problem of low chip yield.

The above are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (10)

1. A method of screening a chip, the method comprising:

performing board-level test on a plurality of sample chips, wherein the environmental temperature of the board-level test is a limit temperature, determining the sample chip meeting a first preset condition as a first target chip, acquiring static current values and oscillation frequency values of the plurality of first target chips, and determining a static current threshold value and an oscillation frequency threshold value, wherein the limit temperature is the highest environmental temperature of an application scene of the sample chip, and the first preset condition is that the test chip normally works and a junction temperature value is within a first preset range;

performing an FT test on the first target chip, and determining the first target chip meeting a second preset condition as a second target chip, wherein the second preset condition is that a junction temperature rise value of the test chip in a preset time is in a second preset range;

performing board level test on the second target chip, wherein the environmental temperature of the board level test is the limit temperature, determining the second target chip meeting the first preset condition and the second preset condition as a third target chip, acquiring a junction temperature rise value of the third target chip in the FT test, and determining a junction temperature rise threshold;

screening a chip to be tested according to the quiescent current threshold, the oscillation frequency threshold and the junction temperature rise threshold, wherein the chip to be tested and the sample chip are chips with the same model.

2. The method of claim 1, wherein before performing an FT test on the first target chip to determine the first target chip satisfying a second predetermined condition as a second target chip, the method further comprises:

performing board-level test on the plurality of first target chips, wherein the environment temperature of the board-level test is a limit temperature, and detecting a junction temperature rise value of the first target chip within the preset time under the condition that the junction temperature value of the first target chip is a preset temperature to obtain a first junction temperature rise value;

and determining the second preset range according to the first temperature rise value.

3. The method of claim 1, wherein performing an FT test on the first target chip, and determining the first target chip satisfying a second predetermined condition as a second target chip, comprises:

under the conditions that the test temperature is set temperature and the test excitation is set test excitation, detecting a junction temperature rise value of the first target chip in the preset time to obtain a second junction temperature rise value, wherein the test temperature is the ambient temperature for performing the FT test on the first target chip, and the test excitation is the excitation for performing the FT test on the first target chip;

and adjusting the set temperature and the set test excitation until the second target chip is obtained.

4. The method of claim 1, wherein screening the chips to be tested according to the quiescent current threshold, the oscillation frequency threshold, and the junction temperature rise threshold comprises:

under the condition that the environmental temperature is the production temperature, obtaining a static current value of the chip to be tested and an oscillation frequency value of an oscillation circuit of the chip to be tested to obtain a target static current value and a target oscillation frequency value, wherein the production temperature is the temperature of the environment where the chip to be tested is in production operation;

under the condition that the junction temperature value of the chip to be tested is a preset temperature, detecting the junction temperature rise value of the chip to be tested in the preset time to obtain a target junction temperature rise value;

and determining that the chip to be tested is qualified under the conditions that the target quiescent current value is less than or equal to the quiescent current threshold value, the target oscillation frequency value is less than or equal to the oscillation frequency threshold value and the target junction temperature rise value is less than or equal to the junction temperature rise threshold value.

5. The method according to claim 2, wherein the predetermined temperature is between 110 ℃ and 120 ℃.

6. The method of claim 1, wherein the predetermined time is greater than or equal to 100 ms.

7. The method of claim 1, wherein the first predetermined range is 115 ℃ to 125 ℃.

8. The method according to claim 2, wherein the minimum value of the second predetermined range is a first temperature rise value, the maximum value of the second predetermined range is a second temperature rise value, the first temperature rise value is 70-90% of the first temperature rise value, and the second temperature rise value is 110-130% of the first temperature rise value.

9. A screen apparatus for a chip, the apparatus comprising:

the first testing unit is used for performing board level testing on a plurality of sample chips, the environmental temperature of the board level testing is a limit temperature, the sample chips meeting a first preset condition are determined as first target chips, quiescent current values and oscillation frequency values of the first target chips are obtained, quiescent current threshold values and oscillation frequency threshold values are determined, the limit temperature is the highest environmental temperature of an application scene of the sample chips, and the first preset condition is that the testing chips work normally and the junction temperature value is in a first preset range;

the second testing unit is used for carrying out FT testing on the first target chip and determining the first target chip meeting a second preset condition as a second target chip, wherein the second preset condition is that the junction temperature rise value of the tested chip in a preset time is in a second preset range;

a third testing unit, configured to perform a board level test on the second target chip, where an ambient temperature of the board level test is a limit temperature, determine the second target chip meeting the first predetermined condition and the second predetermined condition as a third target chip, obtain a junction temperature rise value of the third target chip in the FT test, and determine a junction temperature rise threshold;

and the judging unit is used for screening the chip to be tested according to the quiescent current threshold value, the oscillation frequency threshold value and the junction temperature rising threshold value, and the chip to be tested and the sample chip are chips with the same model.

10. A slice apparatus comprising a processor and a memory, wherein the processor is configured to run a program, wherein the program when run performs the method of any one of claims 1 to 8.

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