CN114284243A - Bonding wafer, bonding structure and bonding method - Google Patents
Bonding wafer, bonding structure and bonding method Download PDFInfo
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- CN114284243A CN114284243A CN202111581105.7A CN202111581105A CN114284243A CN 114284243 A CN114284243 A CN 114284243A CN 202111581105 A CN202111581105 A CN 202111581105A CN 114284243 A CN114284243 A CN 114284243A
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Abstract
本发明提供一种键合用晶圆、键合结构以及键合方法。所述键合方法包括如下步骤：提供键合用的第一晶圆和第二晶圆；在第一晶圆和第二晶圆上形成对准标记，对准标记包括晶圆表面图形或者晶圆通孔。至少有一个晶圆具有通孔，透过该晶圆通孔可以观察到另外一个晶圆的对准标记；以第一晶圆和第二晶圆上的对准标记为基准，将第一晶圆和第二晶圆键合。本发明由于采用晶圆通孔实现可见光同时观察两个晶圆对准标记的直接对准键合，不需要透过硅晶圆的红外辅助装置或者对两个晶圆分别预先定位的机械对准过程，并且对晶圆的透光性无特别要求。
The present invention provides a bonding wafer, a bonding structure and a bonding method. The bonding method includes the following steps: providing a first wafer and a second wafer for bonding; forming alignment marks on the first wafer and the second wafer, and the alignment marks include wafer surface patterns or wafer pass throughs. hole. At least one wafer has a through hole through which the alignment mark of the other wafer can be observed; taking the alignment marks on the first wafer and the second wafer as a reference, the first wafer bonded to the second wafer. In the present invention, since the through-wafer hole is used to realize the direct alignment and bonding of the alignment marks of the two wafers simultaneously observed with visible light, the infrared auxiliary device that penetrates the silicon wafer or the mechanical alignment process of pre-positioning the two wafers is not required. , and there is no special requirement for the light transmittance of the wafer.
Description
Technical Field
The invention relates to the field of semiconductor technology, in particular to a wafer for bonding, a bonding structure and a bonding method.
Background
Bonding is a process of bringing two wafers into contact with each other and bonding them under specific physical conditions. If both wafers for bonding have graphics, the graphics must be aligned with each other. Therefore, how to achieve the alignment of bonding is a problem that the bonding process must solve. One of the methods for solving this problem in the prior art is to use an infrared alignment apparatus, i.e., forming alignment marks corresponding to each other on a wafer for bonding, and imaging the alignment marks by infrared light penetrating through the wafer to form alignment. The drawback of this alignment method is that it requires a special infrared alignment tool and is not suitable for infrared opaque wafers. Another approach in the prior art is to use a visible light imaging system. Because the visible light can not penetrate through the silicon wafer, the two wafers need to be respectively and mechanically aligned and positioned and then aligned and bonded, the process is complex, and meanwhile, the requirement on the moving precision of an alignment machine is high.
Therefore, it is a problem to be solved by the prior art to provide a more convenient and more versatile bonding process.
Disclosure of Invention
The invention aims to provide a bonding wafer, a bonding structure and a bonding method which are more convenient and more universal.
In order to solve the above problems, the present invention provides a wafer for bonding, which includes a through hole for bonding alignment.
In order to solve the above problem, the present invention provides a bonding structure, which includes a first wafer and a second wafer bonded to each other, wherein the first wafer and the second wafer include alignment marks, and at least one of the wafers has a through hole, through which an alignment mark at a corresponding position on the other wafer can be observed.
In order to solve the above problems, the present invention provides a bonding method, comprising the steps of: providing a first wafer and a second wafer for bonding; forming alignment marks on the first wafer and the second wafer, and manufacturing a through hole on at least one wafer; and bonding the first wafer and the second wafer by using the alignment marks on the first wafer and the second wafer as reference.
The alignment mark of another wafer can be observed through the through hole of one wafer, so that the alignment can be realized without an additional infrared auxiliary device and independent mechanical pre-positioning of each wafer, and no special requirement is imposed on the light transmittance of the wafers.
Drawings
FIG. 1 is a schematic diagram illustrating the steps of the method according to the first embodiment of the present invention.
Fig. 2A to 2C are process flow diagrams illustrating a method according to a first embodiment of the present invention.
FIG. 3 is a schematic diagram illustrating the steps of a second embodiment of the method of the present invention.
Fig. 4A to 4C are process flow diagrams illustrating a method according to a second embodiment of the present invention.
FIG. 5 is a schematic diagram illustrating the steps of a third embodiment of the method of the present invention.
Fig. 6A to 6C are process flow diagrams illustrating a method according to a third embodiment of the present invention.
Detailed Description
Specific embodiments of a bonding wafer, a bonding structure, and a bonding method according to the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of the steps of a method according to an embodiment of the present invention, including: step S10, providing a first wafer and a second wafer for bonding; step S11, forming alignment marks on the first wafer and the second wafer, wherein the alignment marks are through holes; step S12, bonding the first wafer and the second wafer with the alignment marks on the first wafer and the second wafer as the reference.
Referring to step S10, as shown in fig. 2A, a first wafer 21 and a second wafer 22 for bonding are provided. The materials of the first wafer 21 and the second wafer 22 are respectively and independently selected from any one common wafer material such as silicon, silicon carbide, sapphire, glass, GaAs, GaN, and metal.
Referring to step S11, as shown in fig. 2B, alignment marks 211 and 221, which are both through holes, are formed on the first wafer 21 and the second wafer 22. In this step, at least one alignment mark on the wafer should include a via. The technical solution adopted in the present embodiment is to set the alignment marks 211 and 221 on both wafers as through holes. The method for forming the through hole can adopt dry etching or wet etching processes including DRIE, ICP, KOH etching and the like, and different etching or etching process parameters are selected according to different wafer materials, so that the consistency of the patterns on the two wafers is ensured. The number of the alignment marks 211 and 221 may be one or more, and the shape thereof may be any shape such as a circle, a square, a cross, and the like, to improve the accuracy of alignment.
Referring to step S12, as shown in fig. 2C, the first wafer 21 and the second wafer 22 are bonded with the alignment marks 211 and 221 on the first wafer 21 and the second wafer 22 as the reference. Because the alignment mark is a through hole, the alignment can be realized without an additional infrared auxiliary device or respectively positioning two wafers in advance, and no special requirement is imposed on the light transmittance of the wafers.
Bonding after wafer alignment is typically achieved by applying pressure and heat. After the preliminary bonding, processes such as annealing, strengthening and the like can be carried out according to needs to complete the bonding so as to improve the firmness of the bonding interface.
The bonding structure obtained after the above steps are performed includes the first wafer 21 and the second wafer 22 bonded to each other, and the first wafer 21 and the second wafer 22 include the alignment marks 211 and 221. At least one of the alignment marks on the wafer in the structure should include a via. In the present embodiment, the alignment marks 211 and 221 are provided as through holes.
FIG. 3 is a schematic diagram illustrating the steps of the method of this embodiment, including: step S30, providing a first wafer and a second wafer for bonding; step S31, forming alignment marks on a first wafer and a second wafer, wherein the alignment mark of the first wafer is a wafer surface pattern, and the alignment mark of the second wafer is a wafer surface pattern; step S32, bonding the first wafer and the second wafer in a back-to-back direction with the alignment marks on the first wafer and the second wafer as a reference.
Referring to step S30, as shown in fig. 4A, a first wafer 41 and a second wafer 42 for bonding are provided. The material of the first wafer 41 and the second wafer 42 is independently selected from any one common wafer material such as silicon, silicon carbide, sapphire, glass, GaAs, GaN, and metal.
Referring to step S31, as shown in fig. 4B, alignment marks 411 and 421 are formed on the first wafer 41 and the second wafer 42, where the alignment mark of the first wafer 41 is a wafer surface pattern 413, and the alignment mark of the second wafer 42 is a wafer surface pattern 421. The method for forming the through hole can adopt dry etching or wet etching processes including DRIE, ICP, KOH etching and the like, and different etching or etching process parameters are selected according to different wafer materials, so that the consistency of the patterns on the two wafers is ensured. The number of the alignment marks may be one or more, and the shape thereof may be any shape such as a circle, a square, a cross, and the like, so as to improve the accuracy of alignment.
Referring to step S32, as shown in fig. 4C, the first wafer 41 and the second wafer 42 are bonded with the alignment marks on the first wafer 41 and the second wafer 42 as the reference marks. Since the alignment mark of the first wafer 41 is the circular surface pattern 413 and the alignment mark of the second wafer 42 is the wafer surface pattern 421, no additional infrared auxiliary device is required, and no special requirement is imposed on the light transmittance of the wafers, so that the alignment can be realized without respectively positioning the two wafers in advance.
Bonding after wafer alignment is typically achieved by applying pressure and heat. After the preliminary bonding, processes such as annealing, strengthening and the like can be carried out according to needs to complete the bonding so as to improve the firmness of the bonding interface.
The bonding structure obtained after the above steps are completed includes a first wafer 41 and a second wafer 42 bonded to each other, the alignment mark of the first wafer 41 is a pattern 413 on the wafer surface, and the alignment mark of the second wafer 42 is a pattern 421 on the wafer surface.
FIG. 5 is a schematic diagram of the steps of a method according to an embodiment of the present invention, including: step S50, providing a first wafer and a second wafer for bonding; step S51, forming alignment marks on a first wafer and a second wafer, wherein the alignment marks on the first wafer are through holes, and the alignment marks on the second wafer are second wafer surface patterns; step S52, bonding the first wafer and the second wafer with the alignment marks on the first wafer and the second wafer as the reference.
Referring to step S50, as shown in fig. 6A, a first wafer 61 and a second wafer 62 for bonding are provided. The materials of the first wafer 61 and the second wafer 62 are respectively and independently selected from any one common wafer material such as silicon, silicon carbide, sapphire, glass, GaAs, GaN, and metal.
Referring to step S51, as shown in fig. 6B, alignment marks 611 and 621 are formed on the first wafer 61 and the second wafer 62, where the alignment mark 611 on the first wafer 61 is a through hole, and the alignment mark 621 on the second wafer 62 is a pattern on the surface of the second wafer 62. In this step, at least one alignment mark on the wafer should include a via. The technical solution adopted in the present embodiment is that the alignment mark 611 on the first wafer 61 is a through hole, and the alignment mark 621 on the second wafer 62 is a pattern on the surface of the second wafer 62. The method for forming the through hole can adopt dry etching or wet etching processes including DRIE, ICP, KOH etching and the like, and different etching or etching process parameters are selected according to different wafer materials, so that the consistency of the patterns on the two wafers is ensured. The number of the alignment marks 611 may be one or more, and the shape thereof may be any shape such as a circle, a square, a cross, and the like, so as to improve the accuracy of alignment. Preferably, the intrinsic pattern on the surface of the second wafer 62 is used as an alignment basis, and a through hole corresponding to the intrinsic pattern is formed on the first wafer 61 as an alignment mark, so as to complete the alignment. The above is particularly suitable for the case where the first wafer 61 has no pattern or a simple pattern, and there is enough space for forming the through holes. The second wafer 62 does not need to make additional bonding alignment marks, so that the wafer area is saved, and the integration level of a single chip on the wafer can be further improved.
Referring to step S52, as shown in fig. 6C, the first wafer 61 and the second wafer 62 are bonded with reference to the alignment marks 611 and 621 on the first wafer 61 and the second wafer 62. Because the alignment mark is a through hole, the alignment can be realized without an additional infrared auxiliary device or respectively positioning two wafers in advance, and no special requirement is imposed on the light transmittance of the wafers.
Bonding after wafer alignment is typically achieved by applying pressure and heat. After the preliminary bonding, processes such as annealing, strengthening and the like can be carried out according to needs to complete the bonding so as to improve the firmness of the bonding interface.
The bonding structure obtained after the above steps are performed includes the first wafer 61 and the second wafer 62 bonded to each other, and the first wafer 61 and the second wafer 62 include the alignment marks 611 and 621. At least one alignment mark on the wafer in the structure comprises a through hole. In this embodiment, the alignment mark 611 on the first wafer 61 is a through hole, and the alignment mark 621 on the second wafer 62 is a pattern on the surface of the second wafer 62.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A wafer for bonding is characterized in that the wafer comprises a through hole for bonding alignment.
2. A bonding structure comprises a first wafer and a second wafer which are bonded with each other, wherein the first wafer and the second wafer comprise alignment marks, and at least one wafer is provided with a through hole in the wafer.
3. The bonding structure of claim 2, wherein the alignment marks on the first and second wafers are through holes.
4. The bonding structure of claim 2, wherein the alignment mark of the first wafer comprises a wafer surface pattern, and the alignment mark of the second wafer comprises a wafer surface pattern.
5. The bonding structure of claim 2, wherein the alignment mark of the first wafer comprises an in-wafer via, and the alignment mark of the second wafer comprises a wafer surface pattern.
6. A bonding method, comprising the steps of:
providing a first wafer and a second wafer for bonding;
forming alignment marks on the first wafer and the second wafer, wherein at least one wafer is provided with a through hole;
and simultaneously observing the alignment marks of the two wafers through one of the wafer through holes, and aligning and bonding the first wafer and the second wafer.
7. The method of claim 6, wherein the alignment marks on the first and second wafers are through holes.
8. The method of claim 6, wherein the alignment mark of the first wafer comprises a surface pattern, and the alignment mark of the second wafer comprises a wafer surface pattern.
9. The bonding structure of claim 6, wherein the alignment mark of the first wafer comprises an in-wafer via, and the alignment mark of the second wafer comprises a wafer surface pattern.
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| CN202111581105.7A CN114284243A (en) | 2021-12-22 | 2021-12-22 | Bonding wafer, bonding structure and bonding method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116153793A (en) * | 2023-02-24 | 2023-05-23 | 芯盟科技有限公司 | The Method of Improving the Residual Value of Bonding Surface Coincidence |
| CN117253806A (en) * | 2023-11-20 | 2023-12-19 | 迈为技术(珠海)有限公司 | A lens concentricity calibration chip and its preparation method |
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| US20060139643A1 (en) * | 2004-12-28 | 2006-06-29 | Industrial Technology Research Institute | Alignment method of using alignment marks on wafer edge |
| CN104282607A (en) * | 2013-07-09 | 2015-01-14 | 中国科学院微电子研究所 | Wafer alignment method and apparatus |
| CN105174209A (en) * | 2015-06-15 | 2015-12-23 | 中国科学院半导体研究所 | Wafer level photoetching machine bonding method |
| CN107305861A (en) * | 2016-04-25 | 2017-10-31 | 晟碟信息科技（上海）有限公司 | Semiconductor device and its manufacture method |
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2021
- 2021-12-22 CN CN202111581105.7A patent/CN114284243A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060139643A1 (en) * | 2004-12-28 | 2006-06-29 | Industrial Technology Research Institute | Alignment method of using alignment marks on wafer edge |
| CN104282607A (en) * | 2013-07-09 | 2015-01-14 | 中国科学院微电子研究所 | Wafer alignment method and apparatus |
| CN105174209A (en) * | 2015-06-15 | 2015-12-23 | 中国科学院半导体研究所 | Wafer level photoetching machine bonding method |
| CN107305861A (en) * | 2016-04-25 | 2017-10-31 | 晟碟信息科技（上海）有限公司 | Semiconductor device and its manufacture method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116153793A (en) * | 2023-02-24 | 2023-05-23 | 芯盟科技有限公司 | The Method of Improving the Residual Value of Bonding Surface Coincidence |
| CN117253806A (en) * | 2023-11-20 | 2023-12-19 | 迈为技术(珠海)有限公司 | A lens concentricity calibration chip and its preparation method |
| CN117253806B (en) * | 2023-11-20 | 2024-01-23 | 迈为技术(珠海)有限公司 | A lens concentricity calibration chip and its preparation method |
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Application publication date: 20220405 |