CN114284162A - Semiconductor test chip and method of making the same - Google Patents
Semiconductor test chip and method of making the same Download PDFInfo
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- CN114284162A CN114284162A CN202011031841.0A CN202011031841A CN114284162A CN 114284162 A CN114284162 A CN 114284162A CN 202011031841 A CN202011031841 A CN 202011031841A CN 114284162 A CN114284162 A CN 114284162A
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- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
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- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
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- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A semiconductor test chip for testing the wire bonding reliability of semiconductor module is composed of a semiconductor substrate and at least one test chip on said semiconductor substrate, which has a top surface opposite to said semiconductor substrate and an electric connection pad with a metal layer and a metallic compound layer on at least part of its surface, and features that said metallic compound layer contains metal oxide and has a thickness of 2-50 nm. In addition, the invention also provides a manufacturing method of the semiconductor test chip. By simulating the surface state of the electrical connection pad of the semiconductor component or the oxidation and corrosion damage conditions in different environments through at least one of the composition, the thickness and the pattern of the metal compound layer, the reaction during the reliability test by using the semiconductor test chip can be accelerated, and the time of the reliability test can be shortened.
Description
Technical Field
The present invention relates to a semiconductor chip and a method for manufacturing the same, and more particularly, to a semiconductor test chip for testing wire bonding reliability and a method for manufacturing the same.
Background
With the demand for thin, small and compact electronic products and the development of semiconductor technology, the size of semiconductor chips is becoming smaller. Among them, wire bonding is an important technology for electrically connecting a semiconductor chip with a small size to the outside, and therefore, how to ensure the wire bonding reliability of the semiconductor chip is an important issue of active attention of related manufacturers.
The metal layers of semiconductor chips used for wire bonding are typically made of aluminum or copper. However, since aluminum or copper is easily oxidized and easily absorbs foreign ions in the external environment, when a metal layer with an oxidized surface or absorbing foreign ions (such as chloride ions, nitrogen ions, etc.) is wire-bonded and packaged to form a semiconductor device, the metal oxide and the foreign ions absorbed in the metal layer may affect the surface properties of the metal layer, further corrode the metal layer, or generate intermetallic compounds between the wire-bonding metal and the metal layer, which may affect the adhesion, so that the wire-bonded semiconductor device may be peeled off or dropped off during the use process, thereby adversely affecting the reliability of the device.
Therefore, in order to ensure the reliability and yield of the chip, the semiconductor device is usually tested for wire bonding reliability before packaging. However, reliability testing is time consuming because of the different environmental conditions to be simulated and the long testing time required.
Disclosure of Invention
The invention aims to provide a semiconductor test chip for testing the wire bonding reliability of a semiconductor component.
The invention relates to a semiconductor test chip, which comprises a semiconductor substrate and at least one test chip.
The at least one test chip is arranged on the semiconductor substrate and comprises a top surface opposite to the semiconductor substrate and at least one electric connection pad exposed outwards from the top surface. The electric connection pad comprises a metal layer and a metal compound layer formed on at least part of the surface of the metal layer in an atomic deposition mode.
Preferably, the semiconductor test chip according to the present invention, wherein the metal compound layer includes at least one of a halogen-containing metal compound, a nitrogen-containing metal compound, and an oxygen-containing metal compound.
Preferably, the thickness of the metal compound layer is 2nm to 50 nm.
Preferably, the at least one test chip further includes a test circuit for electrically connecting the at least one test chip to the outside.
Preferably, the semiconductor test chip of the present invention includes a plurality of test chips distributed in an array on the semiconductor substrate, wherein each test chip further includes a test circuit, and the test chips can be electrically connected by the test circuit.
Preferably, each of the test chips further has a redistribution trace disposed above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution trace and having at least one opening, and each of the electrical connection pads is electrically connected to the redistribution trace and exposed from one of the openings.
Preferably, in the semiconductor test chip of the present invention, the metal layer is electrically connected to the test circuit, and the metal compound layer completely covers a surface of the metal layer.
Preferably, in the semiconductor test chip of the present invention, the metal layer is electrically connected to the test circuit, and the metal compound layer partially covers the surface of the electrical connection pad.
Preferably, in the semiconductor test chip of the present invention, the metal compound layer further extends to cover the dielectric layer.
Another objective of the present invention is to provide a method for manufacturing a semiconductor test chip for testing the wire bonding reliability of a semiconductor device.
The invention relates to a manufacturing method of a semiconductor test chip, which comprises the following steps:
providing a semi-finished product of a semiconductor component, wherein the semi-finished product of the semiconductor component is provided with a semiconductor substrate and at least one chip arranged on the semiconductor substrate, and the at least one chip is provided with a test circuit and at least one metal layer which is electrically connected with the test circuit and is exposed from the top surface of the at least one chip.
And depositing a metal compound layer on at least part of the surface of the at least one metal layer by using an atomic deposition mode to obtain the semiconductor test chip.
Preferably, in the method for manufacturing a semiconductor test chip according to the present invention, the material of the metal compound layer includes at least one of a metal oxide, a halogen-containing metal compound, a nitrogen-containing metal compound, and an oxygen-containing metal compound.
Preferably, in the method for manufacturing a semiconductor test chip of the present invention, the thickness of the metal compound layer is between 2nm and 50 nm.
Preferably, the semiconductor test chip manufacturing method of the present invention, wherein the semiconductor device semi-finished product has a plurality of chips distributed in an array on the semiconductor substrate, each chip has a test circuit, and the chips can be electrically connected by the test circuit.
Preferably, each of the chips further has a redistribution trace disposed above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution trace and having at least one opening, wherein the electrical connection pads are electrically connected to the redistribution trace and respectively exposed from the corresponding openings.
The invention has the beneficial effects that: when the semiconductor test chip is used for testing the reliability of routing, the surface state of the electric connection pad of the semiconductor component, such as roughness, oxidation state and the like, and/or the oxidation and corrosion damage conditions in different environments are simulated through at least one of the composition, the thickness and the pattern of the metal compound layer, so that the reaction during the reliability test by using the semiconductor test chip is accelerated, and the time of the reliability test is shortened.
Drawings
FIG. 1 is a schematic top view of an embodiment of a semiconductor test chip of the present invention;
FIG. 2 is a schematic cross-sectional view illustrating one of the test chips according to the embodiment;
fig. 3 is a partial sectional structural view illustrating the electrical connection pad of the embodiment;
fig. 4 is a TEM image illustrating the formation of a metal compound layer on a metal layer.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
It should be noted that the drawings of the present invention are only for showing the relative relationship of the structures and/or positions of the components, and are not directly related to the actual sizes of the components.
The semiconductor test chip is used for testing the routing reliability.
Referring to fig. 1 and 2, one embodiment of the semiconductor test chip includes a semiconductor substrate 2 and a plurality of test chips 3.
The semiconductor substrate 2 may be selected from silicon, compound semiconductors such as silicon carbide (SiC), or group III-IV such as gallium arsenide (GaAs), indium phosphide (InP), or group II-VI semiconductor materials such as zinc oxide (ZnO), cadmium telluride (CdTe).
The test chips 3 are disposed on the semiconductor substrate 2 in an array arrangement. Each test chip 3 has a top surface opposite to the semiconductor substrate 2, a test circuit 31, a redistribution circuit 32 located above the test circuit 31 and electrically connected to the test circuit 31, a dielectric layer 33 covering the redistribution circuit 32 and having at least one opening 331, and electrical connection pads 34 respectively connected to the redistribution circuit 32 and exposed from one of the openings 331 corresponding to the dielectric layer 33.
In detail, the test circuit 31 has a plurality of dielectric insulating layers 311 and metal circuit layers 312 alternately stacked on the semiconductor substrate 2, and a plurality of conductive vias 313 penetrating through the dielectric insulating layers 311 to electrically connect the metal circuit layers 312 differently, and the conductive vias 313 are electrically connected to the different metal circuit layers 312 to form different conductive loops. In order to simulate the circuit of a general functional chip, the number, thickness, electrical connection relationship, etc. of the dielectric insulating layer 311 and the metal circuit layer 312 of the test circuit 31 can also completely simulate the circuit structure of the functional chip, so that the circuit test result of the test chip 3 can be fed back to the functional chip to correspondingly adjust the circuit design of the functional chip. The dielectric insulating layer 311 may be silicon dioxide, silicon nitride, silicon oxynitride, or polymer material, and the metal circuit layer 312 and the conductive via 313 may be respectively selected from conductive materials such as tungsten, aluminum, copper, aluminum alloy, or copper alloy. Since the related processes and materials of the test circuit 31 are well known in the semiconductor technology field, they will not be described in detail.
The redistribution circuit 32 is disposed above the test circuit 31 and electrically connected to the test circuit 31. The dielectric layer 33 covers the redistribution layer 32 and has a plurality of openings 331 for exposing the redistribution layer 32. The redistribution layer 32 is made of a conductive material such as tungsten, aluminum, copper, aluminum alloy or copper alloy, and the dielectric layer 33 is made of silicon dioxide, silicon nitride, silicon oxynitride or polymer material.
The electrical connection pads 34 and the redistribution traces 32 are connected to the exposed surface of the opening 331 and are exposed from the corresponding openings 331 respectively for subsequent wire bonding or forming solder or copper bumps, so that the metal trace layers 312 are connected in series to form at least one independent conductive loop. In detail, each of the electrical connection pads 34 has a metal layer 341 connected to the surface of the redistribution trace 32 exposed from the opening 331, and a metal compound layer 342 formed on at least a portion of the surface of the metal layer 341. The metal layer 341 is made of aluminum, aluminum alloy, copper, or copper alloy, and the material of the metal compound layer 342 includes metal oxide and at least one of halogen-containing metal compound, nitrogen-containing metal compound, and oxygen-containing metal compound.
In some embodiments, the thickness of the metal compound layer 342 is between 2nm and 50 nm. Preferably, the thickness of the metal compound layer 342 is greater than 5 nm.
In some embodiments, the thickness of the metal compound layer 342 is between 10nm and 50 nm.
It should be noted that, since the metal compound layer 342 is composed of at least one of a metal oxide, a halogen-containing compound, a nitrogen-containing compound, and an oxygen-containing compound, it will affect the electrical properties of the electrical connection pad 34, so that the electrical connection pad 34 can be controlled to have different electrical properties and roughness by the composition and distribution of the metal compound layer 342 (for example, the metal compound layer 342 can be selectively covered on the surface of the metal layer 341 on the whole or in part, for example, see fig. 2 and 3, fig. 2 is a graph in which the metal compound layer 342 covers the surface of the metal layer 341 on the whole and has a thickness of 2nm to 50 nm; fig. 3 is a graph in which the metal compound layer 342 covers part of the surface of the metal layer 341 on the whole and has a thickness of 2nm to 50nm) according to the test requirements and purposes of the semiconductor test chip, so as to be more suitable for simulating the testing conditions of different routing reliability. In addition, it is to be noted that, in practical implementation, the metal compound layer 342 may also be covered on a portion of the surface of the metal layer 341 in an irregular manner, or may further extend to cover the dielectric layer 33 as required, and the structure shown in fig. 2 and 3 is not limited thereto
Generally, the metal compound layer 342 formed on the surface of the metal layer 341 not only causes electrical change, but also causes surface roughness and surface chemical property change, which affects the adhesion and bonding strength between the subsequent wire bonding, solder or copper bump and the electrical connection pad 34. However, since the native metal oxide is typically very thin (<5nm), when a chip having an electrical connection pad with a very thin metal oxide on the surface is used for wire bonding and a reliability evaluation test of wire bonding is performed, a long detection time is required to measure the influence of the metal oxide on the wire bonding. Therefore, the invention controls the original surface property and roughness of the electrical connection pad 34 by the composition of the metal compound layer 342 and the distribution and thickness of the metal compound layer 342, and can provide the test chip 3 with the electrical connection pads 34 with different surface property/electrical property and roughness conditions for wire bonding reliability tests under different conditions and can induce and accelerate the reaction of utilizing the semiconductor test chip in the reliability test, thereby effectively reducing the reliability test time.
Specifically, the metal compound layer 342 can be deposited on the surface of the metal layer 341 of the chip having the test circuit 31, the redistribution layer 32, the dielectric layer 33 and the metal layer exposed from the opening 331 of the dielectric layer 33 by atomic deposition (ALD), so as to control the thickness and pattern of the metal compound layer 342 and the surface roughness of the electrical connection pad 34.
It should be noted that, since the adhesion between the wire/solder ball/copper bump and the electrical connection pad 34 is affected by the surface roughness of the electrical connection pad 34, and also by the chemical properties of the connection interface between the wire/solder ball/copper pillar and the electrical connection pad 34, the metal compound layer 342 of the present invention can further comprise one compound of group a in addition to the metal oxide, wherein the compound of group a is formed by the reaction of the metal layer 341 and the non-metal element (such as halogen, nitrogen, oxygen), and comprises: halogen-containing compounds, nitrogen-containing compounds, and oxygen-containing compounds. Through the composition change of the metal compound layer 342, the surface of the electrical connection pad 34 can be simulated in advance by the change of the surface chemical property in different environments except the change of the roughness, so that the induction reaction is accelerated when the reliability test is performed on the semiconductor test chip, and the time of the reliability test is shortened.
In some embodiments, when the metal layer 341 is made of aluminum (Al), the metal oxide of the metal compound layer 342 is aluminum oxide (Al)2O3) The halogen-containing compound may be [ AlF6]3-Or AlF3The nitrogen-containing compound may be aluminum nitride (AlN).
In other embodiments, the metal layer 341 is made of copper (Cu), and the metal oxide of the metal compound layer 342 is copper oxide (CuO) and/or copper (Cu) oxide2O), the halogen-containing compound may be CuClx。
It should be noted that the test chip 3 may be subsequently formed with solder bumps on its electrical connection pads 34, and electrically connect the solder bumps of one of the electrical connection pads 34 with the solder bumps of the other electrical connection pads 34; or different electrical connection pads 34 are electrically connected to each other by wire bonding to electrically connect a plurality of independent circuits of the test circuit 31 of the test chip 3, or different test chips 3 can be connected in series to form a Daisy chain (Daisy chain). Since the test chips 3 are distributed on the semiconductor substrate 2 in an array manner, the test chips 3 can be cut according to the number of the test chips 3 and the electrical connection pattern (as shown by the dotted line in fig. 1) when in use, and thus the semiconductor device can be used more easily.
Referring to fig. 4, fig. 4 is a TEM photograph showing a metal compound layer 342 containing aluminum oxide formed on a metal layer 341 made of Al, in which fig. 4(b) is a partially enlarged view of fig. 4(a), and fig. 4(c) is a metal compound layer 342 containing aluminum oxide and a fluorine-containing compound. As can be seen from fig. 4, the thickness of the metal compound layer 342 can be used to control the surface roughness of the electrical connection pad 34, and the test chip 3 with different surface roughness and chemical energy states can be obtained by matching the chemical composition change of the metal compound layer 342, so as to be used for the reliability evaluation test for evaluating the influence of different roughness and different surface energy states on wire bonding.
In summary, the present invention utilizes the metal compound layer 342 formed by at least one of the halogen-containing compound, the nitrogen-containing compound and the oxygen-containing compound, which are formed by the metal layer 341 and the metal layer 341 being reacted by different non-metal elements, to form the metal oxide on the surface of the metal layer 341, or further to form the metal compound layer 342 comprising at least one of the halogen-containing compound, the nitrogen-containing compound and the oxygen-containing compound, so that the surface properties of the electrical connection pad 34 can simulate the surface roughness, oxidation and corrosion damage conditions of the electrical connection pad 34 of the semiconductor chip in different environments by means of the metal compound layer 342, thereby obtaining the possible abnormal wire bonding reliability of the metal layer surface in the semiconductor device manufacturing process in the reliability test, accelerating the induction reaction, reducing the time of the reliability test, and assisting the research and development personnel to grasp the problem in real time and shorten the research and development time, thereby achieving the purpose of the present invention.
Claims (14)
1. A semiconductor test chip for testing the wire bonding reliability of a semiconductor device, comprising: a semiconductor substrate; and at least one test chip disposed on the semiconductor substrate, wherein: the at least one test chip includes:
inverting the top surface of the semiconductor substrate; and
at least one electric connection pad exposed from the top surface and comprising a metal layer and a metal compound layer formed on at least part of the surface of the metal layer by atomic deposition.
2. The semiconductor test chip of claim 1, wherein: the metal compound layer includes at least one of a halogen-containing metal compound, a nitrogen-containing metal compound, and an oxygen-containing metal compound.
3. The semiconductor test chip of claim 1, wherein: the thickness of the metal compound layer is between 2nm and 50 nm.
4. The semiconductor test chip of claim 1, wherein: the at least one test chip further comprises a test circuit for electrically connecting the at least one test chip to the outside.
5. The semiconductor test chip of claim 1, wherein: the semiconductor test chip comprises a plurality of test chips distributed on the semiconductor substrate in an array mode, wherein each test chip further comprises a test circuit, and the test chips can be electrically connected through the test circuits.
6. The semiconductor test chip of claim 5, wherein: each test chip is also provided with a redistribution circuit which is positioned above the test circuit and electrically connected with the test circuit, and a dielectric layer which covers the redistribution circuit and is provided with at least one opening, and each electrical connection pad is electrically connected with the redistribution circuit and is exposed from one corresponding opening.
7. The semiconductor test chip of claim 4, wherein: the metal layer is electrically connected with the test circuit, and the metal compound layer completely covers the surface of the metal layer.
8. The semiconductor test chip of claim 4, wherein: the metal layer is electrically connected with the test circuit, and the metal compound layer partially covers the surface of the electric connection pad.
9. The semiconductor test chip of claim 7 or 8, wherein: the metal compound layer also extends over the dielectric layer.
10. A semiconductor test chip manufacturing method is characterized in that: comprises the following steps:
providing a semi-finished product of a semiconductor component, wherein the semi-finished product of the semiconductor component is provided with a semiconductor substrate and at least one chip arranged on the semiconductor substrate, and the at least one chip is provided with a test circuit and at least one metal layer which is electrically connected with the test circuit and is exposed from the top surface of the at least one chip; and
and depositing a metal compound layer on at least part of the surface of the at least one metal layer by using an atomic deposition method to obtain the semiconductor test chip.
11. The method of manufacturing a semiconductor test chip according to claim 10, wherein: the material of the metal compound layer includes at least one of a metal oxide, a halogen-containing metal compound, a nitrogen-containing metal compound, and an oxygen-containing metal compound.
12. The method of manufacturing a semiconductor test chip according to claim 10, wherein: the thickness of the metal compound layer is between 2nm and 50 nm.
13. The method of manufacturing a semiconductor test chip according to claim 10, wherein: the semi-finished product of the semiconductor component is provided with a plurality of chips distributed on the semiconductor substrate in an array mode, each chip is provided with a test circuit, and the chips can be electrically connected through the test circuits.
14. The method of manufacturing a semiconductor test chip according to claim 13, wherein: each chip also has a redistribution circuit located above the test circuit and electrically connected with the test circuit, and a dielectric layer covering the redistribution circuit and having at least one opening, wherein the electrically connecting pads are electrically connected with the redistribution circuit and respectively exposed from the corresponding openings.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114334684A (en) * | 2020-09-29 | 2022-04-12 | 丁肇诚 | Semiconductor test chip with electric connection pad with adjustable energy state and manufacturing method thereof |
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| US20160329275A1 (en) * | 2015-05-07 | 2016-11-10 | Samsung Electronics Co., Ltd. | Package substrate and methods for manufacturing the same |
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| CN212907649U (en) * | 2020-09-27 | 2021-04-06 | 丁肇诚 | Semiconductor test chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114334684A (en) * | 2020-09-29 | 2022-04-12 | 丁肇诚 | Semiconductor test chip with electric connection pad with adjustable energy state and manufacturing method thereof |
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