CN114283872A - Test vector generation device and method - Google Patents
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Abstract
The application relates to a test vector generation device and a test vector generation method, and belongs to the technical field of integrated circuit testing. Wherein, a test vector generation apparatus comprises: the device comprises a functional model module, a test graph algorithm module, a test vector description module, a test vector calculation module and a vector data output module. The function model module is used for establishing a test function model according to the interface information acquired from the memory to be tested; the test pattern algorithm module is used for providing test pattern calculation logic; the test vector description module is used for providing vector data information of a memory address and providing pin definition; the test vector calculation module is used for calculating test vector data of each storage address of the memory to be tested; the vector data output module is used for outputting test vector data. The device can conveniently and quickly generate the test vector data applied to the memory function test, solves the technical problem of long time of the test vector generation process, and improves the test efficiency of the memory.
Description
Technical Field
The present disclosure relates to the field of integrated circuit testing technologies, and in particular, to a test vector generation apparatus and method.
Background
The memory is an important class of integrated circuits, is an important medium for realizing large-capacity data storage and transmission, and is mainly used for storing information such as data, instructions, programs and the like. The continuous development of modern mobile memory technology and memory market makes semiconductor memory become the most widely used memory device at present, and the testing position of memory in the field of integrated circuit is more and more important. The testing of the memory can be used for judging whether the product quality is qualified or not on the one hand, and on the other hand, the data can be acquired through the testing and used for improving the manufacturing process of the memory.
The complexity of the memory chip and the variety of memory cell types further determine the difficulty of testing. The particularity of the memory structure also determines that direct physical detection cannot be adopted for testing the chip of the type, and the physical fault of the memory is converted into a logic displayable form by continuously reading and writing data of the memory unit and comparing the data with a theoretical data state.
The memory test includes a dc parametric test, an ac parametric test, and a functional test, as with other digital circuits. The most important test is the read/write logic function test to detect the failure of the memory cell, including the functional failure due to bad metal connections, bad elements, chip logic errors, etc. The functional test is to apply test vectors to the memory for detection, detect various memory fault defects through read-write operation, and the test vectors represent the logic functions of the tested memory chip. For a large-capacity memory, in order to ensure the fault coverage rate, the data volume of the test vector required by the function test is huge, the time required by the vector generation process is long, and the test efficiency of the memory is directly influenced to a great extent.
Disclosure of Invention
In order to solve the technical problem of long time of a test vector generation process, the application provides a test vector generation device and a test vector generation method.
In a first aspect, the present application provides a test vector generation apparatus, including: the system comprises a functional model module, a test graph algorithm module, a test vector description module, a test vector calculation module and a vector data output module;
the function model module is used for acquiring interface information from a memory to be tested and establishing a test function model of the memory to be tested according to the interface information;
the test pattern algorithm module is used for providing test pattern calculation logic of the memory to be tested;
the test vector description module is used for providing vector data information of a memory address of the memory to be tested and providing pin definition of the memory to be tested;
the test vector calculation module is used for extracting specific pin signals of the memory to be tested according to the vector data information of the memory address and the pin definition, and calculating test vector data of each memory address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model and the test pattern calculation logic;
the vector data output module is used for outputting test vector data of each storage address of the memory to be tested;
further, the interface information includes address information, data information, and control information;
the function model module is used for establishing a test function model of the memory to be tested according to the address information, the data information and the control information;
further, the functional model module includes: the device comprises an address register unit, an address decoding unit, a data register unit, a data reading unit, a data writing unit, a data storage array and a control logic unit;
the address register unit is used for storing the address information;
the address decoding unit is used for analyzing and mapping the address information;
the data registering unit is used for registering the data information;
the read data unit is used for finishing the drive work of the read data of the memory to be tested;
the write data unit is used for finishing the drive work of the write data of the memory to be tested;
the data storage array is used for storing the data information and finishing the data storage of the storage address corresponding to the address information through the mapping of the address information;
the control logic unit is used for controlling the working logic of the memory to be tested according to the control information;
further, the test pattern algorithm module includes: the system comprises a test graph algorithm library, a graph algorithm generator, a control unit, an address unit and a data unit;
the test pattern algorithm library is used for storing at least one test pattern algorithm;
the pattern algorithm generator is used for outputting a test pattern sequence under the action of the test pattern algorithm, and the test pattern sequence comprises a control data sequence, an address data sequence and a test data sequence;
the control unit is used for storing the control data sequence;
the address unit is used for storing the address data sequence;
the data unit is used for storing the test data sequence;
further, the test pattern algorithm library comprises at least one of an all-zero all-one test pattern algorithm, a checkerboard test pattern algorithm, a marching test pattern algorithm and a roaming test pattern algorithm;
the test pattern algorithm is used for testing any memory address of the memory to be tested;
further, the test graph algorithm library also comprises an expansion interface of the test graph algorithm;
the expansion interface is used for increasing and/or optimizing and improving the test pattern algorithm in the test pattern algorithm library;
further, the specific pin signal includes: a control terminal pin signal, an address terminal pin signal and a data terminal pin signal;
the specific pin signal calibration sequence is a control end pin signal, an address end pin signal and a data end pin signal in sequence;
further, the control terminal pin signals comprise output enable pin signals, read/write control pin signals and chip select pin signals;
the control end pin signal calibration sequence is the output enable pin signal, the read/write control pin signal and the chip select pin signal in sequence;
further, the apparatus is used for static random access memory testing.
In a second aspect, the present application provides a test vector generation method, including:
acquiring interface information from a memory to be tested, and establishing a test function model of the memory to be tested according to the interface information;
acquiring a test graph calculation logic of the memory to be tested;
acquiring vector data information of a storage address of the memory to be tested, and acquiring pin definition of the memory to be tested;
extracting specific pin signals of the memory to be tested according to the vector data information of the memory address and the pin definition, and calculating test vector data of each memory address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model and the test pattern calculation logic;
and outputting the test vector data of each memory address of the memory to be tested.
In a third aspect, an electronic device is provided, which includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
and the processor is used for realizing the steps of the test vector generation method in the embodiment of the second aspect when executing the program stored in the memory.
In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the test vector generation method according to the embodiment of the second aspect.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
the test vector generation device provided by the embodiment of the application extracts interface information of a memory to be tested by using the function model module of the device, utilizes vector data information of a memory address provided by the test vector description module and pin definition of the memory to be tested, provides test pattern calculation logic by combining with the test pattern algorithm module, and utilizes the test vector calculation module to calibrate specific pin signals of the memory to be tested, so as to calculate test vector data of each memory address under the action of different test pattern algorithms.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a test vector generation apparatus according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a function model module according to an embodiment of the present disclosure;
FIG. 3 is a schematic block diagram of a test pattern algorithm module according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of a test vector generation method according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart of another test vector generation method according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
A first embodiment of the present application provides a test vector generation apparatus, as shown in fig. 1, including: a functional model module 101, a test pattern algorithm module 102, a test vector description module 103, a test vector calculation module 104 and a vector data output module 105.
The functional model module 101 is configured to obtain interface information from a memory to be tested, and establish a test functional model of the memory to be tested according to the interface information; the test pattern algorithm module 102 is used for providing a test pattern calculation logic of a memory to be tested; the test vector description module 103 is used for providing vector data information of a memory address of the memory to be tested and providing pin definitions of the memory to be tested; the test vector calculation module 104 is configured to extract a specific pin signal of the memory to be tested according to vector data information and pin definitions of one memory address, and calculate test vector data of each memory address of the memory to be tested according to the specific pin signal of the memory to be tested, the test function model, and the test pattern calculation logic; the vector data output module 105 is configured to output test vector data of each memory address of the memory to be tested. The memory address may be referred to as a memory address location or a memory location.
In this embodiment, the functional model module 101, the test pattern algorithm module 102, and the test vector description module 103 are the basis of the test vector calculation module 104. The test pattern calculation logic is obtained according to a test pattern algorithm. The test vector description module 103 mainly provides definition of all pins of the memory, Timing information used in the test process, and read-write row vector data of a main part of the test vector data, that is, a row of vector write data and expected response data of a memory address in a single test period, provides a signal calibration function of the pins of the memory chip for the test vector calculation module, completes the calibration function of the pin signals of the memory through the read-write row of the vector data of a memory address, and provides a pin signal interface for importing a vector graphics algorithm provided by the test graphics algorithm module. The memory chip pin signals further include a control terminal pin signal, an address terminal pin signal, and a data terminal pin signal of the memory chip.
The test vector calculation module 104 calculates a test vector pattern sequence of the memory to be tested by combining the functional model module 101 and the test pattern algorithm module 102 on the basis of the pin signal calibrated by the test vector description module 103, that is, one pattern algorithm in the memory test pattern algorithm library is correspondingly selected according to the test requirement, and test input data and expected response data of different address sequences of all memory cells of the pin of the memory chip are calculated. Where test input data is generally represented by 0 or 1 and expected response data is generally represented by L or H or Z or X.
The vector data output module 105 forms the test vector graphic sequence generated by the test vector calculation module into a data file and outputs a complete test vector data file of the memory to be tested.
The test vector generation device extracts interface information of a memory to be tested by using the functional model module, utilizes vector data information of a memory address and pin definition of the memory to be tested, which are provided by the test vector description module, provides test pattern calculation logic by combining the test pattern algorithm module, and utilizes the test vector calculation module to calibrate specific pin signals of the memory to be tested, so as to calculate test vector data of each memory address under the action of different test pattern algorithms.
In one embodiment, the interface information includes address information, data information, and control information. The function model module is used for establishing a test function model of the memory to be tested according to the address information, the data information and the control information.
In the embodiment, universality and convenience are considered during the generation of the memory test vector, the control information, the address information and the data information are extracted through the functional model module, different test pattern algorithms are combined, and the memory test vector data under different test pattern algorithms can be generated by fast expanding on the basis of the read-write row vector of the single memory address vector data. The test vector generation device of the memory is simple in configuration, can quickly improve the efficiency of memory test vector generation, provides a quick generation device for a user to complete large-scale vector data compiling of the memory, provides a test vector data file with high complexity and large data scale for completing memory function test, greatly improves the memory test efficiency and saves the test cost.
The control information further comprises an enabling control, a reading/writing control and a chip selection control, and the reading and writing operations of the memory circuit are realized through the cooperation of the enabling signal, the reading/writing control signal and the chip selection signal.
In one embodiment, as shown in FIG. 2, the functional model module 101 comprises: address register unit 201, address decode unit 202, data register unit 203, read data unit 204, write data unit 205, data storage array 206, and control logic unit 207.
The address register unit 201 is configured to store address information, the address decode unit 202 is configured to analyze and map the address information, the data register unit 203 is configured to register data information, the data read unit 204 is configured to complete driving of reading data of a memory to be tested, the data write unit 205 is configured to complete driving of writing data of the memory to be tested, the data storage array 206 is configured to store the data information and complete data storage of a storage address corresponding to the address information by mapping the address information, and the control logic unit 207 is configured to control a working logic of the memory to be tested according to the control information.
In this embodiment, the data storage array 206 is a data storage core of the memory, and the stored data information is not lost under the condition that the memory is not powered down. The address decoding unit 202 decodes the address information in the address register and determines the address information of the unit to be accessed or read; the data writing unit 205 and the data reading unit 204 implement writing and reading operations of the memory based on the read/write control logic of the control logic unit, each read/write operation can only act on one storage address of the memory, and all data to be written into the memory and read from the memory are stored in the data registering unit 203.
Specifically, the address register unit 201 is mainly used for storing address information of the memory; the address decoding unit 202 is used for completing the parsing and mapping of the memory address information; the data registering unit 203 is used for completing the storage function of the memory data, wherein the memory data further comprises input data, expected response data and actual acquisition data; the read data unit 204 and the write data unit 205 respectively complete the drive work of reading data and writing data of the memory; the data storage array 206 is mainly used for storing data information, and completes data storage of corresponding storage addresses through mapping of address information; the control logic unit 207 mainly implements a work logic control function for the memory chip, wherein the work logic control further includes an enable control, a read/write control, and a chip select logic control of the memory chip.
In one embodiment, as shown in FIG. 3, the test pattern algorithm module 102 includes: a test pattern algorithm library 301, a pattern algorithm generator 302, a control unit 303, an address unit 304 and a data unit 305.
The test pattern algorithm library 301 is used for storing at least one test pattern algorithm; the pattern algorithm generator 302 is used for outputting a test pattern sequence under the action of a test pattern algorithm, wherein the test pattern sequence comprises a control data sequence, an address data sequence and a test data sequence; the control unit 303 is used to store control data sequences; the address unit 304 is used to store a sequence of address data; the data unit 305 is used to store a test data sequence. Wherein the test data sequence includes an input data sequence and an expected response data sequence.
In this embodiment, the test pattern algorithm module is mainly used to provide a test pattern algorithm library of memory test vectors, and generate test pattern sequences under the action of different test pattern algorithms. The test pattern algorithm can effectively detect the fixed faults, the conversion faults, the address decoding faults and the state coupling faults of the memory.
The control unit 303 is mainly used for storing control data sequences of all storage addresses of the memory chip to be tested; the address unit 304 is mainly used for storing a storage address data sequence of the tested memory unit; the data unit 305 is mainly used to generate the input data and expected response data sequences of the corresponding memory addresses of the memory. The data sequences of the control unit, the address unit and the data unit jointly form a test pattern sequence. Wherein the input data sequence of the control data, address data and data blocks is data written to a memory cell, generally indicated at 0/1; the expected response data is the expected value of the read memory data, generally denoted by L/H/Z/X. A series of test vector graphic sequences representing the logic functions of the memory are output by extracting control terminal pin information, address terminal pin information and data terminal pin information of the memory chip to be tested and correspondingly combining with test input data and expected response data generated by a test graphic algorithm.
In one embodiment, as shown in FIG. 3, the library of test pattern algorithms 301 includes at least one of an all-zero all-one test pattern algorithm, a checkerboard test pattern algorithm, a marching test pattern algorithm, and a roaming test pattern algorithm.
The test pattern algorithm is used for testing the full-function memory address of the memory to be tested, the full-function memory address is all the memory address units, that is, the data of all the memory address units of the memory to be tested are calculated according to the test pattern algorithm, and the test is carried out according to the test pattern algorithm.
The all-zero all-one test pattern algorithm is also called MSCAN test pattern algorithm, the checkerboard test pattern algorithm is also called CheckBoard test pattern algorithm, the marching test pattern algorithm is also called March test pattern algorithm, and the roaming test pattern algorithm is also called GALPAT test pattern algorithm.
In this embodiment, the test pattern algorithm library includes an MSCAN (all zero and all one, or all 0 and all 1) test pattern algorithm, a CheckBoard test pattern algorithm, a March test pattern algorithm, a GALPAT (roaming) test pattern algorithm, and the like, and any one or a plurality of test pattern algorithms may be selected in use. The test pattern sequence output by the test pattern algorithm generator under the action of the pattern algorithm comprises control data, address data and test data, and is respectively stored in the control unit, the address unit and the data unit.
According to the working flows of different test pattern algorithms, different unit address sequences and different test data of all storage addresses of the memory can be generated, so that data writing and reading tests of different sequences of all storage address units can be completed, faults of the memory can be effectively detected, and efficient and comprehensive functional tests of the memory can be completed.
In one embodiment, the test pattern algorithm library further comprises an extension interface of the test pattern algorithm. The expansion interface is used for adding and/or optimizing the test pattern algorithm in the improved test pattern algorithm library.
In this embodiment, interface information such as control information, address information, and data information of the memory is extracted by using the function model module, control pin signals, address pin signals, and data pin signals of the memory chip are calibrated by using the vector read/write line established by the test vector description module, and control data, address data, and read/write data under the action of different test pattern algorithms are calculated by combining different test pattern algorithms provided by the test pattern algorithm module, so as to form a series of test vector pattern sequences covering all test units of the memory, and provide a test vector data source for completing a functional test of the memory, thereby greatly saving time for a user to write a test vector, improving test efficiency of the memory, and saving test cost. The test vector data under the action of the four test pattern algorithms can detect different fault states, and simultaneously provides an extensible interface of the test pattern algorithm, so that space is reserved for increasing or improving the test pattern algorithm, and the existing test pattern algorithm can be optimized or a new test pattern algorithm can be added through the extensible interface.
In one embodiment, the specific pin signals include: the pin signal calibration method comprises the steps that a control end pin signal, an address end pin signal and a data end pin signal are adopted, and the specific pin signal calibration sequence is the control end pin signal, the address end pin signal and the data end pin signal in sequence.
In one embodiment, the control terminal pin signals include an output enable pin signal, a read/write control pin signal and a chip select pin signal, and the control terminal pin signals are sequentially marked in the order of the output enable pin signal, the read/write control pin signal and the chip select pin signal.
In one embodiment, the test vector generation apparatus is used for static random access memory testing. Static Random Access Memory (SRAM) is a type of Random Access Memory, and is called "Static", which means that data stored in the Memory can be constantly maintained as long as the Memory is powered on.
The test vector generating device is suitable for a static random access memory chip, and can randomly write or read information of all storage addresses or information of any at least one storage address in the memory at any time.
Based on the same concept, a second embodiment of the present application provides a test vector generation method, as shown in fig. 4, including:
According to the test vector generation method, by acquiring interface information, combining with test pattern calculation logic, calibrating all pins of a memory to be tested according to pin definitions and vector data information of a memory address, expanding and generating test vector data of each memory address under the test pattern calculation logic, and further outputting the test vector data, the time for writing test vectors by a user is greatly saved, the technical problem that the test vector generation process is long is solved, the test efficiency of the memory is improved, and the test cost is saved.
In one embodiment, a test vector generation method, as shown in fig. 5, includes:
And 505, expanding the test vector data rows of all storage addresses of the memory by combining a test pattern algorithm based on the calibrated pin signal and the vector read/write routine to generate a test vector data file.
In the embodiment, a memory function model is established according to a to-be-tested memory chip manual, interface information (the interface information comprises control information, address information, data information and the like) of a memory is extracted from the function model, a memory test vector read/write data indication routine is established according to the interface information, calibration work of test pin signals is completed, a corresponding test pattern algorithm is selected from a test pattern algorithm library, test vector data read-write rows of all storage addresses of the memory are expanded on the basis of the calibrated pin signals, the test pattern algorithm and the test vector read/write data indication routine, a test vector data file is generated, and the memory test vector data file is output, so that the time for writing test vectors by a user is greatly saved, the technical problem of long time in a test vector generation process is solved, and the test efficiency of the memory is improved, and the test cost is saved.
As shown in fig. 6, a third embodiment of the present application provides an electronic device, which includes a processor 111, a communication interface 112, a memory 113, and a communication bus 114, wherein the processor 111, the communication interface 112, and the memory 113 complete mutual communication via the communication bus 114,
a memory 113 for storing a computer program;
in one embodiment, the processor 111 is configured to implement the test vector generation method provided in any one of the foregoing method embodiments when executing the program stored in the memory 113, where a test vector generation method includes:
acquiring interface information from a memory to be tested, and establishing a test function model of the memory to be tested according to the interface information;
acquiring a test graph calculation logic of the memory to be tested;
acquiring vector data information of a storage address of the memory to be tested, and acquiring pin definition of the memory to be tested;
extracting specific pin signals of the memory to be tested according to the vector data information of the memory address and the pin definition, and calculating test vector data of each memory address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model and the test pattern calculation logic;
and outputting the test vector data of each memory address of the memory to be tested.
The communication bus mentioned in the above terminal may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the terminal and other equipment.
The Memory may include a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
A fourth embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the test vector generation method as provided in any one of the method embodiments described above.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A test vector generation apparatus, comprising: the system comprises a functional model module, a test graph algorithm module, a test vector description module, a test vector calculation module and a vector data output module;
the function model module is used for acquiring interface information from a memory to be tested and establishing a test function model of the memory to be tested according to the interface information;
the test pattern algorithm module is used for providing test pattern calculation logic of the memory to be tested;
the test vector description module is used for providing vector data information of a memory address of the memory to be tested and providing pin definition of the memory to be tested;
the test vector calculation module is used for extracting specific pin signals of the memory to be tested according to the vector data information of the memory address and the pin definition, and calculating test vector data of each memory address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model and the test pattern calculation logic;
the vector data output module is used for outputting the test vector data of each memory address of the memory to be tested.
2. The apparatus of claim 1, wherein the interface information comprises address information, data information, and control information;
the function model module is used for establishing a test function model of the memory to be tested according to the address information, the data information and the control information.
3. The apparatus of claim 2, wherein the functional model module comprises: the device comprises an address register unit, an address decoding unit, a data register unit, a data reading unit, a data writing unit, a data storage array and a control logic unit;
the address register unit is used for storing the address information;
the address decoding unit is used for analyzing and mapping the address information;
the data registering unit is used for registering the data information;
the read data unit is used for finishing the drive work of the read data of the memory to be tested;
the write data unit is used for finishing the drive work of the write data of the memory to be tested;
the data storage array is used for storing the data information and finishing the data storage of the storage address corresponding to the address information through the mapping of the address information;
and the control logic unit is used for controlling the working logic of the memory to be tested according to the control information.
4. The apparatus of claim 1, wherein the test pattern algorithm module comprises: the system comprises a test graph algorithm library, a graph algorithm generator, a control unit, an address unit and a data unit;
the test pattern algorithm library is used for storing at least one test pattern algorithm;
the pattern algorithm generator is used for outputting a test pattern sequence under the action of the test pattern algorithm, and the test pattern sequence comprises a control data sequence, an address data sequence and a test data sequence;
the control unit is used for storing the control data sequence;
the address unit is used for storing the address data sequence;
the data unit is used for storing the test data sequence.
5. The apparatus of claim 4, wherein the library of test pattern algorithms comprises at least one of an all-zero all-one test pattern algorithm, a checkerboard test pattern algorithm, a march test pattern algorithm, and a roving test pattern algorithm;
the test pattern algorithm is used for testing any memory address of the memory to be tested.
6. The apparatus of claim 5, wherein the library of test pattern algorithms further comprises an extended interface for test pattern algorithms;
the expansion interface is used for increasing and/or optimizing and improving the test pattern algorithm in the test pattern algorithm library.
7. The apparatus of claim 1, wherein the pin-specific signal comprises: a control terminal pin signal, an address terminal pin signal and a data terminal pin signal;
the specific pin signal calibration sequence is a control end pin signal, an address end pin signal and a data end pin signal in sequence.
8. The apparatus of claim 7, wherein the control terminal pin signals comprise an output enable pin signal, a read/write control pin signal, and a chip select pin signal;
and the control end pin signal calibration sequence is the output enable pin signal, the read/write control pin signal and the chip select pin signal in sequence.
9. The apparatus of claim 1, wherein the apparatus is configured for static random access memory testing.
10. A test vector generation method, comprising:
acquiring interface information from a memory to be tested, and establishing a test function model of the memory to be tested according to the interface information;
acquiring a test graph calculation logic of the memory to be tested;
acquiring vector data information of a storage address of the memory to be tested, and acquiring pin definition of the memory to be tested;
extracting specific pin signals of the memory to be tested according to the vector data information of the memory address and the pin definition, and calculating test vector data of each memory address of the memory to be tested according to the specific pin signals of the memory to be tested, the test function model and the test pattern calculation logic;
and outputting the test vector data of each memory address of the memory to be tested.
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