CN114282677B - Main control equipment, slave control equipment and quantum computing system - Google Patents

Abstract

The disclosure relates to a master control device, slave control devices and a quantum computing system, wherein the master control device comprises a communication port, a first processing module and a first optical fiber port, the communication port is used for receiving first time sequence data sent by a time sequence editing device, the first processing module is used for embedding a master clock into the first time sequence data to obtain second time sequence data, the first optical fiber port is used for sending the second time sequence data to each slave control device, and the slave control device is connected with the master control device through an optical fiber link. The main control equipment, the slave control equipment and the quantum computing system provided by the disclosure send the second time sequence data to each slave control equipment through the optical fiber link, so that the problem of large attenuation of a long-distance transmission signal caused by a coaxial cable can be solved, and the problems of line complexity and high cost caused by the same can be solved.

Description

Main control equipment, slave control equipment and quantum computing system

Technical Field

The present disclosure relates to the field of quantum computing, and in particular, to a master control device, a slave control device, and a quantum computing system.

Background

In systems such as quantum computation, quantum precision measurement and radar, it is generally required that each slave control device simultaneously completes a corresponding operation indicated by the master control device, however, because an internal local clock between each slave control device may have an asynchronous condition, or a local clock between the master control device and the slave control device may have an asynchronous condition, each slave control device cannot simultaneously or more cooperatively complete a corresponding operation instruction according to an instruction of the master control device, thereby reducing practicality and reliability of the system. It can be seen how to enable each slave control device to complete a corresponding task at the same time has become one of the problems to be solved in the present day.

In view of the foregoing, there is a need in the art for a scheme that enables clock synchronization of a master control device and respective slave control devices.

Disclosure of Invention

In view of this, the present disclosure proposes a master control device, a slave control device, and a quantum computing system.

According to one aspect of the disclosure, a master control device in a quantum computing system is provided, the quantum computing system comprises a master control device and slave control devices, the master control device comprises a communication port and a first optical fiber port, the communication port is used for receiving first time sequence data sent by a time sequence editing device, the first time sequence data comprises first time sequence parameters used for generating a slave clock, the slave clock is a clock of the slave control device, a first processing module is used for embedding a master clock into the first time sequence data to obtain second time sequence data, the master clock is the clock of the master control device, and the first optical fiber port is used for sending the second time sequence data to each slave control device, wherein the slave control device is connected with the master control device through an optical fiber link.

Further, the optical fiber link is a single mode optical fiber link.

Further, the first timing parameter includes at least one of a number of timing pulses of the clock, a period length of the timing pulses of the clock, a pulse width of the timing pulses of the clock, and a delay parameter of a channel, wherein the channel includes a communication channel between the master control device and the slave control device, or a communication channel between the timing editing device and the master control device.

Further, the communication port is configured to delay a preset time according to the delay parameter of the channel, and then receive the first time sequence data.

Further, the first optical fiber port comprises a plurality of first optical fiber sub-ports used for sending the second time sequence data to each slave control device.

Further, the first processing module is configured to embed the master clock in the first time sequence data and convert the first time sequence data including the master clock into the serial second time sequence data.

According to another aspect of the disclosure, there is further provided a slave control device in a quantum computing system, the quantum computing system including a master control device and a slave control device, the slave control device including a second optical fiber port configured to receive second time sequence data sent by the master control device, the second time sequence data being generated by embedding a master clock into first time sequence data sent by a time sequence editing device by the master control device, wherein the first time sequence data includes a first time sequence parameter of a slave clock, and a second processing module configured to generate the slave clock according to the second time sequence data, wherein the master clock is a clock of the master control device, the slave clock is a clock of the slave control device, and the slave control device is connected to the master control device through an optical fiber link.

Further, the optical fiber link is a single mode optical fiber link.

Further, the first timing parameter includes at least one of a number of timing pulses of the clock, a period length of the timing pulses of the clock, a pulse width of the timing pulses of the clock, and a delay parameter of a channel, wherein the channel includes a communication channel between the master control device and the slave control device, or a communication channel between the timing editing device and the master control device.

Further, the second optical fiber port is configured to receive the second time sequence data after delaying for a preset time according to the delay parameter of the channel.

Further, the second processing module is used for obtaining a master clock according to the second time sequence data and generating a slave clock according to the master clock and the first time sequence parameters.

According to another aspect of the present disclosure, there is provided a quantum computing system including a timing editing device configured to generate first timing data, the first timing data including a first timing parameter for generating a slave clock, the slave clock being a clock of a slave control device, a master control device configured to embed a master clock in the first timing data transmitted by the timing editing device, generate second timing data, and transmit the second timing data to each slave control device through a first optical fiber port, wherein the master clock is a clock of the master control device, and at least one slave control device configured to receive the second timing data transmitted by the master control device through a second optical fiber port, and generate a slave clock according to the second timing data, wherein the slave control device is connected to the master control device through an optical fiber link.

The main control equipment, the slave control equipment and the quantum computing system provided by the disclosure send the second time sequence data to each slave control equipment through the optical fiber link, so that the problem of large attenuation of a long-distance transmission signal caused by a coaxial cable can be solved, and the problems of line complexity and high cost caused by the same can be solved. And further, the cost of systems such as quantum computing, quantum precision measurement, radar and the like can be reduced, and the energy sources are saved. In addition, the master control device can send the second time sequence data to the slave control device, and meanwhile, the master clock can send the master clock to the slave control device, so that the slave control device can acquire the second time sequence data according to the master clock synchronous with the master control device, each slave control device can be ensured to obtain the time sequence parameters in the second time sequence data more accurately, the accurate slave clock can be generated to control the work of each module in the slave control device, the operation precision of the slave control device is improved, and the phenomenon of shaking is avoided when the slave control device acquires signals sent by the master control device.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a schematic structural diagram of a quantum computing system according to an embodiment of the disclosure.

Fig. 2 is a schematic diagram of a connection relationship between a master control device and a plurality of slave control devices according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of another main control device according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a slave control device according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of another slave master control device according to an embodiment of the present disclosure.

Fig. 6 is a schematic structural diagram of another quantum computing system provided in an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a timing pulse in a standard mode according to an embodiment of the disclosure.

Fig. 8 is a schematic diagram of a timing pulse in an advanced mode provided by an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

In the existing quantum computing, quantum precision measuring and radar systems generally comprise a master control device and a plurality of slave control devices, and in the multi-bit quantum computing system, the manipulation of quantum bits generally requires the plurality of slave control devices to complete corresponding operations at the same time. However, since the master control device and each slave control device operate under their own local clocks, in the case where each slave control device receives a data signal from the master control device, there is a great probability that the clocks of the master control device and the slave control device are in an asynchronous relationship, that is, the slave control device acquires data transmitted by the master control device through a clock asynchronous with the master control device, resulting in a decrease in operation accuracy when the slave control device processes the data signal transmitted by the master control device. In the digital circuit, the external trigger signal is processed by the slave control device, that is, the slave control device usually uses the clock to directly collect the external trigger signal (corresponding to the data signal sent by the master control device), and since the external trigger signal and the local clock in the slave control device are generated according to different clock sources (that is, there is a possibility that the clocks are asynchronous), in the case that the slave control device collects the trigger signal sent by the master control device according to the local clock, the trigger signal sent by the master control device changes in the period of the local clock of the slave control device along with time, and thus when the slave control device collects the trigger signal according to the local time, a jitter phenomenon is generated in one clock period.

In addition to the above drawbacks, since the master control device and each slave control device typically transmit data signals through coaxial cables, if there is a long distance between the master control device and the slave control device, the data signals received by the slave control device will be attenuated greatly. For example, a digital array radar is an array of radar array elements in space, in which the digital array needs to digitize signals of each receiving and transmitting channel and transmit the signals to the back end for unified processing. Each digital array needs a master control device to control each array element (corresponding to a slave control device) according to a time sequence, so as to realize the transmission and the reception of the wave beam, and the master control device generally transmits control signals such as a preamble to each array element through a coaxial cable. The above method is simple, but in the case that the distance between the main control device and each array element is far, the signal attenuation is also increased, and thus the array element may not perform corresponding operation according to the received signal. In this case, although the attenuation degree of the signal can be reduced by adding a power amplifier and increasing the power of the data signal output by the main control device, the addition of the power amplifier increases the manufacturing cost of the system, and also complicates the circuit inside the system, increases the complexity of wiring, and increases the power of the data signal output by the main control device, which increases the power consumption of the system.

Based on the above drawbacks, the present disclosure provides a main control device 2, as shown in fig. 1-2, 4 and 6. Wherein the main control device 2 comprises a communication port 21, a first processing module 22 and a first fiber port 23.

Further, the communication port 21 is configured to receive first timing data transmitted by the timing editing apparatus 1, the first timing data including first timing parameters for generating the slave clock. Wherein the slave clock is the clock of the slave control device 3. Illustratively, the communication port 21 is a gigabit portal.

Further, the first processing module 22 is configured to embed a master clock in the first timing data to obtain second timing data. Wherein the master clock is the clock of the master control device. Illustratively, the first processing module 22 embeds the master clock into the first timing data via a clock embedding technique to generate the second timing data comprising the master clock.

The first timing parameter illustratively includes at least one of a number of timing pulses, a period length of the timing pulses, a pulse width of the timing pulses, and a channel delay parameter. Wherein the channel includes a communication channel between the master control apparatus 2 and the slave control apparatus 3 (see network channel in fig. 6), or a communication channel between the timing editing apparatus 1 and the master control apparatus 2 (see optical fiber links L1 to L3 in fig. 6).

For example, to enable the slave control device 3 to generate a determined slave clock from the second timing data, the first timing parameter may comprise at least the period length of the timing pulse and the pulse width of the timing pulse.

Alternatively, in the case where the above-described channel indicates a communication channel between the main control device 2 and the timing editing device 1, a channel delay parameter may be included in the first timing data, which may cause the main control device 2 to receive the first timing data after a preset time. Alternatively, the trigger input/output port 25 (as shown in fig. 3) on the main control device may be driven after a preset time according to the channel delay parameter, thereby controlling the time at which the main control device 2 receives the first timing data through the communication port 21. The preset time may be set according to an actual application scenario.

For example, in the digital array radar, each array element (corresponding to the slave control device 3 described above) is required to transmit a beam according to the data signal transmitted from the master control device 2 after 0.2 seconds, and then the trigger input/output port 25 of the master control device 2 can receive the first timing data transmitted from the timing editing device 1 after 0.2 seconds from the standard time by setting the channel delay parameter. Wherein, in this scenario, the standard time is the time when the channel delay parameter is 0, and the main control device 2 receives the first time data.

Further, the first fiber port 23 is used for sending the second timing data to each slave control device.

Illustratively, the slave control device 3 transmits the second timing data to the corresponding slave control device 3 through the first optical fiber port 23. Since the slave control device 3 is connected to the master control device 2 through an optical fiber link (see optical fiber links L1 to L3 in fig. 6), the first optical fiber port 23 achieves the purpose of transmitting the second time-series data to the corresponding slave control device 3 by transmitting the second time-series data to the corresponding optical fiber link. Referring to fig. 1, the first optical fiber port 23 transmits second timing data to the slave control device X1 through an optical fiber link L1, transmits second timing data to the slave control device X2 through an optical fiber link L2, and transmits second timing data to the slave control device X3 through an optical fiber link L3, wherein each slave control device may correspond to one optical fiber link.

Optionally, the optical fiber link is a single mode optical fiber link. In optical fiber communication, a single-mode optical fiber is an optical fiber for directly transmitting optical signals in a transverse mode, and the transmission speed of single-mode optical fiber data is high, and the transmission distance can reach more than 5 km, so that under the application scene of long-distance transmission, the scheme of connecting a main control device and a slave control device by adopting a single-mode optical fiber link can enhance the anti-interference capability in the signal transmission process, widen the bandwidth of a transmission band, and realize the purposes of conveniently deploying a time sequence control system in multiple nodes and long distances. Alternatively, a dual mode fiber may be used in a short-range transmission scenario.

Further, the slave control device 3 may generate a slave clock according to the first timing parameter and the master clock.

Illustratively, the slave control device 3 recovers the master clock of the master control device 2 according to the second time sequence data through the second processing module, and acquires the first time sequence parameters in the second time sequence data according to the master clock to obtain various parameters (such as the number of time sequence pulses of the clock, the period length of the time sequence pulses of the clock and the pulse width of the time sequence pulses of the clock) of the slave clock to generate the slave clock. The slave control device may operate at a prescribed timing according to the respective modules or elements corresponding to the slave clock control.

Illustratively, the above-mentioned time sequence editing device 1 sets the first time sequence parameter by control software (such as arbitrary waveform editing software, data acquisition software, etc.) related to quantum measurement and control, and transmits the first time sequence data containing the first time sequence parameter to the main control device 2 through network communication. Alternatively, the main control device 2 receives the first timing data through a communication port 21 (as shown in fig. 3) thereon. The slave control device 3 is an exemplary synchronous control system, and is configured to generate a slave clock according to a first timing parameter sent by the master control device to control the controlled device to work, so as to achieve the purpose that the master control device controls the plurality of slave control devices 3 to work simultaneously. Wherein each slave control device 3 can coordinate its operation at a specific timing based on the second timing data transmitted from the master control device 2.

The main control equipment provided by the disclosure sends the second time sequence data to each slave control equipment through the optical fiber link, so that the problem of large attenuation of long-distance transmission signals caused by the coaxial cable can be solved, and the problems of line complexity and high cost caused by the same can be solved. And further, the cost of systems such as quantum computing, quantum precision measurement, radar and the like can be reduced, and the energy sources are saved. In addition, the master control device provided by the disclosure can embed the master clock into the first time sequence data to generate the second time sequence data, so that the slave control device can acquire the clock data of the master control device, namely the master clock, according to the second time sequence data, and acquire the second time sequence data according to the master clock, so that each slave control device can acquire the second time sequence data through the clock synchronous with the master control device, more accurately acquire the time sequence parameters in the second time sequence data, generate accurate clock signals to control the work of each module in the slave control device, improve the operation precision of the slave control device, and avoid the occurrence of jitter phenomenon when the slave control device acquires the trigger signals.

Referring to fig. 2-3, in some embodiments of the present disclosure, the first optical fiber port 23 includes a plurality of first optical fiber sub-ports 231, where the plurality of first optical fiber sub-ports 231 are used to send the second timing data to each slave control device 3. Thereby, parallel control of a plurality of slave control devices 3 can be achieved.

Illustratively, in fig. 6, the master control device 2 transmits the second timing data to the slave control device X1 through the first optical fiber sub-port D1 via the optical fiber link L1, transmits the second timing data to the slave control device X2 through the first optical fiber sub-port D2 via the optical fiber link L2, and transmits the second timing data to the slave control device X3 through the first optical fiber sub-port D3 via the optical fiber link L3.

In some embodiments of the present disclosure, the main control device 2 is capable of setting channel parameters of the respective fiber links connected thereto, including channel calibration accuracy.

Further, the main control device 2 has an automatic channel calibration function, that is, in general, the main control device 2 can calibrate the channel states of a plurality of optical fiber links connected thereto to a preset state. In the preset state, the test precision of each channel is better than that of preset data (such as 500 ps). If more accurate calibration accuracy is required in the current application scenario (for example, the test accuracy of each channel is required to be better than 100 ps), the calibration accuracy of the channel can be improved by manually setting the channel calibration accuracy.

The main control equipment provided by the disclosure not only can automatically calibrate the difference between each channel connected with the main control equipment, so that the state of each channel is maintained in a state meeting the premise of transmitting data, but also can further improve the performance of each channel by manually adjusting the channel calibration precision, reduce the calibration error of the system and enable the main control equipment to be applied to the system with higher requirements on clock precision.

Referring to fig. 3, in some embodiments of the present disclosure, the first processing module 22 includes a standard clock generation module 211, a timestamp module 212, and a plurality of first high-speed serial interfaces 214.

Further, the standard clock generation module 211 is configured to generate a master clock according to a predetermined clock source.

For example, the preset clock source may be set according to actual conditions. Alternatively, the preset clock source may be an internal clock source of the main control device 2, or may be a high-precision clock source such as a GPS signal accessed by the main control device 2 through the serial port 24, the PPS input port 26, or the reference clock input port 27.

Alternatively, the standard clock generation module 211 may be an LMK04828 chip, which is an ultra-low phase noise clock chip capable of providing the master control device 2 with a clock having a better phase noise capability. Alternatively, the standard clock generation module 211 generates the master clock according to the clock control instruction output by the clock control module 215.

Further, the time stamp module 212 is configured to add time stamp information to the first time data, where the time source is the clock output by the standard clock generating module 211, and the time source of the time stamp module 212 may be from an internal local clock of the main control device 2, or may be from a high-precision clock source such as a GPS signal accessed by the serial port 24, the PPS input port 26, or the reference clock input port 27.

Further, the plurality of first communication modules 213 are configured to send the first time data added with the time stamp information to the corresponding first high-speed serial interfaces 214, respectively. Optionally, the first communication module 213 is configured to convert the first time data added with the time stamp information into a form that can be transmitted between the master control apparatus 2 and the slave control apparatus 3.

Further, the plurality of first high-speed serial interfaces 214 are configured to receive the data sent by the first communication module 213, embed a master clock in the first time-series data by using a clock embedding technology, so that the first time-series data includes the master clock, and convert the first time-series data embedded in the master clock into serial second time-series data.

Illustratively, a plurality of first high-speed serial interfaces 214 are respectively connected to one slave control device 3 through one first optical fiber sub-port 231, and the first high-speed serial interfaces 214 are used for converting parallel data (first time-series data) into serial data (second time-series data) embedded in a master clock of the master control device 2 and transmitting the converted serial data to the corresponding slave control device 3.

Further, the first fiber port 23 is used to send the second timing data to each slave control device 3. Optionally, the first optical fiber port 23 is configured to send the second timing data to the corresponding slave control device 3 through a single mode optical fiber link. Since the second time sequence data includes the master clock, in the case that the slave control device 3 receives the second time sequence data, the slave control device 3 can recover the master clock according to the second time sequence data and collect the first time sequence parameter in the second time sequence data according to the master clock, so that the slave control device 3 can collect the first time sequence parameter in the second time sequence data according to the clock synchronous with the master control device 2, which is equivalent to that each slave control device 3 can collect the second time sequence data according to the clock synchronous with the master control device 2, thereby realizing time synchronization between each slave control device 3 and the master control device 2 and further solving the jitter phenomenon generated in one clock period due to clock signal asynchronism.

Referring to fig. 1 and 4, according to another aspect of the present disclosure, there is also provided a slave control device 3 in a quantum computing system, the slave control device including a second optical fiber port 31 and a second processing module 32.

Further, the second optical fiber port 31 is used for receiving second timing data transmitted by the main control device 2, the second timing data being generated by the main control device 2 by embedding a master clock in the first timing data transmitted by the timing editing device 1. The first time sequence data comprises a first time sequence parameter of the slave clock, and the second time sequence data comprises the first time sequence parameter of the slave clock and the master clock.

Illustratively, the second fiber port 31 receives corresponding second timing data according to the fiber link to which it is connected. Referring to fig. 6, a second optical fiber port 31 in the slave control device X1 connected to the master control device through the optical fiber link L1 is used to receive second timing data in the optical fiber link L1. A second optical fiber port 31 in the slave control device X2 connected to the master control device through the optical fiber link L2 is used for receiving second timing data in the optical fiber link L2. A second optical fiber port 31 in the slave control device X3 connected to the master control device through the optical fiber link L3 is used for receiving the second timing data in the optical fiber link L3.

The master clock is a clock of the master control device, and the slave control device is connected with the master control device through an optical fiber link.

The first timing parameter includes at least one of a number of timing pulses of the clock, a period length of the timing pulses of the clock, a pulse width of the timing pulses of the clock, and a delay parameter of the channel. Wherein the channel comprises a communication channel between the master control device and the slave control device or a communication channel between the time sequence editing device and the master control device.

Alternatively, in the case where the above-described channel indicates a communication channel between the master control apparatus 2 and the slave control apparatus 3, a channel delay parameter may be included in the second timing data, which may delay the slave control apparatus 3 by a predetermined time to receive the timing data. The preset time may be set according to an actual application scenario.

In the digital array radar, for example, it is required that each array element (corresponding to the slave control device described above) transmits a beam according to the data signal transmitted from the master control device 2 after 0.2 seconds, and then the slave control device 3 can receive the second timing data transmitted from the master control device 2 after 0.2 seconds from the standard time by setting the channel delay parameter. Wherein in this scenario, the standard time is the time at which the second time series data is received from the control device 3 when the channel delay parameter is 0.

Further, the second processing module 32 is configured to obtain a master clock according to the second time sequence data, and generate a slave clock according to the master clock and the first time sequence parameter. The above-described slave clock is, for example, the clock of the slave control device 3.

Illustratively, the slave control device 3 recovers the master clock of the master control device 2 according to the second time sequence data through the second processing module 32, and acquires various parameters of the slave clock (such as the number of time sequence pulses of the clock, the period length of the time sequence pulses of the clock, and the pulse width of the time sequence pulses of the clock) according to the first time sequence parameters in the second time sequence data acquired by the master clock, so as to generate the slave clock. The slave control device 3 may operate on time according to the slave clock control corresponding to each module or element.

Details of the foregoing may correspond to the foregoing, and are not described herein.

The slave control equipment is connected with the master control equipment through the optical fiber link, so that the problem of large attenuation of long-distance transmission signals caused by the coaxial cable can be solved, and the problems of line complexity and high cost caused by the coaxial cable can be solved. And further, the cost of systems such as quantum computing, quantum precision measurement, radar and the like can be reduced, and the energy sources are saved. In addition, the secondary control equipment provided by the disclosure can also collect the second time sequence data according to the master clock, so that each secondary control equipment can collect the second time sequence data through the clock synchronous with the master control equipment, time sequence parameters in the second time sequence data can be obtained more accurately, the accurate secondary clock is generated to control the work of each module in the secondary control equipment, the operation precision of the secondary control equipment is improved, and the shaking phenomenon is avoided when the secondary control equipment collects the trigger signal.

Referring to fig. 4-5, in some embodiments, the second processing module 32 is configured to obtain a master clock according to the second timing data, and generate a slave clock according to the master clock and the first timing parameter.

Further, the second processing module 32 includes a data recovery module 321, a clock control module 322, and a clock chip 323.

Optionally, the data recovery module 321 is configured to recover the master clock according to the second timing data.

Illustratively, the data recovery module 321 includes a second high-speed serial interface 3211, a second communication module 3212, an ARM communication interface 3213, and a time information processing module 3214. The second high-speed serial interface 3211 is configured to receive the second timing data input by the second optical fiber port 31, and send the second timing data to the second communication module 3212. The second communication module 3212 is configured to parse the data signal output by the second high-speed serial interface 3211 according to a data transmission protocol, and send the parsed data signal to the time information processing module 3214 through the ARM communication interface 3213, so as to recover a master clock in the second timing signal through the time information processing module 3214.

Optionally, the clock information processing module 3214 is configured to recover the master clock in the second timing signal by CDR (i.e. Clock and Data Recovery, clock data recovery) technology. For ease of understanding, the CDR technique is briefly explained below.

The CDR technique mainly includes two aspects, namely, first, providing clock signals to each circuit at the receiver end, which is equivalent to the foregoing that the master control device 2 embeds the master clock into the second time sequence data by the clock embedding technique, and sends the second time sequence data embedded into the master clock to each slave control device 3. Second, the received signal is decided, so that the recovery and subsequent processing of the data signal are facilitated, which is equivalent to the recovery of the master clock in the second timing signal by the clock information processing module 3214. Since the optical signal is transmitted over a certain distance in the optical fiber link during the process of the master control apparatus 2 transmitting the second timing data to the slave control apparatus 3, the waveform thereof may be distorted to a certain extent. Since no clock signal is transmitted together with the optical signal, the signal received by the receiving end (e.g. from the control device 3) is a pulse with different lengths, and the main mode of clock recovery is mainly PLL (phase-locked loop) mode. The PLL mode recovers the clock signal based on the feedback principle, that is, compares the phase error of the output signal of the voltage-controlled oscillator with the phase error of the reference signal (e.g., the master clock in the second time-series data received from the control device 3), and generates a corresponding phase error voltage, so that the frequency of the voltage-controlled oscillator is consistent with the signal rate, and the voltage-controlled oscillator outputs the recovered clock signal (e.g., the master clock signal). The PLL circuit includes a phase detector (phase detector), a loop filter (loop filter), and a voltage controlled oscillator (voltage controlled oscillator, VCO for short). The phase detector is usually edge triggered, i.e., edge detector, and performs phase detection by comparing edges of two input signals (e.g., a main clock in the second timing data and an output signal of the voltage-controlled oscillator). Because the voltage output by the phase detector is an alternating current signal and the VCO cannot be directly controlled, the voltage signal needs to be filtered through the loop filter, and the loop filter mainly filters out high-frequency components in the voltage signal to obtain the control voltage of the VCO, so that the frequency of the VCO output signal is changed. After obtaining the correct clock signal by using the PLL, the received signal (e.g., the second time sequence data) may be collected (e.g., sampled, etc.), so as to recover the data signal.

Further, the clock control module 322 is configured to collect the second timing data according to the master clock recovered by the clock information processing module 3214 to obtain the first timing parameter (i.e. the timing parameter set by the timing editing apparatus 1 in the foregoing).

Further, the clock chip 323 is configured to generate a slave clock according to the first timing parameter, i.e., the clock chip 323 generates a corresponding slave clock according to each item of data in the timing parameter. Wherein the slave clock is used for indicating the corresponding device to execute the corresponding operation.

Optionally, the clock information processing module 3214 is further configured to send the recovered master clock to the second communication module 3212, where the second communication module 3212 outputs a 1pps signal according to the master clock, where the 1pps signal is output to a corresponding device through the SMA interface at the same time as the slave clock generated by the clock chip 323, and the device may calibrate the clock therein according to the 1pps signal.

The slave control device provided by the disclosure can recover the master clock through the second time sequence data and acquire the second time sequence data according to the master clock in the second time sequence data under the condition that the slave control device receives the second time sequence data, so that the master clock and the slave clock are synchronized. If each slave control device can collect the second time sequence data according to the master clock, the time synchronization between each slave control device and the master control device can be realized, and the jitter phenomenon generated in one clock period due to the asynchronization of clock signals is further solved. In addition, the slave control equipment can recover the master clock in the second time sequence data according to the CDR technology, so that the waveform of the second time sequence data is ensured to be distorted to a certain extent in the transmission process of the optical fiber link, the slave control equipment is not influenced by the waveform of the second time sequence data, the accurate master clock can still be obtained, and the second time sequence data can be acquired according to the master clock.

In another aspect of the present disclosure there is also provided a quantum computing system comprising a timing editing device 1, a master control device 2 and at least one slave control device 3.

Further, the timing editing apparatus 1 is configured to generate first timing data including first timing parameters for generating a slave clock, which is a clock of the slave control apparatus 3.

Further, the master control device 2 is configured to embed a master clock in the first timing data sent by the timing editing device 1, generate second timing data, and send the second timing data to each slave control device 3 through the first optical fiber port 23, where the master clock is a clock of the master control device 2.

Further, at least one slave control device 3 is configured to receive the second timing data sent by the master control device 2 through the second optical fiber port 31, and generate a slave clock according to the second timing data, where the slave control device 3 is connected to the master control device 2 through an optical fiber link.

The quantum computing system provided by the disclosure is connected with the master control equipment and each slave control equipment through the optical fiber link, so that the problem of large attenuation of long-distance transmission signals caused by the coaxial cable can be solved, and the problems of line complexity and high cost caused by the same can be solved. And further, the cost of systems such as quantum computing, quantum precision measurement, radar and the like can be reduced, and the energy sources are saved. In addition, the master control device in the quantum computing system can also send the second time sequence data to the slave control device, so that the slave control device can acquire the second time sequence data according to the master clock synchronous with the master control device, each slave control device can acquire the time sequence parameters in the second time sequence data more accurately, the accurate slave clock is generated to control the work of each module in the slave control device, the operation precision of the slave control device is improved, and the phenomenon of shaking is avoided when the slave control device acquires the trigger signal.

Referring to fig. 7-8, in some embodiments of the present disclosure, the above-described time sequential editing apparatus includes a standard mode and an advanced mode. Referring to fig. 7, the clock signal generated according to the timing parameters output in the standard mode has equal periods and pulse widths of the pulses, and the periods, pulse widths and channel delay parameters of the pulses can be set according to the actual application scenario. Referring to fig. 8, the clock signal generated according to the output timing parameter in the advanced mode can be flexibly generated according to the actual application scenario, that is, the generated clock signal may include at least one pulse with a period and/or a pulse width different from those of other pulses, or may generate clock signals with the same period and pulse width of each pulse, and the channel delay parameters of each pulse, pulse width and clock signal may be set according to the actual application scenario.

In the quantum computing system provided by the present disclosure, a time sequence editing apparatus includes a standard mode and an advanced mode. In the standard mode, the time sequence editing equipment can quickly generate a first time sequence parameter according to input data, so that time is saved, and the working efficiency of the quantum computing system is improved. In the advanced mode, parameters such as the period, the pulse width and the like of each pulse can be set through the time sequence editing equipment to generate a first time sequence parameter, so that the slave clock generated according to the first time sequence parameter can be more fit with an actual application scene.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (8)

1. A master control device in a quantum computing system, characterized in that the quantum computing system includes a master control device and slave control devices, the master control device comprising: A communication port is used to receive first timing data sent by a timing editing device. The first timing data includes first timing parameters for generating a slave clock, wherein the slave clock is the clock of a slave control device. The first processing module is used to embed a master clock into the first timing data to obtain the second timing data, wherein the master clock is the clock of the main control device; A first fiber optic port is used to send the second timing data to each slave control device, so that each slave control device generates a slave clock according to the second timing data; wherein, generating a slave clock according to the second timing data includes: obtaining a master clock according to the second timing data; and generating a slave clock according to the master clock and the first timing parameters; The slave control device is connected to the master control device via an optical fiber link; The master clock is generated by the standard clock generation module in the first processing module based on a preset clock source. The first timing parameters include: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameters, wherein the channel includes a communication channel between the master control device and the slave control device. The channel delay parameter is used to indicate the preset time delay required for receiving the second timing data from the second fiber optic port in the control device. 2. The main control device according to claim 1, wherein the optical fiber link is a single-mode optical fiber link. 3. The main control device according to claim 1, wherein the communication port is used to receive the first timing data after a preset delay according to the delay parameter of the channel. 4. The main control device according to claim 1, wherein the first optical fiber port comprises: a plurality of first optical fiber sub-ports for transmitting the second timing data to each of the slave control devices. 5. The main control device according to claim 4, wherein the first processing module is used for: The master clock is embedded in the first timing data, and the first timing data including the master clock is converted into serial second timing data. 6. A slave control device in a quantum computing system, characterized in that the quantum computing system includes a master control device and a slave control device, the slave control device comprising: The second fiber optic port is used to receive second timing data sent by the main control device. The second timing data is generated by the main control device embedding a master clock into the first timing data sent by the timing editing device. The first timing data includes first timing parameters of the slave clock. The master clock is generated by the main control device according to a preset clock source. The second processing module is used to generate a slave clock based on the second timing data. Wherein, the master clock is the clock of the master control device, the slave clock is the clock of the slave control device, and the slave control device is connected to the master control device via an optical fiber link; The first timing parameters include: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameters, wherein the channel includes a communication channel between the master control device and the slave control device. The second fiber optic port is used to receive the second timing data after a preset delay based on the channel's delay parameters; The second processing module is used for: The master clock is obtained based on the second timing data; A slave clock is generated based on the master clock and the first timing parameters. 7. The control device according to claim 6, wherein the optical fiber link is a single-mode optical fiber link. 8. A quantum computing system, characterized in that the quantum computing system comprises: A timing editing device is used to generate first timing data, the first timing data including first timing parameters for generating a slave clock, the slave clock being a clock of a slave control device; The main control device is used to embed a master clock into the first timing data sent by the timing editing device, generate second timing data, and send the second timing data to each slave control device through the first optical fiber port. The master clock is the clock of the main control device, and the master clock is generated by the main control device according to a preset clock source. At least one slave control device is configured to receive the second timing data sent by the master control device through a second optical fiber port, and generate a slave clock based on the second timing data, wherein generating the slave clock based on the second timing data includes: obtaining a master clock based on the second timing data; and generating a slave clock based on the master clock and the first timing parameters. The slave control device is connected to the master control device via an optical fiber link; The first timing parameters include: the number of timing pulses of the clock, the period length of the timing pulses of the clock, the pulse width of the timing pulses of the clock, and the channel delay parameters, wherein the channel includes a communication channel between the master control device and the slave control device. The second fiber optic port is used to receive the second timing data after a preset delay based on the channel's delay parameters.