CN114282472A - A kind of FPGA source code segmentation method and system - Google Patents

Abstract

The present invention provides a method and system for dividing a source code of an FPGA. The method includes: according to FPGA resource constraints, using a plurality of Module instances with the highest input and output delay order as initial seeds, and clustering the Module instances interconnected with them respectively. class to obtain multiple clusters; move the Module instance with the smallest input and output delay in each cluster to other clusters to form multiple new clusters that meet the FPGA resource constraints. Repeat this process to find out In the case of the least IO among different clusters, the cluster at this time is used as the result of segmentation. By adopting the technical scheme of the present invention, the segmentation process can be simplified and the segmentation performance can be improved.

Description

A kind of FPGA source code segmentation method and system

technical field

The invention relates to the field of FPGA, in particular to a method and system for dividing a source code of an FPGA.

Background technique

As modern SoC designs become more complex and transistors larger, it becomes equally difficult to verify the design. At present, the use of Emulation for simulation verification acceleration has become the mainstream direction of large-scale and ultra-large-scale integrated circuit design. This design uses multiple FPGA interconnection and cascading methods to accelerate the verification of user logic designs. Users need to try to divide a large design into several small designs, configure them into multiple FPGAs, and at the same time ensure that the logic functions of the entire design are correct at runtime and the performance is up to standard. The existing way of segmenting the user logic DUT logic is relatively simple and extensive segmenting using traditional algorithms, and even requires manual segmenting of the logic design. And most of the segmentation is based on gate-level netlist, which has poor performance and effect.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a source code segmentation method and system for FPGA based on Module instance (module instance), aiming at the defects of poor performance and effect of the above-mentioned prior art FPGA source code segmentation method.

In the embodiment of the present invention, a source code segmentation method of FPGA is proposed, which includes:

Analyze the entire RTL logic project to get the RTL level instantiation tree;

Calculate the resource consumption of each Module instance in the RTL level instantiation tree;

Analyze the input and output delay of each Module instance and sort them in descending order;

According to FPGA resource constraints, multiple Module instances with the highest input and output delays are used as initial seeds, and clustered with their interconnected Module instances to obtain multiple clusters;

Move the Module instance with the smallest input and output delay in each cluster to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraints. Repeat this iterative process to find the least IO between clusters. The cluster combination at this time is taken as the result of segmentation.

In the embodiment of the present invention, the resource consumption of each Module instance includes LUT, FF, RAM, and IO quantity resources.

In the embodiment of the present invention, the input and output delay of the Module instance is the sum of the input delay and the output delay of the Module instance, the input delay of the Module instance is the delay from the input of the Module instance to the first register, and the last register The delay to the output of the Module instance.

In the embodiment of the present invention, the Module instance with the smallest input and output delay in each cluster is moved to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraints, including:

Move the Module instance with the smallest input and output delay in a cluster to other clusters interconnected with it, and then calculate the number of IOs between clusters. If the number of IOs between clusters increases, return to the state before the move, and then Move the Module instance with the smallest input and output delay in the next cluster; if the number of IOs between clusters decreases, the cluster obtained at this time will be used as a new cluster.

In an embodiment of the present invention, a source code segmentation system for an FPGA is also provided, which includes:

The RTL analysis module is used to analyze the entire RTL logic project and obtain the RTL level instantiation tree;

A resource calculation module, used to calculate the resource consumption of each Module instance in the RTL level instantiation tree;

The delay analysis module is used to analyze the input and output delay of each Module instance and sort them in descending order;

The clustering module is used to use the multiple Module instances with the highest input and output delay order as the initial seeds according to the FPGA resource constraints, and cluster the connected Module instances respectively to obtain multiple clusters;

The split module is used to move the Module instance with the smallest input and output delay in each cluster to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraints. Repeat this iterative process to find out The cluster combination with the least IO among the clusters is used as the result of the segmentation.

In the embodiment of the present invention, the resource consumption of each Module instance includes LUT, FF, RAM, and IO quantity resources.

In the embodiment of the present invention, the input and output delay of the Module instance is the sum of the input delay and the output delay of the Module instance, and the input delay of the Module instance is the delay from the input of the Module instance to the first internal register, and the Module instance The output delay is the delay from the last internal register to the output of the Module instance.

In the embodiment of the present invention, the Module instance with the smallest input and output delay in each cluster is moved to other clusters interconnected with it to form multiple new clusters that meet the FPGA resource constraints, including:

Move the Module instance with the smallest input and output delay in a cluster to other clusters interconnected with it, and then calculate the number of IOs between clusters. If the number of IOs between clusters increases, return to the state before the move, and then Move the Module instance with the smallest input and output delay in the next cluster; if the number of IOs between clusters decreases, the cluster obtained at this time will be used as a new cluster.

Compared with the prior art, in the technical solution of the present invention, the module instance is used as the basic unit to perform logical segmentation, which simplifies the segmentation complexity; the delay between the Module instances is considered, and only the delay and the register input from the instance input to the register are analyzed. Delay to output, divided by timing drive. The final result of the division is that the division IO is as small as possible, and the line delay of the division is as low as possible, which improves the timing performance of the logic design.

Description of drawings

FIG. 1 is a flowchart of a method for dividing a source code of an FPGA according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an RTL-level instantiation tree according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of resource calculation according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a delay time of a module example according to an embodiment of the present invention.

FIG. 5 is a schematic structural diagram of a system for dividing a source code of an FPGA according to an embodiment of the present invention.

Detailed ways

As shown in FIG. 1 , in an embodiment of the present invention, a method for dividing a source code of an FPGA is proposed, which includes steps S1-S5. Each of them will be described below.

Step S1: Analyze the entire RTL logic project to obtain an RTL hierarchical instantiation tree.

As shown in Figure 2, the RTL hierarchical instantiation tree is composed of multiple tree-like distributed Module instance nodes. Each Module instance node is associated with at least one other Module instance node.

Step S2: Calculate the resource consumption of each Module instance in the RTL hierarchical instantiation tree.

The resource consumption of each Module instance includes LUT (look up table, lookup table), FF (FlipFlop, trigger), RAM (random access memory, random access memory) and IO (Input Output, input and output) quantity resources.

For example, the resources of the adder Module instance in Figure 3 are as follows:

Lookup Table LUT: 0

Full Adder Adder: 7

Flip Flop: 7

RAM: 0

IO: 20.

Step S3: Analyze the input and output delays of each Module instance, and sort them in descending order.

As shown in Figure 4, the input and output delay of the Module instance is the sum of the input delay and output delay of the Module instance, and the input delay of the Module instance is the delay from the input of the Module instance to the first internal register. The output delay is the delay from the last internal register to the output of the Module instance. There are many connections between instances. The specific calculation method is to calculate the average delay of all other input connections except the clock line as the input delay, and calculate the average delay of all other output connections as the output delay. During the segmentation process, the path with higher delay has lower segmentation probability.

Step S4: According to the FPGA resource constraints, multiple Module instances with high input and output delays are used as initial seeds, and the Module instances interconnected with them are clustered to obtain multiple clusters.

It should be noted that, in the process of segmentation, the higher the delay path, the lower the segmentation probability, the multiple Module instances with the highest input and output delay order can be used as initial seeds to generate multiple clusters.

Step S5: Move the Module instance with the smallest input and output delay in each cluster to other clusters to form multiple new clusters that meet the FPGA resource constraints. Repeat this process to find the IO between different clusters In the least case, the clustering at this time is used as the result of segmentation.

It should be noted that the multiple clusters generated in step S4 are not optimal clusters, so fine-tuning is required. Move the Module instance with the smallest input and output delay in each cluster to other clusters to form multiple new clusters that meet the FPGA resource constraints, including:

Move the Module instance with the smallest input and output delay in a cluster to other clusters interconnected with it, and then calculate the number of IOs between clusters. If the number of IOs between clusters increases, return to the state before the move, and then Move the Module instance with the smallest input and output delay in the next cluster; if the number of IOs between clusters decreases, the cluster obtained at this time is used as a new cluster, and this iterative process is repeated until the IO between clusters is found. In the least case, the clustering at this time is used as the result of the segmentation, and multiple HDL files configured in the FPGA are output according to the result of the segmentation.

As shown in FIG. 5 , corresponding to the above-mentioned FPGA source code segmentation method, an embodiment of the present invention further provides a FPGA source code segmentation system, which includes an RTL analysis module 1, a resource calculation module 2, a delay analysis module 3, Clustering module 4 and segmentation module 5.

The RTL analysis module 1 is used to analyze the entire RTL logic project to obtain the RTL level instantiation tree.

The resource calculation module 2 is configured to calculate the resource consumption of each Module instance in the RTL level instantiation tree.

The delay analysis module 3 is used to analyze the input and output delay of each Module instance, and perform descending sorting.

The clustering module 4 is configured to, according to the FPGA resource constraints, use the multiple Module instances with the highest input and output delay sorting as initial seeds, and perform clustering on the Module instances interconnected with them respectively to obtain multiple clusters.

The described segmentation module 5 is used to move the Module instance with the smallest input and output delay in each cluster to other clusters interconnected with it, to form a plurality of new clusters that meet the FPGA resource constraints, and to find out the clusters The cluster combination with the least amount of IO at this time is used as the result of the segmentation.

To sum up, in the technical solution of the present invention, the module instance is used as the basic unit to perform logical segmentation, which simplifies the segmentation complexity; the delay between the Module instances is considered, and only the delay from instance input to register and register to output are analyzed. The delay is driven by timing. The final result of the division is that the division IO is as small as possible, and the line delay of the division is as low as possible, which improves the timing performance of the logic design.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (8)

1. A source code segmentation method of an FPGA is characterized by comprising the following steps:

analyzing the whole RTL logic project to obtain an RTL hierarchical instantiated tree;

calculating the resource consumption of each Module instance in the RTL level instantiated tree;

analyzing the input and output delay of each Module instance, and performing descending sorting;

according to the FPGA resource constraint condition, taking a plurality of Module instances with the input/output delay sequencing at the front as initial seeds, and respectively clustering the initial seeds with the Module instances interconnected with the initial seeds to obtain a plurality of clusters;

and (3) moving the Module instance with the minimum input and output delay in each cluster to other clusters interconnected with the Module instance to form a plurality of new clusters meeting the FPGA resource constraint condition, repeating the iteration process, finding out the cluster combination with the minimum IO among the clusters, and taking the cluster combination at the moment as a segmentation result.

2. The method of FPGA source code partitioning of claim 1, wherein the resource consumption of each Module instance includes LUT, FF, RAM and IO amount resources.

3. The method of claim 1, wherein the input/output delay of the Module instance is a sum of the input delay and the output delay of the Module instance, the input delay of the Module instance is a delay from an input of the Module instance to a first internal register, and the output delay of the Module instance is a delay from a last internal register to an output of the Module instance.

4. The method for partitioning the source code of the FPGA of claim 1, wherein the Module instance with the smallest input/output delay in each cluster is moved to other clusters interconnected with the Module instance to form a plurality of new clusters that meet FPGA resource constraints, comprising:

moving the Module instance with the minimum input and output delay in a certain cluster to other clusters interconnected with the cluster, then calculating the number of IOs between clusters, if the number of IOs between clusters is increased, returning to the state before moving, and then moving the Module instance with the minimum input and output delay in the next cluster; and if the number of IO between clusters is reduced, taking the cluster obtained at the moment as a new cluster.

5. A source code segmentation system of an FPGA, comprising:

the RTL analysis module is used for analyzing the whole RTL logic project to obtain an RTL level instantiated tree;

the resource calculation Module is used for calculating the resource consumption of each Module instance in the RTL level instantiated tree;

the delay analysis Module is used for analyzing the input and output delay of each Module instance and performing descending sorting;

the clustering Module is used for clustering a plurality of Module instances which are in front of the input-output delay sequencing as initial seeds respectively with the Module instances interconnected with the initial seeds according to the FPGA resource constraint condition to obtain a plurality of clusters;

and the segmentation Module is used for moving the Module instance with the minimum input/output delay in each cluster to other clusters interconnected with the cluster, forming a plurality of new clusters according with the FPGA resource constraint condition, repeating the iteration process, finding out the cluster combination with the minimum IO among the clusters, and taking the cluster combination at the moment as a segmentation result.

6. The FPGA source code partitioning system of claim 5, wherein the resource consumption of each Module instance comprises LUT, FF, RAM and IO amount resources.

7. The FPGA source code partitioning system of claim 5, wherein the input/output delay of the Module instance is a sum of an input delay and an output delay of the Module instance, the input delay of the Module instance is a delay from an input of the Module instance to a first internal register, and the output delay of the Module instance is a delay from a last internal register to an output of the Module instance.

8. The FPGA source code partitioning system of claim 5, wherein the moving of the Module instance with the lowest I/O latency in each cluster to other clusters interconnected therewith forms a plurality of new clusters that meet FPGA resource constraints, comprises:

moving the Module instance with the minimum input and output delay in a certain cluster to other clusters interconnected with the cluster, then calculating the number of IOs between clusters, if the number of IOs between clusters is increased, returning to the state before moving, and then moving the Module instance with the minimum input and output delay in the next cluster; and if the number of IO between clusters is reduced, taking the cluster obtained at the moment as a new cluster.

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