CN114265031A

CN114265031A - High-speed real-time data acquisition system of radar in well based on FPGA

Info

Publication number: CN114265031A
Application number: CN202111463858.8A
Authority: CN
Inventors: 马春光; 聂凯; 赵俊宇; 周静晗; 刘国; 罗勇
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2021-12-03
Filing date: 2021-12-03
Publication date: 2022-04-01

Abstract

The invention discloses an in-well radar high-speed real-time data acquisition system based on an FPGA (field programmable gate array), and belongs to an ultra-wideband radar system. The system comprises an FPGA control module, an integrated data receiving and collecting module, a data storage module, a data transmission module and a digital-analog hybrid power supply module. The system disclosed by the invention realizes the integration of high-speed data receiving and acquisition, data storage and transmission in the radar system in the well, and solves the problems of poor stability, low integration level and weak anti-interference capability in the traditional receiving-acquiring separated design; the design is different from the prior design that an analog system and a digital system are separately designed, and is changed into the design of a digital-analog mixed circuit, so that the system stability is further improved; meanwhile, the gain of the low-noise amplifier can be automatically adjusted according to the state of the collected target, and the reduction of sampling precision caused by the saturation or distortion of data collected by the ADC is avoided.

Description

High-speed real-time data acquisition system of radar in well based on FPGA

Technical Field

The invention belongs to an ultra-wideband radar system, and particularly relates to an in-well radar high-speed real-time data acquisition system based on an FPGA (field programmable gate array).

Background

The radar in the well is one of radar systems widely applied in a radar family, and mainly comprises two working systems, namely a time domain radar and a frequency domain radar, wherein the two working systems are the mainstream systems of the current research. An excitation signal of the radar in the time domain well is mainly a Gaussian-like pulse signal, and belongs to the category of ultra-wideband radar systems. The invention is suitable for an underground nondestructive detection in-well radar system, which transmits nanosecond-level first-order Gaussian pulse signals to the well periphery through an ultra-wideband transmitting antenna, the pulse signals are reflected when encountering media with different electrical parameters (dielectric constant and conductivity) in the well periphery propagation process, and the stratum information and the space target information of a detected area can be extracted by processing reflected wave signals received by a receiving antenna. Compared with other conventional geophysical exploration methods, the radar in the well can enter the underground deep along the borehole, and has the advantages of long detection distance, high resolution and high detection efficiency. Therefore, the radar in the well is widely applied to the industries of hydrogeological survey, nuclear waste storage site selection, underground unexplosive object detection, tunnel driving advanced prediction, oil and gas resource exploration and the like.

Although radar technology in wells has been vigorously developed, there are some technical problems to be overcome.

(1) The receiver, the data acquisition board and the data transmission module of the traditional well radar system generally adopt a separated architecture, namely, signals received by the receiver are transmitted to the data acquisition unit through a cable for acquisition. The system architecture has the advantages of weak stability, low integration level, poor portability and weak interference resistance.

(2) In order to realize adjustable gain amplification, a receiver of a conventional radar in a well usually realizes adjustment of corresponding amplification factors in a radio frequency switch switching mode, and a large number of radio frequency switches need to be introduced into a system, so that the problems of signal transmission loss and crosstalk between links are caused, and the stability of the system is also deteriorated.

(3) The traditional radar in the well mainly adopts an equivalent sampling data acquisition mode, and the sampling mode is mainly based on the assumption that a radar system is slow in travelling speed in an exploration process and can be equivalent to a system static relative to a transmitting repetition frequency. In actual work, however, the radar system in the well does not have completely consistent repetition frequency signals, and due to the randomness of hardware triggering, the equivalent acquisition result is often misaligned. In addition, hardware modules such as signal synchronization and the like are added in the equivalent acquisition system, and the signal-to-noise ratio and the stability of the system are reduced. For example, in the patent of invention granted by the university of electronic technology, "an FPGA-based immediate equivalent acquisition system" (CN110836993B), due to the selection of an equivalent acquisition scheme, a pulse output module and a pulse stretching module are introduced into the system, so that the complexity of hardware connection and program design of the whole system is increased, and the stability of the system is reduced; and a time interval measuring module is introduced, so that the signal-to-noise ratio of the system is reduced, and the cost of the system is increased.

(4) The traditional radar system in the well adopts communication modes such as a serial port and the like to transmit data, and has the problems of short data transmission distance, low transmission speed, large signal attenuation and weak anti-interference capability.

In conclusion, the design of the high-speed real-time data acquisition system for the in-well radar, which can solve the problems, has important engineering application value.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides an FPGA-based high-speed real-time data acquisition system for a radar in a well.

The technical scheme adopted by the invention is as follows:

the high-speed real-time data acquisition system for the in-well radar based on the FPGA is characterized by comprising an FPGA control module, an integrated data receiving and acquiring module, a data storage module, a data transmission module and a digital-analog hybrid power supply module.

The FPGA control module is used for receiving the high-speed real-time data sent by the data receiving and collecting module and sending the high-speed real-time data to the data storage module and the data transmission module; and the history data storage module is also used for receiving a historical data calling instruction transmitted by the data transmission module and sending the historical data stored in the data storage module to the data transmission module according to the instruction.

The data receiving and collecting module receives high-speed real-time data of radar echo signals in the well through the antenna and sends the collected high-speed real-time data to the FPGA control module.

The data storage module receives and stores the high-speed real-time data sent by the FPGA control module, and sends the stored historical data to the FPGA control module according to the historical data calling instruction of the FPGA control module.

The data transmission module sends the high-speed real-time data and the historical data transmitted by the FPGA control module to the upper computer, and sends a historical data calling instruction of the upper computer to the FPGA control module.

And the digital-analog hybrid power supply module uniformly distributes a digital power supply and an analog power supply and is used for supplying power to the FPGA control module, the data receiving and collecting module, the data storage module and the data transmission module.

Furthermore, the data receiving and collecting module comprises a multi-channel preprocessing unit, a low-noise amplifying unit and a signal analog-to-digital conversion unit; the multi-channel preprocessing unit is used for receiving in-well radar echo signals sent by the 4 antennas respectively, performing signal amplitude limiting processing and radio frequency switch selection processing, and outputting two paths of preprocessed signals; the low-noise amplification unit is used for amplifying the voltage amplitudes of the two paths of preprocessing signals, inhibiting noise and outputting two paths of low-noise signals; and the signal analog-to-digital conversion unit is used for transmitting the low-noise signal to the double-channel ADC for real-time acquisition and finally outputting two paths of high-speed real-time data.

Furthermore, the multi-channel preprocessing unit comprises 4 attenuators and 2 alternative radio frequency switches; one attenuator is used for amplitude limiting of radar echo signals in one well respectively to obtain four paths of radio frequency signals; two paths of radio frequency signals enter a first alternative radio frequency switch and output a path of preprocessing signals; the other two paths of radio frequency signals enter a second alternative radio frequency switch and output the other path of preprocessing signals.

Furthermore, the attenuator is a pi-type attenuator formed by non-inductive resistance.

Further, the low noise amplification processing unit comprises two paths of two-stage low noise amplifiers; the first-stage amplifier is a low-noise amplifier with fixed gain, and the second-stage amplifier is a low-noise amplifier with programmable gain.

Further, the signal analog-to-digital conversion unit comprises two single-ended signal to differential signalers Diff, a dual-channel analog-to-digital converter ADC and a phase-locked loop PLL. The phase-locked loop PLL provides a clock for the dual-channel analog-to-digital converter ADC, the two single-ended signal differential signal converters Diff convert the low-noise signals from the single-ended signals into differential signals, and the differential signals are transmitted to the dual-channel analog-to-digital converter ADC for real-time acquisition, so that two paths of high-speed real-time data are output.

Further, the data transmission module comprises a data channel selection unit and an optical communication control unit. The data channel selection unit selects high-speed real-time data in the FPGA control module or historical data in the data storage module to transmit to the optical communication control unit, and sends an upper computer instruction transmitted by the optical communication control unit to the FPGA control module; the optical communication control unit is used for configuring the format of transmission data and directly transmitting data and instructions with an upper computer through optical fibers.

Further, the digital-analog hybrid power supply module comprises a 12V direct-current power supply, and a first voltage conversion chip, a second voltage conversion chip and a third voltage conversion chip which are connected with the direct-current power supply; the first voltage conversion chip converts a 12V direct-current power supply into 5V direct-current voltage, then converts the 5V direct-current voltage into 1V direct-current voltage through a 5V to 1V direct-current voltage chip to supply power for the FPGA control module, and simultaneously converts the 5V to 1.5V direct-current voltage into 1.5V direct-current voltage through a 5V to 1.5V direct-current voltage chip to supply power for the data storage module; the second voltage conversion chip converts a 12V direct-current power supply into 3.3V direct-current voltage to supply power to the data transmission module; the third voltage conversion chip converts a 12V direct-current power supply into 5V direct-current voltage, then converts the 5V direct-current voltage into 2.5V direct-current voltage through a 5V to 2.5V direct-current voltage chip, supplies power for the low-noise amplifier, converts the 5V to 1.9V direct-current voltage into 1.9V direct-current voltage through two 5V to 1.9V direct-current voltage chips, and independently supplies power for an analog part and a digital part of the dual-channel analog-to-digital converter ADC.

The invention has the beneficial effects that:

(1) the integration of high-speed data receiving and acquisition, data storage and transmission in the radar system in the well is realized, and the problems of poor stability, low integration level and weak anti-interference capability in the traditional receiving-acquisition separated design are solved.

(2) The design is separated aiming at the prior analog and digital systems, and is changed into a digital-analog mixed circuit design, so that the system stability is further improved.

(3) The FPGA can automatically adjust the gain of the low-noise amplifier according to the state of the acquired target, and the reduction of sampling precision caused by the saturation or distortion of the data acquired by the ADC is avoided.

(4) A high-speed ADC real-time acquisition scheme is designed, the influence of random factors such as jitter in equivalent sampling is avoided, and a target echo signal can be acquired completely. Aiming at the real-time acquisition scheme, the storage resources on the FPGA chip cannot meet the data cache capacity, so the DDR3 storage unit is additionally arranged to solve the problem.

(5) The invention adopts the optical fiber to transmit data, improves the data transmission rate, and has the characteristics of long transmission distance, low attenuation and the like.

Drawings

FIG. 1 is an overall block diagram of the system of the present invention.

FIG. 2 is a pictorial representation of the system of the present invention.

Fig. 3 is a schematic diagram of a data receiving and collecting module.

FIG. 4 is a schematic diagram of data storage.

Fig. 5 is a schematic diagram of a digital-analog hybrid power supply.

FIG. 6 is a flow chart of the system real-time acquisition logic.

Detailed Description

The following provides a more detailed description of the embodiments and the operation of the present invention with reference to the accompanying drawings.

The embodiment is a high-speed real-time data acquisition system of a radar in a well based on an FPGA, and the system comprises an FPGA control module, an integrated data receiving and acquiring module, a data storage module, a data transmission module and a digital-analog hybrid power supply module.

The data storage module receives and stores the high-speed real-time data sent by the FPGA control module, and sends the stored historical data to the FPGA control module according to a historical data calling instruction of the FPGA control module; the memory module is composed of 2 cascaded memory chips DDR 3.

The data receiving and collecting module comprises a multi-channel preprocessing unit, a low-noise amplifying unit and a signal analog-to-digital conversion unit; the multi-channel preprocessing unit is used for receiving in-well radar echo signals sent by the 4 antennas respectively, performing signal amplitude limiting processing and radio frequency switch selection processing, and outputting two paths of preprocessed signals; the low-noise amplification unit is used for amplifying the voltage amplitudes of the two paths of preprocessing signals, inhibiting noise and outputting two paths of low-noise signals; and the signal analog-to-digital conversion unit is used for transmitting the low-noise signal to the double-channel ADC for real-time acquisition and finally outputting two paths of high-speed real-time data.

The multichannel preprocessing unit comprises 4 attenuators and 2 alternative radio frequency switches; one attenuator is used for amplitude limiting of radar echo signals in one well respectively to obtain four paths of radio frequency signals; then every two paths of radio frequency signals enter 1 alternative radio frequency switch, and one path of preprocessing signals is output respectively. The attenuator is a pi-type attenuator formed by non-inductive resistance.

The low-noise amplification unit comprises two paths of two-stage low-noise amplifiers; the first-stage amplifier is a low-noise amplifier with fixed gain, and the second-stage amplifier is a low-noise amplifier with programmable gain.

The signal analog-to-digital conversion unit comprises two single-ended signal to differential signal converters Diff, a dual-channel analog-to-digital converter ADC and a phase-locked loop PLL. The phase-locked loop PLL provides a clock for the dual-channel analog-to-digital converter ADC, the two single-ended signal differential signal converters Diff convert the low-noise signals from the single-ended signals into differential signals, and the differential signals are transmitted to the dual-channel analog-to-digital converter ADC for real-time acquisition, so that two paths of high-speed real-time data are output.

The data transmission module comprises a data channel selection unit and an optical communication control unit. The data channel selection unit selects high-speed real-time data in the FPGA control module or historical data in the data storage module to transmit to the optical communication control unit, and sends an upper computer instruction transmitted by the optical communication control unit to the FPGA control module; the optical communication control unit is used for configuring the format of transmission data and directly transmitting data and instructions with an upper computer through optical fibers.

The digital-analog hybrid power supply module comprises a 12V direct-current power supply, and a first voltage conversion chip, a second voltage conversion chip and a third voltage conversion chip which are connected with the digital-analog hybrid power supply module; the first voltage conversion chip converts a 12V direct-current power supply into 5V direct-current voltage, then converts the 5V direct-current voltage into 1V direct-current voltage through a 5V to 1V direct-current voltage chip to supply power for the FPGA control module, and simultaneously converts the 5V to 1.5V direct-current voltage into 1.5V direct-current voltage through a 5V to 1.5V direct-current voltage chip to supply power for the data storage module; the second voltage conversion chip converts a 12V direct-current power supply into 3.3V direct-current voltage to supply power to the data transmission module; the third voltage conversion chip converts a 12V direct-current power supply into 5V direct-current voltage, then converts the 5V direct-current voltage into 2.5V direct-current voltage through a 5V to 2.5V direct-current voltage chip, supplies power for the low-noise amplifier, converts the 5V to 1.9V direct-current voltage into 1.9V direct-current voltage through two 5V to 1.9V direct-current voltage chips, and independently supplies power for an analog part and a digital part of the dual-channel analog-to-digital converter ADC.

After the system is powered on, the FPGA control module sends control instructions to be respectively transmitted to the data receiving and collecting module, the data storage module and the data transmission module, and initialization configuration of hardware in each module is completed. According to the instruction transmitted by the FPGA control module, the data receiving and acquiring module completes the configuration of a PLL frequency division controller, a charge pump output circuit controller and clock output synchronization, and the configuration of a calibration function, an acquisition range, a multiplexing mode and a working mode of a dual-channel digital-to-analog converter (ADC); the data storage module completes cascade configuration of 2 storage chips DDR 3; and the data transmission module completes the configuration of a communication protocol and a data transmission rate between the optical communication module and the upper computer.

When the device works normally, two channels of the dual-channel digital-to-analog converter ADC independently and parallelly acquire high-speed data in real time. The data receiving and collecting module receives data converted by the dual-channel digital-to-analog converter ADC at the frequency of 100MHz and transmits the data to the FPGA control module, when the data received by the FPGA control module is higher than a preset value, collection of radar echo signals is completed, each radar echo signal collects 1024 data, each data is 48 bits, the repetition frequency counter starts counting at the moment, when the counting is carried out for 100 times, bit width conversion of the data is carried out, the data is converted into 256bit width from 48 bits, and meanwhile, the repetition frequency counter is reset.

And on one hand, the FPGA control module transmits the data to the data storage module for storage, and the data is used for quick transmission and signal processing in the later period. And on the other hand, the data which is received in real time is transmitted to the data transmission module, and the data transmission module packs and sends the received data to the upper computer according to the fixed communication frame and displays the data on the upper computer in real time. In the process, the waveform counter continuously counts, when the count reaches 72K, the whole acquisition process is finished, and the FPGA control module reports the working state of the hardware.

Meanwhile, the upper computer can send and read data requests to the FPGA control module in the whole acquisition process, the data transmission module transmits data stored in the DDR3 or signals received in real time through the data channel selection module according to instructions, and the data or the signals are transmitted to the upper computer through optical fibers for display after passing through the FIFO of the data bit width conversion buffer unit.

Claims

1. a high-speed real-time data acquisition system based on FPGA in the well radar, is characterized in that, this system comprises FPGA control module, integrated data reception and acquisition module, data storage module, data transmission module and digital-analog hybrid power supply module;

The FPGA control module is used for receiving the high-speed real-time data sent by the data receiving and collecting module, and sending the high-speed real-time data to the data storage module and the data transmission module; and is also used for receiving the retrieval historical data transmitted by the data transmission module instruction, and send the historical data stored in the data storage module to the data transmission module according to the instruction;

The data receiving and collecting module receives the high-speed real-time data of the radar echo signal in the well through the antenna, and sends the collected high-speed real-time data to the FPGA control module;

The data storage module receives and stores the high-speed real-time data sent by the FPGA control module, and sends the stored historical data to the FPGA control module according to the retrieving historical data instruction of the FPGA control module;

The data transmission module sends the high-speed real-time data and historical data transmitted by the FPGA control module to the host computer, and sends the retrieving historical data instruction of the host computer to the FPGA control module;

The digital-analog hybrid power supply module uniformly distributes the digital power supply and the analog power supply for supplying power to the FPGA control module, the data receiving and collecting module, the data storage module and the data transmission module.

2. The FPGA-based high-speed real-time data acquisition system for radar in wells as claimed in claim 1, wherein the data receiving and acquisition module comprises a multi-channel preprocessing unit, a low-noise amplifying unit, and a signal analog-to-digital conversion unit ; wherein, the multi-channel preprocessing unit is used to receive the radar echo signals in the well sent by the four antennas, perform signal limiting processing and radio frequency switch selection processing, and output two preprocessing signals; the low-noise amplifying unit , used to amplify the voltage amplitudes of the two preprocessed signals while suppressing noise, and output two low-noise signals; the signal analog-to-digital conversion unit is used to transmit the low-noise signals to the dual-channel ADC for real-time collection, and finally Output two high-speed real-time data.

3. The FPGA-based high-speed real-time data acquisition system for downhole radar according to claim 2, wherein the multi-channel preprocessing unit comprises 4 attenuators and 2 radio frequency switches; wherein , an attenuator respectively limits the amplitude of one channel of radar echo signals in the well, and obtains four channels of radio frequency signals; two channels of RF signals enter the first two-way RF switch, and output one channel of preprocessing signal; the other two channels of RF signals enter the first channel of radio frequency signal. Two optional RF switches, output another pre-processed signal.

4 . The high-speed real-time data acquisition system for downhole radar based on FPGA according to claim 3 , wherein the attenuator is a π-type attenuator composed of no inductive resistance. 5 .

5. The FPGA-based high-speed real-time data acquisition system for downhole radar according to claim 2, wherein the low-noise amplifying unit comprises two-way two-stage low-noise amplifiers; wherein the first-stage amplifier is a fixed gain The second-stage amplifier is a low-noise amplifier with programmable gain.

6. The high-speed real-time data acquisition system of FPGA-based well radar according to claim 2, wherein the signal analog-to-digital conversion unit comprises two single-ended signal-to-differential annunciators Diff, dual-channel analog-to-digital conversion unit The converter ADC and the phase-locked loop PLL; the phase-locked loop PLL provides the clock for the dual-channel analog-to-digital converter ADC, and the two single-ended signal to differential signal converter Diff converts the low-noise signal from a single-ended signal to a differential signal, and transmits it to The dual-channel analog-to-digital converter ADC performs real-time acquisition, thereby outputting two high-speed real-time data.

7. The FPGA-based high-speed real-time data acquisition system for radar in wells according to claim 1, wherein the data transmission module comprises a data channel selection unit and an optical communication control unit; wherein the data channel selection unit, Select high-speed real-time data in the FPGA control module or historical data in the data storage module to transmit to the optical communication control unit, and send the host computer instructions transmitted by the optical communication control unit to the FPGA control module; the optical communication control unit is used for configuring The format of transmission data, and the host computer directly transmits data and instructions through optical fiber.

8. The FPGA-based high-speed real-time data acquisition system for in-well radars as claimed in claim 2, wherein the digital-analog hybrid power supply module comprises a 12V DC power supply, and a first voltage conversion chip connected to it, The second voltage conversion chip and the third voltage conversion chip; the first voltage conversion chip converts the 12V DC power supply into a 5V DC voltage, and then converts the 5V to 1V DC voltage chip into a 1V DC voltage to supply power for the FPGA control module, and at the same time The 5V to 1.5V DC voltage chip is converted into a 1.5V DC voltage to supply power to the data storage module; the second voltage conversion chip converts the 12V DC power into a 3.3V DC voltage to supply power to the data transmission module; the third voltage The conversion chip converts 12V DC power into 5V DC voltage, and then converts it into 2.5V DC voltage through the 5V to 2.5V DC voltage chip to power the low-noise amplifier, and simultaneously converts it into 1.9V DC through two 5V to 1.9V DC voltage chips. Voltage, which independently powers the analog and digital parts of the dual-channel analog-to-digital converter ADC.