CN114256374B - Avalanche photodetector and preparation method thereof - Google Patents

Abstract

The application provides an avalanche photodetector and a preparation method thereof. Wherein the avalanche photodetector includes: a substrate, a surface of which includes a first semiconductor layer; the second semiconductor layer is positioned on the substrate, the first semiconductor layer comprises a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region which are sequentially arranged in a first direction, the dopant concentration of the first to third P-type doped regions is sequentially decreased, the dopant concentration of the first to third N-type doped regions is sequentially decreased, and the first direction is the electron flow direction; the second semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and the third P-type doped region in the first direction, and the first N-type doped region is connected with the first electrode; the third P-type doped region is connected with the second electrode; the first N-type doped region is connected with the third electrode.

Description

Avalanche photodetector and preparation method thereof

Technical field

The invention relates to the field of photonic integrated chip detection technology, and in particular to an avalanche photoelectric detector and a preparation method thereof.

Background technique

As one of the core devices of the silicon photonic architecture, the avalanche photodetector has the function of converting low-power optical signals into electrical signals. Its working principle is that photogenerated carriers (hole-electron pairs) generated through the photoelectric effect, in high electric fields The area is rapidly accelerated when moving, and one or more collisions may occur during the movement. Secondary and third new hole-electron pairs are generated through the collision ionization effect, resulting in an avalanche multiplication effect, which rapidly increases the number of carriers, thereby forming a comparison large optical signal current.

Currently, germanium-silicon materials compatible with CMOS technology are widely used in silicon photonic integrated chips to achieve avalanche photoelectric detection. It uses silicon material as an optical waveguide and as an avalanche gain area (also called a multiplication area), while the germanium material absorbs photons. The current shortcomings of the germanium-silicon avalanche photodetector structure are as follows: First, it requires an epitaxial monocrystalline silicon process, which is relatively complex to manufacture; second, the absorption area is usually doped by P or N type, and these dopings will cause light absorption loss, and then Reduce the quantum efficiency of the detector; thirdly, the absorption region and the multiplication region are not easy to adjust independently. The concentration accuracy of the doped region must be too high, and the process tolerance is low, which can easily lead to unsatisfactory gain bandwidth. Therefore, avalanche photodetectors using germanium-silicon materials need further improvement.

Contents of the invention

In view of this, embodiments of the present invention provide an avalanche photodetector and a preparation method thereof to solve at least one problem existing in the background art.

In order to achieve the above objects, the technical solution of the present invention is implemented as follows:

On the one hand, embodiments of the present invention provide an avalanche photodetector, including:

a substrate, a surface of which includes a first semiconductor layer;

a second semiconductor layer located above the first semiconductor layer, the material of the second semiconductor layer being different from the material of the first semiconductor layer; wherein,

The first semiconductor layer includes a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, and a third P-type doped region arranged sequentially in a first direction. impurity region, a second intrinsic region, a second N-type doping region and a first N-type doping region, the dopant concentrations of the first to third P-type doping regions decrease in sequence, and the first The dopant concentration to the third N-type doped region decreases successively, and the first direction is the electron flow direction of the avalanche photodetector;

The second semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region along the first direction. district,

The first N-type doped region is connected to a first electrode; the third P-type doped region is connected to a second electrode; and the first P-type doped region is connected to a third electrode.

In the above solution, a first reverse bias voltage V ₁ is set between the first electrode and the third electrode, and a second reverse bias voltage V ₂ is set between the first electrode and the second electrode. .

In the above solution, the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, germanium-silicon alloy, III-V group materials and alloys thereof.

In the above scheme, the dopant concentration of the first P-type doped region or the first N-type doped region is 1×10 ²⁰ /cm ³ ~ 5×10 ²⁰ /cm ³ , and the second P-type doped region The dopant concentration of the N-type doped region or the second N-type doped region is 2×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ , and the third P-type doped region or the third The dopant concentration of the N-type doped region is 1.2×10 ¹⁷ to 4×10 ¹⁷ /cm ³ .

In the above solution, the size of the second intrinsic region in the first direction is 50 nm to 800 nm.

In the above solution, the size of the second semiconductor layer in the first direction is 150 nm to 1500 nm, the size in the second direction is 1 μm to 100 μm, and the size in the third direction is 150 nm to 1500 nm. 600 nm, wherein the third direction is a direction perpendicular to the substrate, and the second direction is perpendicular to the third direction and perpendicular to the first direction.

Embodiments of the present invention also provide a method for preparing an avalanche photodetector, which includes:

providing a substrate including a first semiconductor layer on a surface thereof;

A selective doping process is performed to form a first P-type doped region, a second P-type doped region, a third N-type doped region, and a third N-type doped region arranged sequentially along a first direction on the first semiconductor layer. An intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region, the doping of the first to third P-type doped regions The dopant concentration decreases in sequence, and the dopant concentration of the first to third N-type doped regions decreases in sequence;

Form a second semiconductor layer, the material of the second semiconductor layer is different from the material of the first semiconductor layer, and cover part of the second P-type doped region, the third N-type doped region in the first direction. impurity region, the first intrinsic region and part of the third P-type doped region;

A first electrode, a second electrode and a third electrode are formed perpendicular to the plane direction of the substrate. The first electrode is electrically connected to the first N-type doped region; the second electrode is connected to the first N-type doped region. Three P-type doping regions are electrically connected, and the third electrode is electrically connected to the first P-type doping region;

The first direction is the electron flow direction of the avalanche photodetector.

In the above solution, the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, germanium-silicon alloy, III-V group materials and alloys thereof.

In the above scheme, the dopant concentration of the first P-type doped region or the first N-type doped region is 1×10 ²⁰ /cm ³ ~ 5×10 ²⁰ /cm ³ , and the second P-type doped region The dopant concentration of the N-type doped region or the second N-type doped region is 2×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ , and the third P-type doped region or the third The dopant concentration of the N-type doped region is 1.2×10 ¹⁷ to 4×10 ¹⁷ /cm ³ .

In the above solution, forming the first electrode, the second electrode and the third electrode arranged perpendicularly to the plane direction of the substrate include:

forming a covering layer covering the first semiconductor layer and the second semiconductor layer;

Forming first, second and third windows respectively corresponding to the first N-type doped region, the third P-type doped region and the first P-type doped region;

The first, second and third windows are filled with metal to form first, second and third electrodes.

The avalanche photodetector provided by the embodiment of the present invention includes: a substrate, the surface of the substrate includes a first semiconductor layer; a second semiconductor layer located on the first semiconductor layer, the material of the second semiconductor layer Different materials from the first semiconductor layer; wherein the first semiconductor layer includes a first P-type doped region, a second P-type doped region, and a third N-type doped region arranged sequentially in the first direction. region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region, the first to third P-type doped regions The dopant concentration of the first to third N-type doping regions decreases in sequence, and the first direction is the electron flow direction of the avalanche photodetector; the second The semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region along the first direction, The first N-type doped region is connected to a first electrode; the third P-type doped region is connected to a second electrode; and the first P-type doped region is connected to a third electrode. Since the multiple doped charge regions and the second intrinsic region as the avalanche region are both in the first semiconductor layer, there is no need for additional epitaxial production of single crystal silicon, and the production is relatively simple, which is beneficial to reducing costs; in addition, since the first The N-type doping region is connected to the first electrode, the third P-type doping region is connected to the second electrode, and the first P-type doping region is connected to the third electrode. Subsequently, bias can be applied independently on these three electrodes. Therefore, the electric field located in the second semiconductor layer as the absorption region and the second intrinsic region as the avalanche region can be adjusted independently, and the tolerance for the concentration accuracy of the doping region is better, which is conducive to achieving low noise and high gain. bandwidth.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

Figure 1 is a schematic isometric view of an avalanche photodetector provided by an embodiment of the present invention;

Figure 2 is a schematic top view of an avalanche photodetector provided by an embodiment of the present invention;

Figure 3 is a schematic diagram along the Y direction of an avalanche photodetector provided by an embodiment of the present invention;

Figure 4 is a schematic flow chart of a method for preparing an avalanche photodetector provided by an embodiment of the present invention;

5a to 5e are cross-sectional views of the device structure during the preparation process of the avalanche photodetector provided by the embodiment of the present invention.

Detailed ways

In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

In the embodiment of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, but are not used to describe a specific order or sequence.

In embodiments of the present invention, unless otherwise explicitly stated and limited, the “upper” or “lower” relationship between two layers in the semiconductor structure may be direct contact between the two layers, or indirect contact between the two layers through an intermediate layer. .

In embodiments of the present invention, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal surfaces at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces. Also, a layer may include multiple sub-layers.

In the embodiment of the present invention, spatially relative terms, such as “below”, “below”, “down”, “above”, “up”, “upward”, “downward”, etc. may be used herein for convenience of description. Describes the relationship of one element or feature to another element(s) or feature(s), as shown in the figure. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Silicon photonics technology is a new generation technology based on silicon and silicon-based substrate materials (such as SiGe/Si, silicon-on-insulator, etc.) and using the existing complementary metal oxide semiconductor (CMOS) process to develop and integrate optical devices. Silicon photonics technology combines the ultra-large-scale, ultra-high-precision manufacturing characteristics of integrated circuit technology with the ultra-high speed and ultra-low power consumption of photonic technology. It is a disruptive technology to cope with the failure of Moore's Law. This combination benefits from the scalability of semiconductor wafer manufacturing, which reduces costs. As one of the core devices of silicon photonic architecture, photodetectors have the function of converting optical signals into electrical signals. The current shortcomings of the germanium-silicon avalanche photodetector structure are as follows: First, it requires an epitaxial monocrystalline silicon process, which is relatively complex to manufacture; second, the absorption area is usually doped by P or N type, and these dopings will cause light absorption loss, and then Reduce the quantum efficiency of the detector; third, the absorption region and avalanche region (also called the multiplication region) are not easy to adjust independently. The concentration accuracy of the doping region must be too high, and the process tolerance is low, which can easily lead to unsatisfactory gain bandwidth. .

Based on this, the following technical solutions of the embodiments of the present application are proposed.

An embodiment of the present invention provides an avalanche photodetector, which includes:

a substrate, a surface of which includes a first semiconductor layer;

a second semiconductor layer located above the first semiconductor layer, the material of the second semiconductor layer being different from the material of the first semiconductor layer; wherein,

The first semiconductor layer includes a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, and a third P-type doped region arranged sequentially in a first direction. impurity region, a second intrinsic region, a second N-type doping region and a first N-type doping region, the dopant concentrations of the first to third P-type doping regions decrease in sequence, and the first The dopant concentration to the third N-type doped region decreases successively, and the first direction is the electron flow direction of the avalanche photodetector;

The second semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region along the first direction. district,

The first N-type doped region is connected to a first electrode; the third P-type doped region is connected to a second electrode; and the first P-type doped region is connected to a third electrode.

Please refer specifically to FIGS. 1 to 3 below. FIG. 1 is a schematic isometric view of an avalanche photodetector provided by an embodiment of the present invention; FIG. 2 is a top view of an avalanche photodetector provided by an embodiment of the present invention. Schematic diagram; Figure 3 is a schematic diagram along the Y direction of an avalanche photodetector provided by an embodiment of the present invention.

With reference to Figures 1 to 3, the avalanche photodetector includes:

Substrate 10, the substrate includes a first semiconductor layer 300; an avalanche region of the avalanche photodetector is formed in the first semiconductor layer 300 to achieve an avalanche effect;

The second semiconductor layer 400 uses a different material from the first semiconductor layer 300 .

Here, the substrate may be a multi-layer structure, wherein the top of the substrate is the first semiconductor layer, and the bottom may include a single semiconductor material (such as silicon (Si), germanium (Ge), etc.), a compound semiconductor material (such as A layer composed of silicon germanium (SiGe, etc.) and an insulating layer composed of its oxide. In this example, the substrate 10 may be silicon-on-insulator (SOI) or germanium-on-insulator (GeOI), or the like.

The embodiment of the present application is described by taking the layer below the substrate surface as SOI as an example. It can be understood that the first semiconductor layer 300 is located on the top of the substrate 10 of the present invention.

In some embodiments, the material of first semiconductor layer 300 includes silicon. The layers located below the first semiconductor layer 300 include the insulating layer 200 and the bottom layer 100 in sequence.

In practical applications, the bottom layer 100 may be a silicon wafer or a wafer made of other materials. Therefore, the material of the bottom layer 100 may be silicon, germanium, sapphire, etc.

In some embodiments, the material of the bottom layer 100 is silicon. Correspondingly, the material of the insulating layer 200 can be an oxide of silicon, such as silicon dioxide.

The bottom layer 100 may have a thicker thickness than the first semiconductor layer 300 . It should be understood that in order to clearly illustrate each layer structure in the figure, the dimensional proportional relationship of each layer structure may be inconsistent with the actual structure.

It should be noted that, for convenience of description, as shown in Figure 1 , the embodiment of the present invention is described with reference to the first direction (X), the second direction (Y) and the third direction (Z) (see Figure 1 ). .

Here, the substrate 10 may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when flatness of the top surface and the bottom surface is ignored, the direction perpendicular to the top surface and the bottom surface of the substrate is defined as Three directions (Z). The third direction Z is also the stacking direction of each layer structure subsequently deposited on the substrate, or the height direction of the device. The plane where the top surface and the bottom surface of the substrate are located, or strictly speaking, the center plane in the thickness direction of the substrate, is determined as the substrate plane. Two first directions (X) and second directions (Y) that intersect each other (for example, are perpendicular to each other) are defined in the substrate plane direction. In this embodiment, the first direction X is the direction of electron flow; the second direction Y is the propagation direction of the optical signal.

Since in theory, any semiconductor material can be used as the material of the first semiconductor layer 300 in the avalanche photodetector, the first semiconductor material is not strictly limited here. In an embodiment in which the substrate 10 includes a single Si bottom layer 100, the first semiconductor material is Si.

In order to achieve the avalanche effect in the avalanche photodetector, different regions formed in the first semiconductor layer 300 of the avalanche photodetector have different doping regions, including doping with P-type dopants, N-type dopants with different concentrations. dopants, and undoped regions (intrinsic regions).

The structure of the first semiconductor layer 300 of the avalanche photodetector according to the embodiment of the present disclosure will be described in detail below. In some embodiments, the first semiconductor layer 300 in the avalanche photodetector includes a first P-type doped region 301, a second P-type doped region 302, and a third N-type doped region arranged sequentially in the first direction X. region 303, first intrinsic region 304, third P-type doped region 305, second intrinsic region 306, second N-type doped region 307 and first N-type doped region 308. The P-type dopant concentrations of the first P-type doped region, the second P-type doped region, and the third P-type doped region decrease in sequence, and the first N-type doped region, the second N-type doped region, The N-type dopant concentration of the third N-type doped region decreases successively.

In some embodiments, the P-type dopant may be boron (B), and the N-type dopant may be phosphorus (P) or arsenic (As).

In some embodiments, the dopant concentration of the first P-type doped region 301 or the first N-type doped region 308 is 1×10 ²⁰ /cm ³ ~ 5×10 ²⁰ /cm ³ , and the second P-type doped region 308 has a dopant concentration of 1 The dopant concentration of the impurity region 302 or the second N-type doping region 307 is 2×10 ¹⁷ /cm ³ ~ 5×10 ¹⁸ /cm ³ , and the third P-type doping region 305 or the third N-type doping region The dopant concentration of 303 is 1.2×10 ¹⁷ ~ 4×10 ¹⁷ /cm ³ .

In practical applications, since the intrinsic region is undoped or lightly doped, its concentration is generally less than a predetermined value, for example, less than 1×10 ¹⁷ /cm ³ .

It should be noted that the dopant concentrations of the first P-type doped region and the first N-type doped region may be the same or different, as long as their doping concentrations are within the above range.

Similarly, the dopant concentrations of the second P-type doped region and the second N-type doped region, and the third P-type doped region and the third N-type doped region may also be the same or different respectively.

For the intrinsic region, it may be an undoped or lightly doped first semiconductor material. Among them, the intrinsic region is the region where impact ionization specifically occurs to generate electron-hole pairs.

In the first semiconductor layer 300 in the avalanche photodetector of the present invention, the avalanche region may be the second intrinsic region 306.

It should be understood that the avalanche photodetector is based on applying a voltage between avalanche regions to generate an electric field, thereby extracting photogenerated carriers through the electric field to form a current. Specifically, a bias voltage is applied to both sides of the avalanche zone along the first direction to achieve photoelectric detection.

In an embodiment of the present invention, a second semiconductor layer 400 is included above the first semiconductor layer 300, and the material of the second semiconductor layer 400 is different from the material of the first semiconductor layer.

In some embodiments, the material of the first semiconductor layer 300 is silicon, and the material of the second semiconductor layer 400 is germanium, germanium-silicon alloy, III-V group materials and alloys thereof.

In a further embodiment, the material of the first semiconductor layer 300 is silicon, and the material of the second semiconductor layer is germanium. The resulting avalanche photodetector is a silicon germanium photodetector.

Here, since the second semiconductor layer 400 as the absorption region in the avalanche photodetector provided by the present invention is not doped with P or N type and does not involve ohmic contact, the light absorption loss can be reduced as much as possible, which is beneficial to improving quantum absorption. efficiency.

The second semiconductor layer 400 of the avalanche photodetector in this embodiment sequentially covers part of the second P-type doped region 302, the third N-type doped region 303, the first intrinsic region 304 and part of the third doped region along the first direction. Three P-type doped regions 305. The second semiconductor layer 400 is formed as the absorption region of the avalanche photodetector.

Here, when a light signal is applied in the Y direction of the avalanche photodetector, the second semiconductor layer 400 absorbs photons in the light signal. According to the photoelectric effect proposed by Einstein, one photon produces one photogenerated electron. Therefore, the second semiconductor layer 400 absorbs photons and generates electrons, and the generated electrons are photogenerated electrons.

Please refer to FIGS. 1 to 3 . The second semiconductor layer 400 covers part of the second P-type doped region 302 and part of the third P-type doped region 305 , thereby doping the second P-type doped region 302 and the third P-type doped region 305 . The hybrid regions 305 are bridged to form a path for carriers. The above-mentioned photogenerated electrons can move from the second P-type doped region 302 to the third P-type doped region 305 under the action of the electric field.

Continuing to refer to FIGS. 1 to 3 , the avalanche photodetector of this embodiment further includes a first electrode 501 , a second electrode 502 and a third electrode 503 . The first electrode 501 is electrically connected to the first N-type doped region 308; the second electrode 502 is electrically connected to the third P-type doped region 305, and the third electrode 503 is electrically connected to the The first P-type doped region 301 is electrically connected.

The first electrode 501, the second electrode 502 and the third electrode 503 electrically connected to the first N-type doped region 308, the third P-type doped region 305 and the first P-type doped region 301 can pass through the first A first bias voltage V ₁ is provided between the electrode 501 and the third electrode 503 to provide a first bias voltage V ₁ between the first N-type doped region 308 and the first P-type doped region 301 , and at the same time, by A second bias voltage V ₂ is provided between the first electrode 501 and the second electrode 502 to provide an external second bias voltage V ₂ between the first N-type doped region 308 and the third P-type doped region 305 .

As mentioned above, the second semiconductor layer 400 as an absorption region connects the second P-type doped region 302 and the third P-type doped region 305 to form a path for carriers. Therefore, by applying an electric field between the first N-type doped region 308 and the first P-type doped region 301 (ie, through the first bias voltage V ₁ ), the energy of the above-mentioned photogenerated electrons can be adjusted.

As for providing the second bias voltage V ₂ between the third P-type doped region 305 and the first N-type doped region 308, since it is located at both ends of the second intrinsic region 306, the second intrinsic Region 306 serves as an avalanche region, so the second bias voltage V ₂ can regulate the electric field distribution in the avalanche region. The avalanche region of the avalanche photodetector refers to the region where carriers (here, electrons) are multiplied, so it can also be called the multiplication region. The absorption area of the avalanche photodetector can convert the incident light signal into multiple electrons. These electron pairs flow under the action of the electric field to form a photocurrent; the avalanche area can further excite the small amount of electrons formed in the absorption area through the avalanche effect to form A large number of electrons are used to achieve amplification; finally, the photocurrent is conducted through a pair of metal electrodes to achieve photoelectric detection.

In the presence of an electric field (due to the first bias voltage V ₁ applied to the avalanche photodetector), these photogenerated electrons are accelerated to the second intrinsic region 306 for multiplication. As the photogenerated electrons pass through the second intrinsic region 306, they collide with other carriers bound in the semiconductor atomic lattice, thereby generating more free carriers through a process called "impact ionization." These new free carriers are also accelerated by the applied electric field and create more free carriers.

In addition, the arrangement of the third N-doped region 303, the first intrinsic region 304 and the third P-doped region 305 of the avalanche photodetector in the embodiment of the present invention, as well as the third N-doped region The respective dopant concentration ranges of 303 and the third P-doped region 305 are beneficial to the electric field distribution in the second semiconductor layer 400 as the absorption region. Due to the existence of the first intrinsic region 304, even under the action of the first bias voltage _V1 , electrons cannot pass through the first intrinsic region 304, and the first intrinsic region 304 plays a certain blocking role. Electrons from the direction of the second P-doped region 302 can pass through the third N-doped region 303, pass through the second semiconductor layer 400, and then pass through the third P-doped region 305 to the avalanche region.

In order to achieve the above-mentioned avalanche effect, existing avalanche photodetectors only apply bias voltages at both ends of the avalanche zone. This approach has some shortcomings. For example, the absorption zone and avalanche zone (also known as the multiplication zone) are not easy to adjust independently. The concentration accuracy of the doped region is too high and the process tolerance is low, which can easily lead to unsatisfactory gain bandwidth. To this end, the present invention sets bias voltages at both ends of the absorption region and the avalanche region of the avalanche photodetector at the same time, that is, a first bias voltage is provided between the first P-doped region 301 and the first N-doped region 308. The voltage V ₁ is set, and the second bias voltage V ₂ is provided between the first N-doped region 308 and the third P-type doped region 305 . As a result, independent adjustment of the electric fields corresponding to the absorption region and the avalanche region is achieved, and the gain bandwidth can be further improved.

It should be noted that the first bias voltage V ₁ and the bias voltage V ₂ are relatively independent. The first bias voltage V ₁ acts on the absorption region, and its value may be 1 to 4 volts. The second bias voltage V ₂ acts on the avalanche zone, and its value can be 3 to 20 volts.

In some embodiments, the size of the second intrinsic region 306 in the first direction X ranges from 50 nm to 800 nm, that is to say, the width of the second intrinsic region 306 is within the above interval. Thus, a large bandwidth is achieved while achieving higher gain. Since the second intrinsic region 306 is the avalanche region of the avalanche photodetector according to the embodiment of the present invention, the size of the second intrinsic region 306 in the first direction X should not be too small. For example, when it is less than 50nm, the electrons moving from the absorption area do not have sufficient avalanche space, so they cannot be effectively absorbed, and the multiplication effect is poor. Its size should not be too large, otherwise the voltage requirements required at both ends of the avalanche zone will be too high, the avalanche time for electrons will be too long, the response will be reduced, and the detection effect will be affected.

In some embodiments, the size of the second semiconductor layer in the first direction X is 150 nm to 1500 nm, the size in the second direction Y is 1 μm to 100 μm, and the size in the third direction Z is 150 nm to 600nm. The size of the second semiconductor layer in the embodiment of the present invention is limited to the above range, which can reduce noise and reduce the generation of dark current.

Here, when describing the size of the second semiconductor layer, the size difference between the upper and lower surfaces of the second semiconductor layer during the epitaxial growth process may not be considered.

It should be noted that the shape of the second semiconductor layer 400 parallel to the substrate 10 may be a regular rectangle, or may have a trapezoid with a certain size of chamfer along the first direction X, see FIG. 1 .

The avalanche photodetector of the present invention may further include a covering layer covering the first semiconductor layer 300, the second semiconductor layer 400, the first electrode 501, the second electrode 502 and the third electrode 503 (see Figure 5e).

It should be noted that the structure of the avalanche photodetector of the present invention can also be its own mirror structure. For example, referring to Figure 3, the first direction X in the embodiment of the present invention is from right to left, then the third direction of the mirror structure is One direction X' is from left to right. Therefore, the avalanche photodetector and its mirror structure provided by the embodiments of the present invention are within the scope of protection of the present invention.

The avalanche photodetector provided by the embodiment of the present invention includes: a substrate, the surface of the substrate includes a first semiconductor layer; a second semiconductor layer located on the first semiconductor layer, the material of the second semiconductor layer Different materials from the first semiconductor layer; wherein the first semiconductor layer includes a first P-type doped region, a second P-type doped region, and a third N-type doped region arranged sequentially in the first direction. region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region, the first to third P-type doped regions The dopant concentration of the first to third N-type doping regions decreases in sequence, and the first direction is the electron flow direction of the avalanche photodetector; the second The semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region along the first direction, The first N-type doped region is connected to a first electrode; the third P-type doped region is connected to a second electrode; and the first P-type doped region is connected to a third electrode. Since the multiple doped charge regions and the second intrinsic region as the avalanche region are both in the first semiconductor layer, there is no need for additional epitaxial production of single crystal silicon, and the production is relatively simple, which is beneficial to reducing costs; in addition, since the first The N-type doping region is connected to the first electrode, the third P-type doping region is connected to the second electrode, and the first P-type doping region is connected to the third electrode. Subsequently, bias can be applied independently on these three electrodes. Therefore, the electric field in the second semiconductor layer as the absorption region and the second intrinsic region as the avalanche region can be adjusted independently, and the tolerance to the concentration accuracy of the doped region is better, which is beneficial to achieving low noise and high performance. gain bandwidth.

An embodiment of the present invention also provides a method for preparing an avalanche photodetector; for details, please see Figures 5a to 5e. As shown in the figure, the method includes the following steps:

Step 201: Provide a substrate, including a first semiconductor layer on the surface of the substrate;

Step 202: Perform a selective doping process to form a first P-type doping region, a second P-type doping region, and a third N-type doping region arranged sequentially along the first direction on the first semiconductor layer. region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region;

Step 203: Form a second semiconductor layer. The material of the second semiconductor layer is different from the material of the first semiconductor layer, and covers part of the second P-type doped region, the third P-type doped region, and the third semiconductor layer in the first direction. N-type doped region, the first intrinsic region and part of the third P-type doped region;

Step 204: Form a first electrode, a second electrode and a third electrode arranged perpendicular to the plane direction of the substrate. The first electrode is electrically connected to the first N-type doped region; the second electrode is The third P-type doped region is electrically connected, and the third electrode is electrically connected to the first P-type doped region.

The above-mentioned first direction is the electron flow direction of the avalanche photodetector.

Next, the avalanche photodetector and its preparation method provided by the embodiment of the present invention will be further described in detail with reference to the cross-sectional view of the device structure during the preparation process of the avalanche photodetector shown in Figures 5a to 5e.

First, perform step 201. A substrate is provided, the substrate including a first semiconductor layer.

Referring to FIG. 5a, a substrate 10 is provided; the substrate 10 may include a multi-layer structure, and functional layers are further grown on the multi-layer structure. Therefore, the substrate 10 of the present invention may include a multi-layer structure, wherein the surface of the substrate 10 includes the first semiconductor layer 300, and the layer located below the surface may include a simple semiconductor material (for example, silicon (Si), germanium ( Ge), etc.), a composite semiconductor material (such as silicon germanium (SiGe), etc.) and an insulating layer composed of its oxide. Therefore, the substrate 10 may be silicon-on-insulator (SOI) or germanium-on-insulator (GeOI).

This embodiment of the present application takes the substrate 10 as SOI as an example for description. It can be understood that the first semiconductor layer 300 is located on the surface of the substrate 10 of the present invention.

The substrate 10 also includes an intermediate layer 200 (which may be an insulating layer in practical applications) and a bottom layer 100 (which may be a silicon layer in practical applications) located under the first semiconductor layer 300 . The insulating layer 200 is, for example, a silicon dioxide layer, which can be directly obtained by thermally oxidizing the bottom layer 100 . The bottom layer 100 may have a thicker thickness than the first semiconductor layer 300 .

Next, step 202 is performed. Here, reference is made to Figure 5b. A selective doping process is performed to form a first P-type doped region 301, a second P-type doped region 302, and a third N-type doped region sequentially arranged along the first direction on the first semiconductor layer 300. region 303, first intrinsic region 304, third P-type doped region 305, second intrinsic region 306, second N-type doped region 307 and first N-type doped region 308.

In the actual process, the mask photolithography process can be used to sequentially open windows in the areas that need to be doped. Ions are then implanted in the window to form doped regions with different doping concentrations.

Specifically, the doping concentration of the first P-type doped region or the first N-type doped region is 1×10 20 /cm ³ to 5×10 20 /cm 3 , and the second P-type doped region has a doping concentration of 1×10 ²⁰ /cm 3 to 5×10 ²⁰ /cm ³ . The doping concentration of the doping region or the second N-type doping region is 2×10 ¹⁷ /cm ³ ~ 5×10 ¹⁸ /cm ³ , and the third P-type doping region or the third N-type doping region The doping concentration of the doped region is 1.2×10 ¹⁷ to 4×10 ¹⁷ /cm ³ . In some embodiments, the dopant in the first P-type doped region 301, the second P-type doped region 302, and the third P-type doped region 305 is boron (B) element; and the first N-type doped region The dopant of the impurity region 308, the second N-type doping region 307, and the third N-type doping region 303 is phosphorus (P) element or arsenic (As) element.

Next, step 203 is performed. Referring to FIG. 5c, a second semiconductor layer 400 is formed, covering the first intrinsic region 304 and the third N-type doped region 303 in the first direction X, and covering part of the second P-type doped region 302 and The third P-type doped region 305.

In some embodiments, an initial second semiconductor layer 400' (not shown in the figure) covering the first semiconductor material is first formed, and then the initial second semiconductor layer 400' is etched using a patterned photoresist layer. The second semiconductor layer 400 is formed, and then the photoresist layer is removed.

Here, the formed second semiconductor layer 400 has a ladder structure (the shape thereof can be referred to the second semiconductor layer 400 in FIG. 1 ). Among them, the trapezoidal structure has a smaller side length near the light incident end.

In some embodiments, the first semiconductor layer is made of a different material than the second semiconductor layer. For example, when the material of the first semiconductor layer is Si, the material of the second semiconductor layer is germanium, germanium-silicon alloy, III-V group materials and alloys thereof.

In a specific embodiment of the avalanche photodetector according to the embodiment of the present invention, the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium. In other words, the avalanche photodetector according to the embodiment of the present invention is made of germanium. Silicon avalanche photodetector.

Processes such as molecular beam epitaxial growth can be used to epitaxially grow high-quality polycrystalline germanium materials to form the second semiconductor layer.

Next, step 204 is performed. See Figure 5d. A first electrode 501, a second electrode 502 and a third electrode 503 are formed perpendicular to the plane direction of the substrate. The first electrode 501 is electrically connected to the first N-type doped region 308; the second electrode 501 is electrically connected to the first N-type doped region 308; The electrode 502 is electrically connected to the third P-type doped region 305 , and the third electrode 503 is electrically connected to the first P-type doped region 301 .

In some embodiments, forming the first electrode 501, the second electrode 502 and the third electrode 503 arranged perpendicularly to the plane direction of the substrate includes:

Forming a covering layer 600 covering the first semiconductor layer 300 and the second semiconductor layer 400;

Forming a first window, a second window and a third window respectively above the first N-type doped region 308, the third P-type doped region 305 and the first N-type doped region 308;

The first window, the second window and the third window are filled with metal material to form the first electrode 501 , the second electrode 502 and the third electrode 503 .

In one embodiment, the covering layer 600 may be directly formed of insulating material. Referring to FIG. 5e , a capping layer 600 may first be formed using an insulating material, such as silicon dioxide, to cover the doped first semiconductor layer 300 and the second semiconductor layer 400 . Then, photolithography and inductive plasma etching are used to open windows on the covering layer 600 to form a first window, a second window and a third window to expose the first N-type doped region 308 in the first semiconductor layer 300 , the surfaces of the third P-type doped region 305 and the first P-type doped region 301, and then use, for example, a magnetron sputtering process to deposit metal materials in the first window, the second window and the third window to form respective The first N-type doped region 308, the third P-type doped region 305 and the first P-type doped region 301 are electrically connected to the first electrode 501, the second electrode 502 and the third electrode 503.

After the electrodes are formed, the upper surface of the covering layer 600 may also be planarized. Specifically, a chemical mechanical polishing (CMP) process may be used. In this way, different voltages can be applied between the first electrode 501 and the second electrode 502 and between the first electrode 501 and the third electrode 503 through external leads, so that between the first electrode 501 and the third electrode 503, And providing a bias voltage to the first electrode 501 and the third electrode 503 .

It should be noted that the avalanche photodetector embodiments and the avalanche photodetector preparation method embodiments provided by the present invention belong to the same concept; the technical features in the technical solutions recorded in each embodiment shall not conflict with each other unless there is any conflict. , can be combined in any way. However, it needs further explanation that the combination of technical features of the avalanche photodetector provided by the embodiment of the present invention can already solve the technical problems to be solved by the present invention; therefore, the avalanche photodetector provided by the embodiment of the present invention can be There are limitations to the preparation method of the avalanche photodetector provided by the embodiment of the present invention. Any avalanche photodetector prepared by a preparation method that can form the avalanche photodetector structure provided by the embodiment of the present invention is within the scope of protection of the present invention. .

The above are only preferred embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in within the protection scope of the present invention.

Claims (10)

1. An avalanche photoelectric detector, characterized in that it includes: a substrate, a surface of which includes a first semiconductor layer; a second semiconductor layer located above the first semiconductor layer, the material of the second semiconductor layer being different from the material of the first semiconductor layer; wherein, The first semiconductor layer includes a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, and a third P-type doped region arranged sequentially in a first direction. impurity region, a second intrinsic region, a second N-type doping region and a first N-type doping region, the dopant concentrations of the first to third P-type doping regions decrease in sequence, and the first The dopant concentration to the third N-type doped region decreases successively, and the first direction is the electron flow direction of the avalanche photodetector; the electrons pass from the second P-type doped region through the third Three N-type doped regions flow to the second intrinsic region through the second semiconductor layer and the third P-type doped region; The second semiconductor layer sequentially covers part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region along the first direction. doped region, The first N-type doped region is connected to a first electrode; the third P-type doped region is connected to a second electrode; and the first P-type doped region is connected to a third electrode. 2. The avalanche photodetector according to claim 1, wherein a first reverse bias voltage V ₁ is provided between the first electrode and the third electrode, and the first electrode and the second electrode A second reverse bias voltage V ₂ is set between them. 3. The avalanche photodetector according to claim 1 or 2, characterized in that the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, germanium-silicon alloy, III-V group Materials and their alloys. 4. The avalanche photodetector according to claim 1, wherein the dopant concentration of the first P-type doped region or the first N-type doped region is 1×10 ²⁰ /cm ³ ~ 5×10 ²⁰ /cm ³ , the dopant concentration of the second P-type doped region or the second N-type doped region is 2×10 ¹⁷ /cm ³ ~ 5×10 ¹⁸ /cm ³ , so The dopant concentration of the third P-type doped region or the third N-type doped region is 1.2×10 ¹⁷ to 4×10 ¹⁷ /cm ³ . 5. The avalanche photodetector according to claim 1, wherein the size of the second intrinsic region in the first direction is 50 nm to 800 nm. 6. The avalanche photodetector according to claim 1 or 2, characterized in that the size of the second semiconductor layer in the first direction is 150 nm to 1500 nm, and the size in the second direction is 1 μm to 100 μm. , and the size in the third direction is 150nm to 600nm, wherein the third direction is a direction perpendicular to the substrate, and the second direction is perpendicular to the third direction and perpendicular to the first direction. 7. A method for preparing an avalanche photoelectric detector, which is characterized by comprising: providing a substrate including a first semiconductor layer on a surface thereof; A selective doping process is performed to form a first P-type doped region, a second P-type doped region, a third N-type doped region, and a third N-type doped region arranged sequentially along a first direction on the first semiconductor layer. An intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region, the doping of the first to third P-type doped regions The dopant concentration decreases in sequence, and the dopant concentration of the first to third N-type doped regions decreases in sequence; Forming a second semiconductor layer, the material of the second semiconductor layer is different from the material of the first semiconductor layer, and covers part of the second P-type doped region, the third N-type doped region in the first direction, Type doped region, the first intrinsic region and part of the third P-type doped region; A first electrode, a second electrode and a third electrode are formed perpendicular to the plane direction of the substrate. The first electrode is electrically connected to the first N-type doped region; the second electrode is connected to the first N-type doped region. Three P-type doping regions are electrically connected, and the third electrode is electrically connected to the first P-type doping region; The first direction is the electron flow direction of the avalanche photodetector; the electrons pass from the second P-type doped region through the third N-type doped region, and pass through the second semiconductor layer and the third N-type doped region. The three P-type doped regions flow to the second intrinsic region. 8. The method of claim 7, wherein the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, germanium-silicon alloy, III-V group materials and alloys thereof . 9. The method according to claim 7, wherein the dopant concentration of the first P-type doped region or the first N-type doped region is 1×10 ²⁰ /cm ³ to 5× 10 ²⁰ /cm ³ , the dopant concentration of the second P-type doped region or the second N-type doped region is 2×10 ¹⁷ /cm ³ ~ 5×10 ¹⁸ /cm ^{3 , and the dopant concentration of the second P-type doped region or the second N-type doped region is 2×10 17 /cm 3 ~ 5×10 18 /cm 3} . The dopant concentration of the three P-type doped regions or the third N-type doped region is 1.2×10 ¹⁷ to 4×10 ¹⁷ /cm ³ . 10. The method according to claim 7, wherein forming the first electrode, the second electrode and the third electrode arranged perpendicularly to the plane direction of the substrate includes: forming a covering layer covering the first semiconductor layer and the second semiconductor layer; A first window, a second window and a third window are respectively formed in the first N-type doped region, the third P-type doped region and one end of the first P-type doped region along the second direction. , to expose part of the surface of the first P-type doped region, the third P-type doped region and the first N-type doped region; The first, second and third windows are filled with metal to form first, second and third electrodes.