CN114256169B - Semiconductor packaging structure and preparation method thereof - Google Patents
Semiconductor packaging structure and preparation method thereof Download PDFInfo
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- CN114256169B CN114256169B CN202111500686.7A CN202111500686A CN114256169B CN 114256169 B CN114256169 B CN 114256169B CN 202111500686 A CN202111500686 A CN 202111500686A CN 114256169 B CN114256169 B CN 114256169B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 237
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 29
- 238000002360 preparation method Methods 0.000 title abstract description 14
- 239000004033 plastic Substances 0.000 claims abstract description 102
- 229910000679 solder Inorganic materials 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000012790 adhesive layer Substances 0.000 claims description 35
- 239000010410 layer Substances 0.000 claims description 34
- 238000012546 transfer Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000005520 cutting process Methods 0.000 claims description 5
- 239000002313 adhesive film Substances 0.000 claims description 2
- 229920001169 thermoplastic Polymers 0.000 claims description 2
- 239000004416 thermosoftening plastic Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000003292 glue Substances 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000000638 solvent extraction Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The embodiment of the invention provides a semiconductor packaging structure and a preparation method thereof, which relate to the technical field of semiconductor packaging, and the semiconductor packaging structure is realized by arranging a semiconductor device on a substrate carrier plate, arranging a plastic package body coated outside the semiconductor device, and then arranging a first adapter plate and a second adapter plate on the semiconductor device, wherein the plastic package body is provided with a first groove and a second groove which penetrate through the semiconductor device, the first adapter plate and the second adapter plate are respectively attached in the first groove and the second groove, the first adapter plate and the second adapter plate are provided with a first solder ball and a second solder ball, the semiconductor device is electrically connected with the first adapter plate and the second adapter plate at the same time, and the wiring structure is realized by arranging the adapter plates. Meanwhile, an external circuit is realized through the solder balls on the adapter plate, the adapter plate can be prepared in advance, the size and the occupied space of the solder balls can be smaller, the size of the whole product can be certainly reduced, and the miniaturization of the product is facilitated.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a preparation method thereof.
Background
With rapid development of the semiconductor industry, fan-out wafer level package (FOWLP) package structures are widely used in the semiconductor industry. The fan out technology mainly realizes multi-pin output and smaller output pin spacing, and the pin end of the traditional fan-out type package adopts a slotting mode to leak out a circuit and then carries out a ball mounting process again, so that the size is larger, the miniaturization of the product is not facilitated, and meanwhile, the maintenance and replacement cannot be realized.
Disclosure of Invention
The invention aims at providing a semiconductor packaging structure and a preparation method thereof, which can reduce the size of a ball implant, are beneficial to miniaturization of products and are convenient to maintain and replace the products.
Embodiments of the invention may be implemented as follows:
in a first aspect, an embodiment of the present invention provides a semiconductor package structure, including:
A base carrier plate;
A semiconductor device disposed on the base carrier;
the plastic package body is arranged on the base carrier plate and is coated outside the semiconductor device;
a first interposer and a second interposer disposed on the semiconductor device;
the plastic package body is provided with a first groove and a second groove which are communicated with the semiconductor device, the first adapter plate and the second adapter plate are respectively attached to the first groove and the second groove, one side, far away from the semiconductor device, of the first adapter plate is provided with a plurality of first solder balls, one side, far away from the semiconductor device, of the second adapter plate is provided with second solder balls, and the semiconductor device is electrically connected with the first adapter plate and the second adapter plate simultaneously.
In an optional embodiment, the first adapter plate and the second adapter plate are arranged at intervals, a buffer adhesive layer is arranged between the first adapter plate and the second adapter plate, and the buffer adhesive layer is arranged on the surface of the plastic package body.
In an alternative embodiment, the end of the first adapter plate, which is far away from the second adapter plate, is also provided with the buffer glue layer, and the end of the second adapter plate, which is far away from the first adapter plate, is also provided with the buffer glue layer.
In an alternative embodiment, the first groove and the second groove are communicated, and the first adapter plate and the second adapter plate are connected into a whole.
In an alternative embodiment, a first transfer pad is disposed on a side, close to the semiconductor device, of the first transfer plate, a second transfer pad is disposed on a side, close to the semiconductor device, of the second transfer plate, a first conductive pad and a second conductive pad are disposed on a side, away from the base carrier, of the semiconductor device, the first conductive pad is connected with the first transfer pad, and the second conductive pad is connected with the second transfer pad.
In an alternative embodiment, a first adhesive layer is arranged between the first adapter plate and the semiconductor device so that the first adapter plate is attached to the surface of the semiconductor device, and a second adhesive layer is arranged between the second adapter plate and the semiconductor device so that the second adapter plate is attached to the surface of the semiconductor device.
In an alternative embodiment, the projection of the first adapter plate on the base carrier plate at least partially overlaps with the projection of the semiconductor device on the base carrier plate, and the projection of the second adapter plate on the base carrier plate at least partially overlaps with the projection of the semiconductor device on the base carrier plate.
In an alternative embodiment, the first solder balls have a smaller size than the second solder balls.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor package structure, for manufacturing the semiconductor package structure, including:
mounting a semiconductor device on a base carrier plate;
forming a plastic package body coated outside the semiconductor device by plastic package on the base carrier plate;
Slotting on the plastic package body to form a first groove and a second groove which penetrate through the semiconductor device;
a first adapter plate is attached to the first groove, and a second adapter plate is attached to the second groove;
cutting the plastic package body and the substrate carrier plate;
The semiconductor device comprises a first adapter plate, a second adapter plate, a first solder ball, a second solder ball, a first adapter plate, a second adapter plate and a second adapter plate, wherein the first solder ball is arranged on one side, far away from the semiconductor device, of the first adapter plate, the second solder ball is arranged on one side, far away from the semiconductor device, of the second adapter plate, and the semiconductor device is electrically connected with the first adapter plate and the second adapter plate at the same time.
In a third aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor package structure, which is used for manufacturing the semiconductor package structure, including:
mounting a semiconductor device on a carrier;
forming a plastic package body which is coated outside the semiconductor device by plastic package on the carrier;
Removing the carrier to expose the semiconductor device on one side surface of the plastic package body;
forming a base carrier plate covered on the semiconductor device by plastic packaging on one side surface of the plastic packaging body;
slotting on the other side surface of the plastic package body to form a first groove and a second groove which penetrate through the semiconductor device;
a first adapter plate is attached to the first groove, and a second adapter plate is attached to the second groove;
cutting the plastic package body and the substrate carrier plate;
The semiconductor device comprises a first adapter plate, a second adapter plate, a first solder ball, a second solder ball, a first adapter plate, a second adapter plate and a second adapter plate, wherein the first solder ball is arranged on one side, far away from the semiconductor device, of the first adapter plate, the second solder ball is arranged on one side, far away from the semiconductor device, of the second adapter plate, and the semiconductor device is electrically connected with the first adapter plate and the second adapter plate at the same time.
The beneficial effects of the embodiment of the invention include, for example:
The embodiment of the invention provides a semiconductor packaging structure and a preparation method thereof, wherein a semiconductor device is arranged on a substrate carrier plate, a plastic package body which is coated outside the semiconductor device is arranged, and then a first adapter plate and a second adapter plate are arranged on the semiconductor device, wherein the plastic package body is provided with a first groove and a second groove which are communicated with the semiconductor device, the first adapter plate and the second adapter plate are respectively stuck in the first groove and the second groove, one side of the first adapter plate, which is far away from the semiconductor device, is provided with a first solder ball, one side of the second adapter plate, which is far away from the semiconductor device, is provided with a second solder ball, the semiconductor device is electrically connected with the first adapter plate and the second adapter plate at the same time, the wiring structure is realized by arranging the adapter plates, and the later product is convenient and reliable only by processing the adapter plates during maintenance and replacement. Meanwhile, an external circuit is realized through the solder balls on the adapter plate, the adapter plate can be prepared in advance, the size and the occupied space of the solder balls can be smaller, the size of the whole product can be certainly reduced, and the miniaturization of the product is facilitated. Compared with the prior art, the semiconductor packaging structure provided by the invention can reduce the size of the implant ball, is beneficial to miniaturization of products, and is convenient to maintain and replace the products.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1a is a schematic cross-sectional view of a semiconductor package according to a first embodiment of the present invention;
fig. 1b is a schematic cross-sectional view of a semiconductor package according to a first embodiment of the present invention;
Fig. 2 is a schematic diagram of the overall structure of a semiconductor package according to a first embodiment of the present invention;
Fig. 3 to 9 are process flow diagrams of a method for manufacturing a semiconductor package according to a first embodiment of the present invention;
fig. 10 is a schematic view of a semiconductor package structure according to a second embodiment of the present invention;
Fig. 11 is a schematic view of a semiconductor package structure according to a third embodiment of the present invention;
fig. 12 is a schematic view of a semiconductor package structure according to a fourth embodiment of the present invention;
fig. 13 is a schematic view of a semiconductor package structure according to a fifth embodiment of the present invention;
Fig. 14 is a schematic mounting diagram of a semiconductor package structure according to a fifth embodiment of the present invention.
The icons are 100-semiconductor packaging structure, 110-substrate carrier, 130-semiconductor device, 131-first conductive pad, 133-second conductive pad, 135-circuit layer, 150-plastic package, 151-first groove, 153-second groove, 170-first adapter plate, 171-first solder ball, 173-first adapter pad, 175-first adhesive layer, 180-buffer adhesive layer, 190-second adapter plate, 191-second solder ball, 193-second adapter pad, 195-second adhesive layer, and 200-carrier.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
As disclosed in the background art, in the conventional fan-out wafer packaging process, the problem that the grounding resistance of the oxide to the edge bonding pad is unstable is easily generated due to the adoption of the process of etching the substrate to open the grooves and then to implant balls. Meanwhile, in the fan-out type wafer chip packaging process, the problem of plastic package warpage easily exists due to mismatching of thermal expansion coefficients of various materials in the plastic packaging process. And in the traditional fan-out packaging structure, after the grooves are formed, the circuit layer is exposed, and then the ball planting process is performed, so that the ball planting size is larger, the occupied area of the whole solder ball is larger, the packaging size of the product is larger, and the miniaturization of the product is not facilitated. When the product is maintained, the circuit layer cannot be maintained, and only the circuit layer can be scrapped integrally, so that maintenance and replacement cannot be realized.
In order to solve the problems, the invention provides a novel semiconductor packaging structure and a preparation method thereof, which can avoid the process of ball implantation after etching a slot to expose a circuit layer, and the ball implantation size is small, thereby being beneficial to miniaturization of products. Meanwhile, when a problem occurs in a circuit layer of a product, only the adapter plate needs to be maintained and replaced, and the product is convenient to maintain and replace. It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1a and 2, the present embodiment provides a semiconductor package structure 100, which can avoid the process of ball placement after etching the slot to expose the circuit layer, and has a small ball placement size, which is beneficial to miniaturization of the product. Meanwhile, when a problem occurs in a circuit layer of a product, only the adapter plate needs to be maintained and replaced, and the product is convenient to maintain and replace.
The semiconductor package structure 100 provided in this embodiment includes a base carrier 110, a semiconductor device 130, a plastic package body 150, a first adapter plate 170 and a second adapter plate 190, where the semiconductor device 130 is disposed on the base carrier 110, the plastic package body 150 is disposed on the base carrier 110 and covers the semiconductor device 130, the first adapter plate 170 and the second adapter plate 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating through the semiconductor device 130, the first adapter plate 170 and the second adapter plate 190 are respectively attached in the first groove 151 and the second groove 153, a plurality of first solder balls 171 are disposed on a side of the first adapter plate 170 away from the semiconductor device 130, a second solder ball 191 is disposed on a side of the second adapter plate 190 away from the semiconductor device 130, and the semiconductor device 130 is electrically connected with the first adapter plate 170 and the second adapter plate 190.
In the actual manufacturing process, the preparation of the base carrier 110, the semiconductor device 130 and the plastic package body 150 is firstly completed, wherein the base carrier 110 can be the carrier 200 or the substrate, the preparation of the base carrier can complete the plastic package action of the plastic package body 150 before the plastic package body 150 is formed, namely after the semiconductor device 130 is attached to the base carrier 110, the base carrier 110 can also be a plastic package structure, the preparation of the base carrier can complete the plastic package action of the plastic package body 150 after the plastic package body 150 is formed, namely after the semiconductor device 130 is attached to the carrier 200, the plastic package body 150 is formed, and then the carrier 200 is removed and the plastic package body 110 is formed again at the same position. The specific structure of the substrate carrier 110 may be determined according to different process conditions and processes, and is not specifically limited herein.
It should be noted that, in the present embodiment, the base carrier 110 may be a carrier 200 or a substrate, and an adhesive layer may be further disposed on the base carrier 110, and the material of the adhesive layer may be polyimide, benzocyclobutene, etc., so as to perform an adhesive function, and meanwhile, the base carrier 110 performs a protection function on the semiconductor device 130, and also slows down a plastic package warpage phenomenon generated when the plastic package forms the plastic package body 150.
In other preferred embodiments of the present invention, the base carrier 110 may also be a plastic package structure, which is formed by plastic packaging using the same plastic packaging material as the plastic package body 150, and the warpage of the plastic package is greatly reduced due to the use of the same plastic packaging material.
In this embodiment, by disposing the semiconductor device 130 on the base carrier 110 and disposing the plastic package body 150 wrapping the semiconductor device 130, and then disposing the first interposer 170 and the second interposer 190 on the semiconductor device 130, wherein the plastic package body 150 is provided with the first groove 151 and the second groove 153 penetrating through the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively mounted in the first groove 151 and the second groove 153, wherein the side of the first interposer 170 away from the semiconductor device 130 is provided with the first solder ball 171, the side of the second interposer 190 away from the semiconductor device 130 is provided with the second solder ball 191, the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190 at the same time, and by disposing the interposer, only the interposer needs to be processed when the product is maintained and replaced in the later period, which is convenient and reliable. Meanwhile, an external circuit is realized through the solder balls on the adapter plate, the adapter plate can be prepared in advance, the size and the occupied space of the solder balls can be smaller, the size of the whole product can be certainly reduced, and the miniaturization of the product is facilitated.
It should be noted that, in this embodiment, the first interposer 170 and the second interposer 190 are prepared in advance, the first solder ball 171 and the second solder ball 191 thereon may also be formed in advance, and the first interposer 170 and the second interposer 190 are each formed with a circuit layer, so that connection with external circuits can be directly achieved through the first solder ball 171 and the second solder ball 191. The first adapter plate 170 and the second adapter plate 190 which are prepared in advance are adopted, so that the size of the solder balls can be smaller, the occupied space of the solder balls can be smaller, miniaturization of products is facilitated, maintenance and replacement of the products are facilitated, the preparation process of the products is greatly shortened through the preparation of the adapter plates in advance, the process difficulty is reduced, and the preparation efficiency of the products is improved.
In this embodiment, the first interposer 170 and the second interposer 190 are disposed at intervals, and a buffer adhesive layer 180 is disposed at least between the first interposer 170 and the second interposer 190, and the buffer adhesive layer 180 is disposed on the surface of the plastic package 150. Specifically, the first groove 151 and the second groove 153 are disposed on a side surface of the plastic package body 150 away from the substrate carrier 110 at intervals, and the size of the first groove 151 is matched with the first adapter plate 170, and the size of the second groove 153 is matched with the second adapter plate 190. In addition, the first interposer 170 and the second interposer 190 are both protruded from the plastic package body 150, so that a groove structure can be formed between the first interposer 170 and the second interposer 190, and the groove structure is used for forming the buffer adhesive layer 180, thereby realizing a buffer effect between the first interposer 170 and the second interposer 190.
In this embodiment, the buffer adhesive layer 180 is made of a material with a thermal expansion coefficient and a young's modulus lower than those of the plastic package body 150, and can deform preferentially to the plastic package body 150, so as to play a role in buffering, protect solder ball pads on the first interposer 170 and the second interposer 190, and avoid soldering cracks caused by the stress influence of the first solder ball 171 and the second solder ball 191. Meanwhile, the buffer layer may be designed around the first interposer 170 and the second interposer 190, or may be disposed at four corner regions of the semiconductor device 130, or designed at regions with larger deformation according to stress simulation data of the semiconductor device 130, so as to reduce stress and deformation of the semiconductor device 130.
It should be noted that, in the present embodiment, the first interposer 170 and the second interposer 190 are multiple, the first interposer 170 and the second interposer 190 are annularly disposed around the semiconductor device 130, each first interposer 170 and each second interposer 190 are electrically connected with the semiconductor device 130, wherein the first interposer 170 and the second interposer 190 have the same structure, and are separately disposed on two sides of the semiconductor device 130, so that the product is guaranteed to have enough signal access points. Of course, the specific number of first adapter plates 170 and second adapter plates 190 is not limited herein.
In the present embodiment, a first transfer pad 173 is disposed on a side of the first transfer plate 170 close to the semiconductor device 130, a second transfer pad 193 is disposed on a side of the second transfer plate 190 close to the semiconductor device 130, a first conductive pad 131 and a second conductive pad 133 are disposed on a side of the semiconductor device 130 away from the base carrier 110, the first conductive pad 131 is connected to the first transfer pad 173, and the second conductive pad 133 is connected to the second transfer pad 193. Specifically, the first transfer board 170 is internally provided with a first circuit layer, the first transfer pad 173 is connected to the first circuit layer through a conductive line, and the plurality of first solder balls 171 are connected to the first circuit layer, thereby realizing signal output. The second interposer 190 is provided therein with a second wiring layer, the second interposer pad 193 is connected to the second wiring layer through a conductive wire, and the plurality of second solder balls 191 are connected to the second wiring layer. The first transfer pad 173 and the first conductive pad 131 are copper pads, and are connected by Cu-Cu soldering, and the second transfer pad 193 and the second conductive pad 133 are copper pads, and are also connected by Cu-Cu soldering. Meanwhile, the first and second transfer plates 170 and 190 may be polyimide, benzocyclobutene, or the like as a dielectric layer, and wiring and ball mounting may be completed on the dielectric layer.
Note that, in this embodiment, the semiconductor device 130 is a chip, and the first interposer 170 and the second interposer 190 are directly connected to pads on the chip, which may be implemented as a chip package. In other preferred embodiments of the present invention, referring to fig. 1b, the semiconductor device 130 may also be a combined structure of a chip and a circuit layer 135, that is, the upper surface of the chip is provided with the circuit layer 135, and the first interposer 170 and the second interposer 190 are disposed on the circuit layer 135 of the chip, so as to change the packaging structure of the chip and improve the packaging manner of the chip.
In the present embodiment, a first adhesive layer 175 is disposed between the first interposer 170 and the semiconductor device 130 to attach the first interposer 170 to the surface of the semiconductor device 130, and a second adhesive layer 195 is disposed between the second interposer 190 and the semiconductor device 130 to attach the second interposer 190 to the surface of the semiconductor device 130. Specifically, the first adhesive layer 175 and the second adhesive layer 195 may be thermoplastic adhesive layers with lower melting points, so that the first adapter plate 170 and the second adapter plate 190 can be detached smoothly after heating, and convenient disassembly and assembly are realized. Meanwhile, by arranging the first adhesive layer 175 and the second adhesive layer 195, the adhesive fixing effect of the first adapter plate 170 and the second adapter plate 190 can be improved, and the reliability of products can be improved.
In the present embodiment, the projection of the first interposer 170 onto the base carrier 110 at least partially overlaps the projection of the semiconductor device 130 onto the base carrier 110, and the projection of the second interposer 190 onto the base carrier 110 at least partially overlaps the projection of the semiconductor device 130 onto the base carrier 110. Specifically, in the present embodiment, the projected edges of the first interposer 170 on the base carrier 110 and the projected edges of the second interposer 190 on the base carrier 110 overlap, i.e. the first interposer 170 is flush with one side of the semiconductor device 130 and the second interposer 190 is flush with the other side of the semiconductor device 130, so that the product structure with smaller size can be cut out during subsequent dicing.
In the present embodiment, the ball implantation sizes of the first solder ball 171 and the second solder ball 191 are the same and are all 10 μm-20 μm, and since the first interposer 170 and the second interposer 190 adopt the advanced manufacturing process, the ball implantation sizes of the first solder ball 171 and the second solder ball 191 can be smaller, and more solder balls can be disposed in the same ball implantation area, so that the output terminals are more, and the product performance is greatly improved. Meanwhile, under the requirement of the same output end number, the ball planting area can be smaller, and the miniaturization of products is facilitated.
Referring to fig. 3 to 7 in combination, the present embodiment also provides a method for manufacturing a semiconductor package structure 100, wherein the substrate carrier 110 is a carrier 200 that is kept, that is, a step of removing the carrier 200 is not required, and specifically, the method provided in this embodiment includes the following steps:
s1a, mounting the semiconductor device 130 on the base carrier 110.
Referring to fig. 3 in detail, a carrier 200 is provided, and a film layer is disposed on the carrier 200, and then the semiconductor device 130 is mounted, wherein the first conductive pads 131 and the second conductive pads 133 on the semiconductor device 130 are disposed upwards, so that the back surface of the semiconductor device 130 is mounted on the film layer of the carrier 200.
S2a, plastic packaging is carried out on the base carrier plate 110 to form a plastic packaging body 150 which is coated outside the semiconductor device 130.
Referring to fig. 4 in combination, specifically, after the mounting of the semiconductor device 130 is completed, a plastic package body 150 is formed by using a plastic package process, and the plastic package body 150 is wrapped outside the semiconductor device 130.
S3a, a first groove 151 and a second groove 153 penetrating to the semiconductor device 130 are formed in the molding body 150.
Referring to fig. 5 in detail, after forming the molding body 150, first grooves 151 and second grooves 153 are formed on the molding body 150 at positions corresponding to the semiconductor device 130 through a laser grooving process, wherein the first grooves 151 and the second grooves 153 are spaced apart and correspond to the first conductive pads 131 and the second conductive pads 133 on the semiconductor device 130, respectively, and the first conductive pads 131 and the second conductive pads 133 are exposed.
S4a, mounting the first adapter plate 170 in the first groove 151 and mounting the second adapter plate 190 into the second groove 153.
Referring to fig. 6 in combination, specifically, the first and second transfer plates 170 and 190 may be simultaneously mounted, and adhesive may be applied to the bonding surfaces of the first and second transfer plates 170 and 190 before mounting, and the first and second adhesive layers 175 and 195 may be formed after bonding. In the mounting, it is also necessary to connect the first transfer pad 173 on the first transfer board 170 to the first conductive pad 131 by cu—cu soldering, and connect the second transfer pad 193 on the second transfer board 190 to the second conductive pad 133 by cu—cu soldering.
Here, the first interposer 170 and the second interposer 190 are prepared in advance, and wiring and ball placement are completed.
Referring to fig. 7 in combination, after the mounting of the first and second transfer plates 170 and 190 is completed, a buffer adhesive layer 180 is further required to be disposed between the first and second transfer plates 170 and 190. Specifically, the first interposer 170 and the second interposer 190 are both protruded from the plastic package body 150, so that a groove structure can be formed between the first interposer 170 and the second interposer 190, then a dispensing process is utilized to fill the groove structure, and the glue adopts a material with a thermal expansion coefficient and a young modulus lower than those of the plastic package body 150, so that the material is deformed in preference to the plastic package body 150, plays a role of a buffer layer, protects solder ball pads at the bottom of the interposer, and is not affected by stress to cause solder ball welding cracks.
S5a, cutting the plastic package body 150 and the base carrier plate 110.
With continued reference to fig. 1, specifically, the plastic package body 150 and the base carrier 110 are cut along a dicing street, where the dicing street may be as close to the first interposer 170 and the second interposer 190 as possible, and preferably, the dicing street may be cut along edges of the first interposer 170 and the second interposer 190, so as to ensure that the size of the product structure after dicing is further reduced, and the preparation of the product is completed after dicing.
The present embodiment also provides another method for manufacturing a semiconductor package structure, which is used for manufacturing the semiconductor package structure 100 as described above, wherein the substrate carrier 110 is used for plastic packaging the structure, that is, a step of removing the carrier 200 is needed, and specifically, the method provided in the present embodiment includes the following steps:
s1b, mounting the semiconductor device 130 on the carrier 200.
With reference to fig. 3, in particular, a carrier 200 is provided, and a film layer is disposed on the carrier 200, and then the semiconductor device 130 is mounted, wherein the first conductive pads 131 and the second conductive pads 133 on the semiconductor device 130 are disposed upwards, so that the back surface of the semiconductor device 130 is mounted on the film layer of the carrier 200. The adhesive film layer is preferably a UV adhesive layer, so that the subsequent stripping action is facilitated.
S2b, plastic packaging is carried out on the carrier 200 to form the plastic packaging body 150 which is coated outside the semiconductor device 130.
With continued reference to fig. 4, specifically, after the semiconductor device 130 is mounted, a plastic package body 150 is formed on the carrier 200 by using a plastic package process, and the plastic package body 150 is wrapped around the semiconductor device 130.
And S3b, removing the carrier 200 to expose the semiconductor device 130 on one side surface of the plastic package 150.
Referring to fig. 8 in combination, specifically, the UV light is irradiated to detach the UV glue layer, thereby completing the peeling action of the carrier 200 and exposing the semiconductor device 130.
And S4b, molding and forming the base carrier plate 110 covered on the semiconductor device 130 on one side surface of the molding body 150.
Referring to fig. 9 in combination, specifically, after removing the carrier 200, the plastic packaging operation is performed again, and the substrate carrier 110 is formed by plastic packaging on a surface of one side of the plastic package body 150, wherein the substrate carrier 110 is in a plastic packaging structure, and the plastic packaging material of the substrate carrier is consistent with that of the plastic package body 150.
The subsequent steps correspond to the steps S3a-S5a described above and will not be described in detail here.
In summary, the embodiment provides a semiconductor package structure 100 and a method for manufacturing the same, in which a semiconductor device 130 is disposed on a base carrier 110, a plastic package body 150 is disposed on the base carrier 110 and is wrapped around the semiconductor device 130, and then a first interposer 170 and a second interposer 190 are disposed on the semiconductor device 130, wherein the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating through the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively mounted in the first groove 151 and the second groove 153, a first solder ball 171 is disposed on a side of the first interposer 170 away from the semiconductor device 130, a second solder ball 191 is disposed on a side of the second interposer 190 away from the semiconductor device 130, the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190, and a wiring structure is realized by disposing the first interposer 170 and the second interposer. Meanwhile, an external circuit is realized through the solder balls on the adapter plate, the adapter plate can be prepared in advance, the size and the occupied space of the solder balls can be smaller, the size of the whole product can be certainly reduced, and the miniaturization of the product is facilitated.
Second embodiment
Referring to fig. 10, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned.
In this embodiment, the semiconductor package structure 100 includes a base carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, where the semiconductor device 130 is disposed on the base carrier 110, the plastic package body 150 is disposed on the base carrier 110 and covers the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating through the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, a plurality of first solder balls 171 are disposed on a side of the first interposer 170 away from the semiconductor device 130, a second solder ball 191 is disposed on a side of the second interposer 190 away from the semiconductor device 130, and the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190.
In this embodiment, the first interposer 170 and the second interposer 190 are disposed at intervals, and a buffer adhesive layer 180 is disposed between the first interposer 170 and the second interposer 190, and the buffer adhesive layer 180 is disposed on the surface of the plastic package 150. Meanwhile, the end of the first adapter plate 170 far away from the second adapter plate 190 is also provided with a buffer adhesive layer 180, and the end of the second adapter plate 190 far away from the first adapter plate 170 is also provided with a buffer adhesive layer 180. Specifically, the buffer glue layers 180 are disposed on both sides of the first adapter plate 170 and both sides of the second adapter plate 190, so that a better buffer effect can be achieved.
Third embodiment
Referring to fig. 11, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned.
In this embodiment, the semiconductor package structure 100 includes a base carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, where the semiconductor device 130 is disposed on the base carrier 110, the plastic package body 150 is disposed on the base carrier 110 and covers the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating through the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, a plurality of first solder balls 171 are disposed on a side of the first interposer 170 away from the semiconductor device 130, a second solder ball 191 is disposed on a side of the second interposer 190 away from the semiconductor device 130, and the semiconductor device 130 is simultaneously electrically connected with the first interposer 170 and the second interposer 190.
In the present embodiment, the first groove 151 and the second groove 153 communicate, and the first adapter plate 170 and the second adapter plate 190 are integrally connected. Specifically, the first groove 151 and the second groove 153 are communicated into a whole, that is, the buffer glue layer 180 is not disposed between the first adapter plate 170 and the second adapter plate 190, and the first adapter plate 170 and the second adapter plate 190 are also connected into a whole, so that the whole adapter plate mounting structure can be conveniently formed, and the mounting of the adapter plates is more convenient. Meanwhile, the problems of unstable resistance of the semiconductor device 130, falling of a welding layer and the like caused by oxidation of various chemical agents generated on a bonding pad of the semiconductor device 130 in the conventional fan-out type semiconductor device 130 manufacturing process, plasma etching/exposure developing and the like can be avoided.
Fourth embodiment
Referring to fig. 12, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned.
The semiconductor package structure 100 provided in this embodiment includes a base carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, where the semiconductor device 130 is disposed on the base carrier 110, the plastic package body 150 is disposed on the base carrier 110 and covers the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating through the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, a plurality of first solder balls 171 are disposed on a side of the first interposer 170 away from the semiconductor device 130, a second solder ball 191 is disposed on a side of the second interposer 190 away from the semiconductor device 130, and the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190.
In the present embodiment, the projection of the first interposer 170 onto the base carrier 110 at least partially overlaps the projection of the semiconductor device 130 onto the base carrier 110, and the projection of the second interposer 190 onto the base carrier 110 at least partially overlaps the projection of the semiconductor device 130 onto the base carrier 110. Specifically, the projection of the first interposer 170 exceeds the projection of the semiconductor device 130, and the projection of the second interposer 190 exceeds the projection of the semiconductor device 130, i.e., the first interposer 170 protrudes outward from one side edge of the semiconductor device 130, and the second interposer 190 protrudes outward from the other side edge of the semiconductor device 130.
The semiconductor package structure 100 provided in this embodiment adopts the first interposer 170 and the second interposer 190 with widened dimensions, so that the first interposer 170 and the second interposer 190 can fall outside the dimensions of the semiconductor device 130, the number of wires and the degree of wire density on the first interposer 170 and the second interposer 190 can be greatly improved, and the output solder ball ends can be denser, which is helpful for improving the product performance.
Fifth embodiment
Referring to fig. 13, the present embodiment provides a semiconductor package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned.
The semiconductor package structure 100 provided in this embodiment includes a base carrier 110, a semiconductor device 130, a plastic package body 150, a first interposer 170 and a second interposer 190, where the semiconductor device 130 is disposed on the base carrier 110, the plastic package body 150 is disposed on the base carrier 110 and covers the semiconductor device 130, the first interposer 170 and the second interposer 190 are disposed on the semiconductor device 130, the plastic package body 150 is provided with a first groove 151 and a second groove 153 penetrating through the semiconductor device 130, the first interposer 170 and the second interposer 190 are respectively attached in the first groove 151 and the second groove 153, a plurality of first solder balls 171 are disposed on a side of the first interposer 170 away from the semiconductor device 130, a second solder ball 191 is disposed on a side of the second interposer 190 away from the semiconductor device 130, and the semiconductor device 130 is electrically connected with the first interposer 170 and the second interposer 190.
In this embodiment, the size of the first solder ball 171 on the first interposer 170 is smaller than the size of the second solder ball 191 on the second interposer 190, so that the first interposer 170 and the second interposer 190 can be suitable for different output ports, and solder balls with different sizes can be attached to different pad areas during subsequent board loading, so as to realize different pad areas and functional partitioning.
Referring to fig. 14, specifically, in actual board mounting, the semiconductor package structure 100 is mounted on the circuit board 300, wherein the first solder balls 171 and the second solder balls 191 are mounted on different areas of the circuit board 300, and at the same time, the respective mounting can be implemented for the areas with different heights, further implementing different pad areas and functional partitioning.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A semiconductor package structure, comprising:
A base carrier plate;
A semiconductor device disposed on the base carrier;
the plastic package body is arranged on the base carrier plate and is coated outside the semiconductor device;
a first interposer and a second interposer disposed on the semiconductor device;
The plastic package body is provided with a first groove and a second groove which penetrate through the semiconductor device, the first adapter plate and the second adapter plate are respectively attached in the first groove and the second groove, one side, far away from the semiconductor device, of the first adapter plate is provided with a plurality of first solder balls, one side, far away from the semiconductor device, of the second adapter plate is provided with second solder balls, and the semiconductor device is electrically connected with the first adapter plate and the second adapter plate at the same time;
The first adapter plate and the second adapter plate are prepared in advance, a first adhesive layer is arranged between the first adapter plate and the semiconductor device so that the first adapter plate is attached to the surface of the semiconductor device, a second adhesive layer is arranged between the second adapter plate and the semiconductor device so that the second adapter plate is attached to the surface of the semiconductor device, and the first adhesive layer and the second adhesive layer are thermoplastic adhesive film layers.
2. The semiconductor package according to claim 1, wherein the first interposer and the second interposer are disposed at intervals, a buffer adhesive layer is disposed at least between the first interposer and the second interposer, and the buffer adhesive layer is disposed on a surface of the plastic package.
3. The semiconductor package according to claim 2, wherein the buffer adhesive layer is also disposed at an end of the first interposer remote from the second interposer, and the buffer adhesive layer is also disposed at an end of the second interposer remote from the first interposer.
4. The semiconductor package according to claim 1, wherein the first recess and the second recess communicate, and the first interposer and the second interposer are integrally connected.
5. The semiconductor package structure according to claim 1, wherein a first transfer pad is provided on a side of the first transfer board adjacent to the semiconductor device, a second transfer pad is provided on a side of the second transfer board adjacent to the semiconductor device, a first conductive pad and a second conductive pad are provided on a side of the semiconductor device away from the base carrier, the first conductive pad is connected to the first transfer pad, and the second conductive pad is connected to the second transfer pad.
6. The semiconductor package according to claim 1, wherein the projection of the first interposer onto the substrate carrier at least partially overlaps the projection of the semiconductor device onto the substrate carrier, and wherein the projection of the second interposer onto the substrate carrier at least partially overlaps the projection of the semiconductor device onto the substrate carrier.
7. The semiconductor package according to claim 1, wherein the first solder balls have a smaller size than the second solder balls.
8. A method for manufacturing a semiconductor package according to any one of claims 1 to 7, comprising:
mounting a semiconductor device on a base carrier plate;
forming a plastic package body coated outside the semiconductor device by plastic package on the base carrier plate;
Slotting on the plastic package body to form a first groove and a second groove which penetrate through the semiconductor device;
a first adapter plate is attached to the first groove, and a second adapter plate is attached to the second groove;
cutting the plastic package body and the substrate carrier plate;
The semiconductor device comprises a first adapter plate, a second adapter plate, a first solder ball, a second solder ball, a first adapter plate, a second adapter plate and a second adapter plate, wherein the first solder ball is arranged on one side, far away from the semiconductor device, of the first adapter plate, the second solder ball is arranged on one side, far away from the semiconductor device, of the second adapter plate, and the semiconductor device is electrically connected with the first adapter plate and the second adapter plate at the same time.
9. A method for manufacturing a semiconductor package according to any one of claims 1 to 7, comprising:
mounting a semiconductor device on a carrier;
forming a plastic package body which is coated outside the semiconductor device by plastic package on the carrier;
Removing the carrier to expose the semiconductor device on one side surface of the plastic package body;
forming a base carrier plate covered on the semiconductor device by plastic packaging on one side surface of the plastic packaging body;
slotting on the other side surface of the plastic package body to form a first groove and a second groove which penetrate through the semiconductor device;
a first adapter plate is attached to the first groove, and a second adapter plate is attached to the second groove;
cutting the plastic package body and the substrate carrier plate;
The semiconductor device comprises a first adapter plate, a second adapter plate, a first solder ball, a second solder ball, a first adapter plate, a second adapter plate and a second adapter plate, wherein the first solder ball is arranged on one side, far away from the semiconductor device, of the first adapter plate, the second solder ball is arranged on one side, far away from the semiconductor device, of the second adapter plate, and the semiconductor device is electrically connected with the first adapter plate and the second adapter plate at the same time.
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| CN112701088A (en) * | 2020-12-29 | 2021-04-23 | 华进半导体封装先导技术研发中心有限公司 | Secondary plastic package structure and manufacturing method thereof |
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| JP2000022039A (en) * | 1998-07-06 | 2000-01-21 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacture |
| US20120267782A1 (en) * | 2011-04-25 | 2012-10-25 | Yung-Hsiang Chen | Package-on-package semiconductor device |
| JP5921297B2 (en) * | 2012-04-09 | 2016-05-24 | キヤノン株式会社 | Multilayer semiconductor device, printed circuit board, and method of manufacturing multilayer semiconductor device |
| CN110676240A (en) * | 2019-10-16 | 2020-01-10 | 上海先方半导体有限公司 | 2.5D packaging structure and manufacturing method thereof |
| CN111933590B (en) * | 2020-09-11 | 2021-01-01 | 甬矽电子(宁波)股份有限公司 | Packaging structure and manufacturing method thereof |
| CN112908946B (en) * | 2021-01-18 | 2023-05-23 | 上海先方半导体有限公司 | Packaging structure for reducing warpage of plastic packaging wafer and manufacturing method thereof |
| CN113707651A (en) * | 2021-10-29 | 2021-11-26 | 甬矽电子(宁波)股份有限公司 | Semiconductor packaging structure and preparation method thereof |
| CN113707621B (en) * | 2021-10-29 | 2022-02-08 | 甬矽电子(宁波)股份有限公司 | Semiconductor packaging structure and preparation method thereof |
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| CN110211954A (en) * | 2019-06-17 | 2019-09-06 | 上海先方半导体有限公司 | A kind of multichip packaging structure and its manufacturing method |
| CN112701088A (en) * | 2020-12-29 | 2021-04-23 | 华进半导体封装先导技术研发中心有限公司 | Secondary plastic package structure and manufacturing method thereof |
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