CN114256064A - Method for improving back-etched photoresist process window - Google Patents
Method for improving back-etched photoresist process window Download PDFInfo
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- CN114256064A CN114256064A CN202111409074.7A CN202111409074A CN114256064A CN 114256064 A CN114256064 A CN 114256064A CN 202111409074 A CN202111409074 A CN 202111409074A CN 114256064 A CN114256064 A CN 114256064A
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- layer
- filling material
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- carbon filling
- etching
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 229920002120 photoresistant polymer Polymers 0.000 title claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 35
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 12
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000004528 spin coating Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 description 7
- 238000009825 accumulation Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000005457 optimization Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a method for improving a back-etching photoresist process window, which comprises the steps of providing a substrate, forming an active area on the surface of the substrate, and forming a plurality of first structure bodies, a plurality of second structure bodies and a thin film layer in the active area, wherein the first structure bodies are higher than the second structure bodies and are provided with an upper layer structure and a lower layer structure; forming a carbon filling material layer having a first thickness on the substrate covering the plurality of first structures, the plurality of second structures, and the thin film layer; performing first etching to remove the carbon filling material layer, so that the residual thickness of the top surface of the first structure is a second thickness; and carrying out second etching to enable the upper layer structure to be etched and the lower layer structure to be exposed, wherein the carbon filling material layer with the second thickness enables the thin film layer not to be etched.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving a back-etched photoresist process window.
Background
In the existing technological process of 28nm high-k dielectric photoetching materials, the back-etching photoresist process cannot realize nickel silicide protection and no defect at the same time, and a technological window is not available; the current problem to be solved is that the loss of nickel silicide is serious by sacrificing the thickness of nickel silicide under the condition of ensuring no defects. Meanwhile, the mobility of the photoresist in different density areas on the wafer graph is different, so that the photoresist accumulation on the grid electrode of the high density area is higher. Therefore, a layer of mask is required to be added, and the gate with a higher photoresist accumulation and a larger size is opened first, and then the whole etching is performed.
The existing 28nm high-k dielectric photoetching material process flow increases the process cost and the process complexity, and is not beneficial to the mass production of products.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a method for improving a back-etching photoresist process window, which is used to solve the problem that the back-etching photoresist process in the prior art cannot simultaneously achieve nickel silicide protection and defect free, and has no process window.
To achieve the above and other related objects, the present invention provides a method for improving a back-etching photoresist process window, comprising:
providing a substrate, forming an active region on the surface of the substrate, and forming a plurality of first structural bodies, a plurality of second structural bodies and a thin film layer in the active region, wherein the first structural bodies are higher than the second structural bodies, and each first structural body has an upper layer structure and a lower layer structure;
forming a carbon filling material layer covering the plurality of first structures, the plurality of second structures, and the thin film layer on the substrate; the carbon filler material layer has a first thickness;
step three, performing first etching to remove the carbon filling material layer in the step two, so that the thickness of the carbon filling material layer left on the top surface of the first structure is a second thickness;
and fourthly, performing second etching to enable the upper layer structure to be partially etched, wherein the lower layer structure is not etched due to the partially etched upper layer structure, and the thin film layer is not etched due to the carbon filling material layer with the second thickness.
Optionally, the material of the thin film layer in the first step is nickel silicide.
Optionally, the carbon filling material layer in the second step is a spin-on carbon filling material used in a 14nm process.
Optionally, the lower layer structure in the first step is a gate.
Optionally, the upper layer structure in the first step is a hard mask layer.
Optionally, the hard mask layer is divided into two layers, an upper layer is an oxide layer, and a lower layer is a silicon nitride layer.
Optionally, the second structural body in the first step is a pad.
Optionally, the thickness of the carbon filling material layer in the second step is 1000 to 4000 angstroms.
Optionally, the second thickness in step three is 210 to 310 angstroms.
Optionally, the method is used for a process flow of 28nm technology nodes.
As described above, the method for improving the etch back photoresist process window of the present invention has the following advantages: one photomask is saved, and the product cost is reduced; the fluidity and gap filling advantages of the carbon filling material used by spinning in the 14nm process can improve the planarization on the graph, and are beneficial to reducing the accumulation problem among areas with different densities; the excellent thermal stability and etching resistance of the spin-on carbon filling material used in the 14nm process provide a better etching rate process optimization window for etching, and compared with photoresist and the like, the etching rate is lower, so that the etching process is more convenient to keep stable; compared with a photoresist scheme, the problem of coverage alignment does not need to be considered, and the process is simpler.
Drawings
FIG. 1 is a schematic flow chart of the process of the present invention;
FIG. 2 shows a schematic process flow diagram of a high-k dielectric photolithographic material provided for the prior art;
FIG. 3 is a schematic diagram of a method for improving a process window according to the present invention;
FIG. 4 is a cross-sectional view of a wafer after a first etching process according to the present invention.
FIG. 5 is a schematic view showing the etch back and the horn height of the present invention;
FIG. 6 shows a schematic of the NiSi loss of the present invention.
The structure comprises a substrate 1, a second structure 2, a first structure 3, a thin film layer 4, a carbon filling material layer 5, a lower layer structure 6 and an upper layer structure 7.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. two, in the existing 28nm high-k dielectric photoresist material scheme, the mobility of the photoresist in different density areas on the wafer pattern is different, so that the photoresist accumulation on the gate of the high-density area is higher, and the photoresist cannot be effectively planarized on the pattern, so that a layer of photomask needs to be added, the gate with larger size is opened first, the higher photoresist thickness is reduced, and then the whole etching is performed, but the process of etching back the photoresist cannot realize nickel silicide protection and defect free at the same time, and a process window is not available; the current solution is to sacrifice nickel silicide thickness and loss of nickel silicide is severe while ensuring defect free.
Referring to the first embodiment, a method for improving a back-etching photoresist process window is provided, which comprises:
providing a substrate 1, forming an active area on the surface of the substrate 1, forming a plurality of first structure 3 bodies, a plurality of second structure 2 bodies and a thin film layer 4 in the active area, wherein the thin film layer 4 covers the local surface of the active area, the first structure 3 bodies are higher than the second structure 2 bodies, and the first structure 3 bodies are provided with an upper layer structure 7 and a lower layer structure 6;
in a possible embodiment, the upper layer 7 in the first structure 3 is a hard mask layer. In one possible embodiment, the underlying structure 6 in the first structure 3 is a gate.
In one possible embodiment, the second structure 2 is a pad.
In one possible embodiment, the material of the thin film layer 4 in the first step is nickel silicide, and the nickel silicide is seriously lost in the existing process flow of 28nm high-k dielectric photoetching material.
Step two, referring to fig. three, a carbon filling material layer 5 with a first thickness is formed on the substrate 1 to cover the plurality of first structures 3, the plurality of second structures 2 and the thin film layer 4;
in a possible embodiment, the carbon filling material in the second step is LT80003, and the thickness is 1000 to 4000 angstroms, because of the fluidity and gap filling advantages of the spin-on carbon filling material used in the 14nm process, the deposition on the pattern may not be high, and the planarization on the pattern may be improved, thereby being beneficial to reducing the deposition problem between regions with different densities; the excellent thermal stability and the etching resistance of the Spin-on Carbon used in 14nm Process (Spin on Carbon used in 14nm Process) provide a better etching rate Process optimization window for etching.
Step three, referring to the fourth drawing, the carbon filling material layer 5 in the step two is removed by first etching in a plasma etching manner without exposing and developing a photomask, so that the residual thickness of the top surface of the first structure 3 is a second thickness;
referring to fig. five and fig. six, the abscissa is the thickness of the carbon filling material layer 5, the ordinate is the height of the ox Horn (Horn height), which means the height of the ox Horn is higher than the height of the gate 6, in the case of using the carbon filling material layer 5 instead of the photoresist, it can be seen from the experimental result that in one possible embodiment, the second thickness in the third step is preferably 210 a to 310 a, so that the process window is expanded from 0 a to 100 a.
And fourthly, performing second etching to enable the upper layer structure 7 to be partially etched, wherein the lower layer structure 6 is not etched due to the partially etched upper layer structure 7, and the thin film layer 4 is not etched due to the carbon filling material layer with the second thickness.
In one possible embodiment, the hard mask layer is divided into two layers, the upper layer is an oxide layer, and the lower layer is a silicon nitride layer.
Specifically, the thickness of the oxide layer is: the thickness of the silicon nitride layer is 3: 1 to 4: 1, the second etching step is to etch the oxide layer, the silicon nitride layer is not required to be etched, the grid electrode can be protected, and the silicon nitride layer can be cleaned by a WET process after the second etching step in the actual process.
In a possible implementation manner, the hard mask layer on the gate is etched until the silicon nitride layer on the top of the gate is etched, so long as the oxide layer is etched, the silicon nitride layer can be completely removed by the following process, no defect is formed, and meanwhile, the protection effect of the carbon filling material layer 5 does not cause loss to the nickel silicide film when the oxide layer on the gate is etched.
In one possible embodiment, the method is used in a process flow for 28nm technology nodes.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In conclusion, the invention saves one light shield and reduces the product cost; the fluidity and gap filling advantages of the spin-on carbon filling material used in the 14nm process can improve the flatness on the pattern, and are beneficial to reducing the accumulation problem among areas with different densities; the excellent thermal stability and etching resistance of the spin-on carbon filling material used in the 14nm process provide a better etching rate process optimization window for etching, and compared with photoresist and the like, the etching rate is lower, so that the etching process is more convenient to keep stable; compared with a photoresist scheme, the problem of coverage alignment does not need to be considered, and the process is simpler. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111409074.7A CN114256064B (en) | 2021-11-25 | 2021-11-25 | A method for improving the process window of photoresist etching back |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111409074.7A CN114256064B (en) | 2021-11-25 | 2021-11-25 | A method for improving the process window of photoresist etching back |
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| CN114256064A true CN114256064A (en) | 2022-03-29 |
| CN114256064B CN114256064B (en) | 2025-03-14 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6524938B1 (en) * | 2002-02-13 | 2003-02-25 | Taiwan Semiconductor Manufacturing Company | Method for gate formation with improved spacer profile control |
| CN105355547A (en) * | 2014-08-21 | 2016-02-24 | 中芯国际集成电路制造(上海)有限公司 | Fabrication method of grid and fabrication method of memory device |
| CN109065445A (en) * | 2018-07-13 | 2018-12-21 | 上海华力集成电路制造有限公司 | The manufacturing method of metal gate structure |
| CN110571194A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造（天津）有限公司 | Manufacturing method of semiconductor device |
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2021
- 2021-11-25 CN CN202111409074.7A patent/CN114256064B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6524938B1 (en) * | 2002-02-13 | 2003-02-25 | Taiwan Semiconductor Manufacturing Company | Method for gate formation with improved spacer profile control |
| CN105355547A (en) * | 2014-08-21 | 2016-02-24 | 中芯国际集成电路制造(上海)有限公司 | Fabrication method of grid and fabrication method of memory device |
| CN110571194A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造（天津）有限公司 | Manufacturing method of semiconductor device |
| CN109065445A (en) * | 2018-07-13 | 2018-12-21 | 上海华力集成电路制造有限公司 | The manufacturing method of metal gate structure |
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| CN114256064B (en) | 2025-03-14 |
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