CN114253821B - Method and device for analyzing GPU performance and computer storage medium - Google Patents

Abstract

The embodiment of the present invention discloses a method, a device and a computer storage medium for analyzing GPU performance; the method may include: obtaining an instruction list obtained by running a target program in a set environment, the number of threads to be started, and the effect of each thread on all the execution result of each instruction in the instruction list; start the thread simulator in the GPU performance model to be analyzed according to the number of threads to be started by the simulation scheduler in the GPU performance model to be analyzed; each thread simulator traverse each instruction in the instruction list, and execute the instruction according to the instruction execution control value of each instruction during the traversal process to measure the duration of executing the traversed instruction; when all instructions in the instruction list have been traversed , to obtain the total execution time of all thread simulators executing all the instructions in the instruction list.

Description

A method, device and computer storage medium for analyzing GPU performance

technical field

Embodiments of the present invention relate to the technical field of graphics processing units (GPUs, Graphics Processing Units), and in particular, to a method, an apparatus, and a computer storage medium for analyzing GPU performance.

Background technique

In GPU performance statistics, Instructions Per Cycle (IPC, Instructions Per Cycle) is a relatively important GPU performance indicator, which represents how many instructions the GPU can process in each clock cycle; The execution time and the main frequency of the system are calculated to obtain the IPC.

In the process of GPU performance statistics, it is usually necessary to model GPU performance. Specifically, the performance of GPU is usually modeled in two ways: one is simulation modeling, such as using software simulation to build a simulation model of GPU, and performing real execution process according to the simulation model to obtain real performance data of GPU; The second is analytical modeling, for example, by constructing a certain mapping function (also called an analytical model) to analyze and process the input of the GPU, thereby calculating the corresponding performance results.

For the simulation modeling method, although the hardware execution process can be simulated and real simulation data can be obtained; however, since the simulation model needs to simulate the execution of the real GPU, the operation efficiency is low. If the GPU architecture needs to be adjusted, then Therefore, it is necessary to reconstruct the simulation model for the GPU after the architecture adjustment. Therefore, the use of simulation modeling for GPU performance statistics has the defects of relatively poor scalability and long development cycle. For the analysis modeling method, the analysis model does not need to simulate the real operation process of the instruction, and only needs to perform modeling analysis operations on the input instruction information to obtain the performance result data. Therefore, the analysis modeling method is used to calculate the running efficiency of GPU performance statistics. It is very high, the structure design is simple, and the scalability is strong; however, in the specific implementation process, if the analysis model does not process the output instructions finely enough, it will cause a large error rate in the final GPU performance statistics.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present invention are expected to provide a method, apparatus and computer storage medium for analyzing GPU performance, which can reduce the error rate of GPU performance statistics based on the analysis and modeling method, and provide more accurate performance data about GPU.

The technical solution of the embodiment of the present invention is realized as follows:

In a first aspect, an embodiment of the present invention provides a method for analyzing GPU performance, the method comprising:

Obtain the instruction list obtained by running the target program under the setting environment, the number of threads to be started, and the execution result of each thread on each instruction in the instruction list; wherein, the execution result includes the instruction for each instruction. execution control value;

Start the thread simulator in the GPU performance model to be analyzed according to the number of threads to be started by the simulation scheduler in the GPU performance model to be analyzed;

Each thread simulator traverses each instruction in the instruction list, and executes the instruction according to the instruction execution control value of each instruction during the traversal process, so as to measure the duration of executing the traversed instruction;

When all the instructions in the instruction list have been traversed, the total execution time of all the thread simulators executing all the instructions in the instruction list is obtained.

In a second aspect, an embodiment of the present invention provides an apparatus for analyzing GPU performance, the apparatus includes: an acquisition part, a simulation scheduler, a thread simulator, and a statistics part; wherein,

The obtaining part is configured to obtain the instruction list obtained by running the target program in the set environment, the number of threads to be started, and the execution result of each thread on each instruction in the instruction list; wherein, the execution The result includes the instruction execution control value for each instruction;

The simulation scheduler is configured to start a thread simulator in the GPU performance model to be analyzed according to the number of threads to be started;

Each of the thread simulators is configured to traverse each instruction in the instruction list, and execute the currently traversed instruction according to the instruction execution control value and the instruction type of each instruction during the traversal process, so as to measure the execution of the instruction. Describe the duration of the currently traversed instruction;

The statistics part is configured to acquire the total execution time for all thread simulators to execute all the instructions in the instruction list when all instructions in the instruction list have been traversed.

In a third aspect, an embodiment of the present invention provides a computer storage medium, where the computer storage medium stores a program for analyzing GPU performance, and when the program for analyzing GPU performance is executed by at least one processor, the analysis described in the first aspect is implemented Method steps for GPU performance.

The embodiments of the present invention provide a method, a device and a computer storage medium for analyzing GPU performance; during the performance analysis process, the execution time of each type of instruction in the instruction list of the target program executed by each simulated thread in the GPU performance model is measured. , and count the total execution time, so that it can cover and simulate the processing of all current GPU instruction types, reduce the error rate of GPU performance statistics based on analysis and modeling methods, and provide more accurate performance data about GPUs.

Description of drawings

FIG. 1 is a schematic diagram of multithreading executing sequential instructions in a SIMT mode according to an embodiment of the present invention.

FIG. 2 is a schematic flowchart of a method for analyzing GPU performance according to an embodiment of the present invention.

FIG. 3 is a schematic flowchart of obtaining an instruction list and an execution result of a target program according to an embodiment of the present invention.

FIG. 4 is a specific implementation process for each thread simulator according to an embodiment of the present invention to measure the duration of executing the traversed instruction in the process of traversing the instruction list and obtain the total execution duration of all thread simulators executing all the instructions in the instruction list. Schematic.

FIG. 5 is a schematic structural diagram of an apparatus for analyzing GPU performance according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

At present, the instructions that the GPU can process can generally be divided into three types, namely arithmetic logic instructions, memory access instructions, and branch and jump instructions. At present, the conventional method of analyzing and modeling GPU performance statistics involves arithmetic logic instructions and memory access instructions, and can accurately calculate and obtain the execution time of each arithmetic logic instruction and memory access instructions. As for the branch and jump instructions, on the one hand, the existing conventional solutions do not consider the processing of the branch and jump instructions, and on the other hand, the branch and jump instructions have a great impact on the execution performance of the instructions. Therefore, the embodiments of the present invention are expected to provide a solution for analyzing GPU performance, which can accurately know the execution status of each thread on branch and jump instructions, so as to more accurately analyze and obtain the performance of GPU running instructions compared with conventional solutions.

It should be noted that the GPU uses Single Instruction Multiple Threads (SIMT, Single Instruction Multiple Threads) to run instructions, that is, each instruction fetches an instruction and then schedules multiple threads to execute at the same time. Based on the SIMT method, if a branch jump instruction is encountered during the execution process, it will enter different branch processing processes according to the data processed by each thread. Generally speaking, when the GPU executes the branch jump instruction, it will still Continue to fetch instructions sequentially, and each thread will control whether its current instruction needs to be executed by setting the mask bit. If the current mask bit of the thread is true, the current instruction will be executed; if the mask bit is false, the current instruction will not be executed. Pipeline execution, thereby controlling the processing and execution of SIMT branch and jump instructions. Taking FIG. 1 as an example, it is assumed that the GPU includes n+1 threads, which are respectively identified as Thread0, Thread1, Thread2, ..., Threadn. The instruction sequence is shown on the left side of Figure 1, which are: ADD, SUB, IF A, ADD, SUB, ELSE, MUL, DIV, ENDIF, ADD, and SUB. It can be seen from this that the branch jump instructions are IF A and ELSE, then when the GPU executes the above instructions through SIMT, when a branch jump instruction occurs, it will schedule different threads to execute different instruction segments. Thread1 in Figure 1 In the process of executing the instruction segment of the branch jump instruction IF A with Thread2, its mask position is false, therefore, the instruction segment of the branch jump instruction IF A does not enter the execution of threads Thread1 and Thread2, as shown in the dashed box in Figure 1; In addition, in Figure 1, when threads Thread0 and Threadn execute the instruction segment of the branch jump instruction ELSE, their mask bit is false. Therefore, the instruction segment of the branch jump instruction ELSE does not enter the execution of threads Thread0 and Threadn. The same is true in Figure 1. Shown as a dashed box.

Combined with the above description about sequential instruction fetch execution in the process of GPU executing instructions in SIMT mode and whether to use the mask bit to control whether the thread executes the current branch jump instruction, see FIG. 2 , which shows an analysis GPU performance provided by an embodiment of the present invention. method, which can include:

S201: Obtain the instruction list obtained by running the target program in the setting environment, the number of threads to be started, and the execution result of each thread on each instruction in the instruction list; wherein, the execution result includes the execution result of each instruction The instruction execution control value of ;

S202: Start the thread simulator in the GPU performance model to be analyzed according to the number of threads to be started by the simulation scheduler in the GPU performance model to be analyzed;

S203: Each thread simulator traverses each instruction in the instruction list, and executes the currently traversed instruction according to the instruction execution control value and the instruction type of each instruction during the traversal process to measure the execution of the currently traversed instruction the duration of the instruction;

S204: When all the instructions in the instruction list have been traversed, obtain the total execution time of all the thread simulators executing all the instructions in the instruction list.

Through the technical solution shown in FIG. 2 , the target program is run in advance in the setting environment to obtain the instruction list and the execution result of each thread on each instruction in the instruction list; then in the process of performance analysis, the GPU performance model is measured Each simulated thread in the target program executes the execution time of various types of instructions in the instruction list of the target program, and counts the total execution time; thus, it can cover the processing of all current GPU instruction types and reduce the time required for GPU performance statistics based on analytical modeling methods. Error rate, which provides more accurate data about GPU performance. Moreover, the structure of the GPU to be analyzed can be easily adjusted, so as to realize the analysis process of the performance indicators of the same instruction under different GPU architectures.

Based on the technical solution shown in FIG. 2 , in some possible implementations, the obtained target program runs in a set environment to obtain an instruction list, the number of threads to be started, and each thread’s response to each item in the instruction list. The execution result of each instruction, including:

Run the target program in a real environment or a simulation environment, and obtain the instruction list of the target program, the number of threads to be started, and the execution result of each thread executing each instruction during the running process; wherein, the execution result Includes operand register values and instruction execution control values.

For the above implementation manner, in detail, the target program can exemplarily select an application program for performing GPU performance analysis, as shown in FIG. 3, the application program can be in an existing real running environment or a simulation running environment Run, detect and obtain the instruction code, and obtain the instruction list of the application program according to the detected instruction code; in addition, in the process of running the application program through the SIMT mode, it can also be traced to the real operating environment or the simulated operating environment for execution. The number of threads enabled by the instruction list and the execution result of each instruction in the instruction list executed by each thread. Specifically, in the embodiment of the present invention, it is set that the instruction list includes m instructions, and the number of enabled threads is n, Then the number of execution results is m×n in total. Each execution result is preferably represented in the form of a list in this embodiment of the present invention, that is, [dest, src0, src1, mask]; wherein, dest, src0, and src1 all represent operand register values, and specifically, dest represents execution as an instruction The destination operand register value of the result, src0 represents the first source operand register value, src1 represents the second source operand register value, and mask represents the instruction execution control value. Combined with the foregoing, the mask value is used to control whether the thread needs to execute For the current instruction, for example, if the current mask value of the thread is true, the current instruction is executed; if the mask bit is false, the current instruction does not enter the execution pipeline for execution. In addition, for the execution result, depending on the type of instruction, dest, src0 and src1 do not necessarily need to be complete, but dest will definitely exist in each execution result, and the mask value will definitely exist in each execution result. execution result. For example, referring to Table 1, the number of enabled threads is set as n+1, which are respectively identified as T ₀ , T ₁ , T ₂ , . . . , T _n . instruction, each thread corresponds to an execution result, and the specific content is shown in Table 1.

Table 1

As can be seen from Table 1, IF R3 and ELSE R3 in the instruction list are branch and jump instructions, each of which has a corresponding instruction segment behind it. For IF R3, it can be seen from Table 1 that the mask values of threads T ₀ and T _n are true, indicating that the execution of IF R3 corresponds to the instructions "ADD R4, R1, R2" and "SUB R5, R4, R1" instruction segment, and the mask value _of threads T1 and T2 is false, indicating that neither the instruction segment corresponding to IF R3 _is executed _; further, when threads _T0 and Tn execute instructions "ADD R4, R1" , R2" and "SUB R5, R4, R1", threads _T1 and _T2 can be regarded as executing NOP instructions.

For ELSE R3, it can be seen from Table 1 that the mask values of threads T ₁ and T ₂ are true, indicating that the execution of ELSE R3 corresponds to the instructions "MUL R4, R1, R2" and "ADD R5, R4, R1""instruction segment, and the mask value _of threads T1 and T2 is false, indicating that neither _of them executes the instruction segment corresponding to ELSE R3 _; further, when threads T1 and _T2 execute instructions including "MUL R4, R1, During the instruction segment process of "R2" and "ADD R5, R4, R1", threads T ₀ and T _n can be regarded as executing NOP instructions.

Then refer to Table 1. For other types of instructions except branch and jump instructions, the mask value of each thread is true, which means that for other types of instructions, such as arithmetic logic instructions and memory access instructions, during the execution process, SIMT mode Multiple threads are scheduled to execute at the same time.

From the above description of the execution results shown in Table 1, it can be understood that since there is an instruction execution control value mask of each thread for each instruction in the execution result, and the mask value can be used to control whether the thread executes the instruction, so , the instruction list can be input into the performance analysis model of the GPU to be analyzed, and the execution of each thread model can be controlled according to the execution results shown in Table 1, so that the performance data of executing branch and jump instructions can be obtained more accurately, thereby reducing the Analyze the error rate of GPU performance statistics by modeling method, and provide more accurate performance data about GPU.

For the technical solution shown in FIG. 2, in some possible implementations, each thread simulator traverses each instruction in the instruction list, and executes the control value according to the instruction of each instruction during the traversal process And the instruction type executes the currently traversed instruction to measure the duration of executing the currently traversed instruction, including:

For each of the thread simulators, determine whether the instruction execution control value in the execution result of the currently traversed instruction indicates that the currently traversed instruction is executed;

Corresponding to the instruction execution control value indicating that the currently traversed instruction is not executed, the duration of executing the fixed NOP instruction is used as the duration of executing the currently traversed instruction;

Corresponding to the instruction execution control value indicating that the currently traversed instruction is executed, the instruction type of the currently traversed instruction is determined;

The instruction type corresponding to the currently traversed instruction is a memory access instruction, and the duration of executing the currently traversed instruction is measured according to the mode of executing the memory access instruction;

Corresponding to the instruction type of the currently traversed instruction is an arithmetic logic instruction, the fixed duration for executing the arithmetic logic instruction is used as the duration for executing the currently traversed instruction.

For the above implementation manner, in some examples, the measuring the execution time of the currently traversed instruction according to the manner of executing the memory access instruction includes:

According to the memory access address corresponding to the operand register value in the execution result of the currently traversed instruction, the duration of executing the currently traversed instruction is measured according to the set cache access analysis model.

For the above implementation manner and its examples, in the specific implementation process, combined with the foregoing content, the instruction execution control value mask can be true or false; if the current mask value of the thread is true, the current instruction is executed; if the current mask bit of the thread is If false, the current instruction does not enter the execution pipeline for execution, that is, the currently traversed instruction is not executed.

For the above implementations, in some examples, the method further includes:

For each thread simulator, during the traversal process, determine whether the currently traversed instruction is the end instruction in the instruction list:

If not, then determine whether the instruction execution control value in the execution result of the currently traversed instruction indicates that the currently traversed instruction is executed;

If so, it is determined that the thread simulator has completed traversing all the instructions in the instruction list.

For the above example, it should be noted that since each thread simulator needs to execute the instructions in the instruction list sequentially, when traversing each instruction in the instruction list, it should firstly determine whether the currently traversed instruction is an instruction list The end instruction in the instruction list, the end instruction represents the termination of the operation of the instructions in the instruction list; if it is an end instruction, it is determined that the thread simulator has traversed all the instructions in the instruction list, and then can execute S204 to obtain all thread simulators The process of executing the total execution time of all the instructions in the instruction list; if it is not an end instruction, it is necessary to execute the current execution according to the instruction execution control value and instruction type of each instruction as described in the above implementation manner and the foregoing example. traversed instructions to measure how long to execute the currently traversed instruction" process.

For the technical solution shown in FIG. 2, in some possible implementations, for each thread simulator, after measuring the duration of executing the currently traversed instruction, the method further includes:

For each thread simulator, the duration of executing the currently traversed instruction is added to the total execution duration of the corresponding thread simulator; wherein, before traversing the first instruction in the instruction list, the total execution duration The starting value is 0.

For the above implementation, it should be noted that, for each of the thread simulators, before traversing the instructions in the instruction list, the total execution duration with a starting value of 0 may be set; then, as the thread simulator traverses the instruction list In each instruction process, the duration of the traversed instruction is continuously added to the total execution duration; finally, when all the instructions in the instruction list are traversed and completed, the final total execution duration is the execution time of the thread simulator. The total execution time of all instructions in the instruction list.

4, the embodiment of the present invention uses a thread simulator as an example to illustrate the specific process of implementing S203 and S204. As shown in FIG. 4, the specific process may include:

S401: Set the initial value of the total execution time of the thread simulator to 0;

S402: The thread simulator traverses the instruction list;

S403: Determine whether the current traversed instruction is the end instruction in the instruction list: if so, go to S410, determine that the thread simulator has traversed all instructions in the instruction list, and execute S411: obtain the thread simulator execution instruction list. The total execution time of all instructions; if not, go to S404: determine whether the mask value of the execution result of the currently traversed instruction is true: if not, it means that the currently traversed instruction is a branch jump instruction or corresponding to a branch jump instruction and the thread simulator is controlled not to execute the instruction segment corresponding to the branch jump instruction and the branch jump instruction, therefore, go to S405: take the duration of executing the fixed NOP instruction as the duration of executing the currently traversed instruction ; if true, then regardless of whether the currently traversed instruction is a branch jump instruction or an instruction segment of a branch jump instruction, the thread simulator is controlled to execute the instruction, therefore, go to S406: determine the instruction of the currently traversed instruction type.

Corresponding to the instruction type being a memory access instruction, execute S407: measure the duration of executing the current traversed instruction according to the method of executing the memory access instruction; specifically, if the currently traversed instruction is a memory access instruction, according to the execution result of the thread The corresponding memory access address is used to calculate the execution time of the thread simulator for the current memory access instruction through the Cache access analysis model.

Corresponding to the instruction type being an arithmetic logic instruction, since the execution duration of the arithmetic logic instruction is fixed, S408 is executed: the fixed duration of executing the arithmetic logic instruction is used as the execution duration of the currently traversed instruction.

After completing S405, S407 and S408 to obtain the execution duration of the current traversed instruction, the thread simulator will execute S409: adding the execution duration of the currently traversed instruction to the total execution duration of the corresponding thread simulator. And go to S402, so that the thread simulator traverses the next instruction in the instruction list until it traverses to the end instruction in the instruction list.

Through the specific flow example shown in FIG. 4, using the execution result of each thread obtained by S201 for each instruction, the execution process of the real simulated instruction can be eliminated in the performance analysis process, and finally the execution process of the thread simulator in the execution instruction list can be obtained. The total execution time of all instructions is calculated according to the thread execution time and the main frequency of the system to obtain the IPC. Therefore, the performance data of executing the branch and jump instructions can be obtained more accurately, the error rate of the GPU performance statistics result based on the analytical modeling method can be reduced, and more accurate performance data about the GPU can be provided.

Based on the same inventive concept as the foregoing technical solutions, see FIG. 5 , which shows an apparatus 50 for analyzing GPU performance provided by an embodiment of the present invention. The apparatus 50 includes: an acquisition part 501 , a simulation scheduler 502 , and a thread simulator 503 and statistics section 504; where,

The obtaining part 501 is configured to obtain the instruction list obtained by running the target program under the set environment, the number of threads to be started, and the execution result of each thread on each instruction in the instruction list; wherein, the The execution result includes the instruction execution control value for each instruction;

The simulation scheduler 502 is configured to start the thread simulator 503 in the GPU performance model to be analyzed according to the number of threads to be started;

Each of the thread simulators 503 is configured to traverse each instruction in the instruction list, and execute the currently traversed instruction according to the instruction execution control value and the instruction type of each instruction during the traversal process to measure the execution the duration of the currently traversed instruction;

The statistics section 504 is configured to obtain the total execution time of all the thread simulators 503 for executing all the instructions in the instruction list when all instructions in the instruction list have been traversed.

In some examples, the obtaining part 501 is configured to run the target program in a real environment or a simulation environment, and obtain the instruction list of the target program, the number of threads to be started, each thread during the running process An execution result of executing each instruction; wherein the execution result includes an operand register value and an instruction execution control value.

In some examples, each of the thread simulators 503 is configured to:

Determine whether the instruction execution control value in the execution result of the currently traversed instruction indicates that the currently traversed instruction is executed;

Corresponding to the instruction execution control value indicating that the currently traversed instruction is not executed, the duration of executing the fixed NOP instruction is used as the duration of executing the currently traversed instruction;

Corresponding to the instruction execution control value indicating that the currently traversed instruction is executed, the instruction type of the currently traversed instruction is determined;

The instruction type corresponding to the currently traversed instruction is a memory access instruction, and the duration of executing the currently traversed instruction is measured according to the mode of executing the memory access instruction;

Corresponding to the instruction type of the currently traversed instruction is an arithmetic logic instruction, the fixed duration for executing the arithmetic logic instruction is used as the duration for executing the currently traversed instruction.

In some examples, each of the thread simulators 503 is configured to:

According to the memory access address corresponding to the operand register value in the execution result of the currently traversed instruction, the duration of executing the currently traversed instruction is measured according to the set cache access analysis model.

In some examples, each of the thread simulators 503 is configured to:

During the traversal process, determine whether the current traversed instruction is the end instruction in the instruction list:

If not, then determine whether the instruction execution control value in the execution result of the currently traversed instruction indicates that the currently traversed instruction is executed;

If so, it is determined that the thread simulator 503 has finished traversing all the instructions in the instruction list.

In some examples, each of the thread simulators 503 is further configured to: after measuring the duration of executing the currently traversed instruction, add the duration of executing the currently traversed instruction to the corresponding thread simulator 503 in the total execution time; wherein, before traversing the first instruction in the instruction list, the initial value of the total execution time is 0.

It can be understood that, in this embodiment, a "part" may be a part of a circuit, a part of a processor, a part of a program or software, etc., of course, it may also be a unit, or a module or non-modularity.

In addition, each component in this embodiment may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware, or can be implemented in the form of software function modules.

If the integrated unit is implemented in the form of a software functional module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or The part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium and includes several instructions for making a computer device (which can be It is a personal computer, a server, or a network device, etc.) or a processor (processor) that executes all or part of the steps of the method described in this embodiment. The aforementioned storage medium includes: U disk, removable hard disk, Read Only Memory (ROM, Read Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes.

Therefore, this embodiment provides a computer storage medium, where the computer storage medium stores a program for analyzing GPU performance, and when the program for analyzing GPU performance is executed by at least one processor, the analysis of GPU performance in the foregoing technical solution is implemented. method steps.

It can be understood that the above-mentioned exemplary technical solution of the device 50 for analyzing GPU performance belongs to the same concept as the technical solution of the aforementioned method for analyzing GPU performance. Therefore, the above-mentioned technical solution for analyzing the device 50 for analyzing GPU performance does not describe the details in detail. , can refer to the description of the technical solution of the method for analyzing GPU performance. This embodiment of the present invention will not describe this in detail.

It should be noted that the technical solutions described in the embodiments of the present invention may be combined arbitrarily unless there is a conflict.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (8)

1. A method for analyzing GPU performance, the method comprising:

acquiring an instruction list obtained by the operation of a target program under a set environment, the number of threads to be started and an execution result of each thread on each instruction in the instruction list; wherein the execution result comprises an instruction execution control value for each instruction;

starting a thread simulator in the GPU performance model to be analyzed according to the number of threads to be started through a simulation scheduler in the GPU performance model to be analyzed;

each thread simulator traverses each instruction in the instruction list, and executes the currently traversed instruction according to the instruction execution control value and the instruction type of each instruction in the traversing process so as to measure the time length for executing the currently traversed instruction;

when all the instructions in the instruction list are traversed, acquiring the total execution duration of all the instructions in the instruction list executed by all the thread simulators;

wherein each thread simulator traverses each instruction in the instruction list, and executes a currently traversed instruction according to an instruction execution control value and an instruction type of each instruction in the traversal process to measure the time length for executing the currently traversed instruction, and the method comprises the following steps:

for each thread simulator, judging whether an instruction execution control value in the execution result of the current traversed instruction represents the execution of the current traversed instruction;

corresponding to the instruction execution control value, the current traversed instruction is not executed, and the time length for executing the fixed NOP instruction is used as the time length for executing the current traversed instruction;

determining an instruction type of the currently traversed instruction corresponding to the instruction execution control value indicating execution of the currently traversed instruction;

the instruction type corresponding to the current traversed instruction is a memory access instruction, and the time length for executing the current traversed instruction is measured according to the mode of executing the memory access instruction;

and taking the fixed time length for executing the arithmetic logic instruction as the time length for executing the current traversed instruction, wherein the instruction type corresponding to the current traversed instruction is an arithmetic logic instruction.

2. The method of claim 1, wherein the obtaining of the instruction list obtained by the target program running under the set environment, the number of threads to be started, and the execution result of each thread on each instruction in the instruction list comprises:

running the target program through a real environment or a simulation environment, and acquiring an instruction list of the target program, the number of threads needing to be started and an execution result of each instruction executed by each thread in the running process; wherein the execution result includes an operand register value and an instruction execution control value.

3. The method of claim 1, wherein said metering a duration of execution of said currently traversed instruction by way of executing a memory access instruction comprises:

and according to the access address corresponding to the operand register value in the execution result of the current traversed instruction, measuring the time length for executing the current traversed instruction according to a set Cache access analysis model.

4. The method of claim 1, further comprising:

for each thread simulator, judging whether the current traversed instruction is an end instruction in the instruction list in the traversing process:

if not, judging whether an instruction execution control value in the execution result of the current traversed instruction represents the execution of the current traversed instruction or not;

and if so, determining that the thread simulator finishes traversing all the instructions in the instruction list.

5. The method of claim 1, wherein for each of the thread simulators, after metering a duration of execution of the currently traversed instruction, the method further comprises:

for each thread simulator, adding the time length for executing the currently traversed instruction into the total execution time length of the corresponding thread simulator; before traversing the first instruction in the instruction list, the starting value of the total execution time is 0.

6. An apparatus for analyzing GPU performance, the apparatus comprising: the device comprises an acquisition part, a simulation scheduler, a thread simulator and a statistic part; wherein,

the acquisition part is configured to acquire an instruction list obtained by running a target program under a set environment, the number of threads to be started and an execution result of each thread on each instruction in the instruction list; wherein the execution result comprises an instruction execution control value for each instruction;

the simulation scheduler is configured to start a thread simulator in a GPU performance model to be analyzed according to the number of threads to be started;

each thread simulator is configured to traverse each instruction in the instruction list, and execute a currently traversed instruction according to an instruction execution control value and an instruction type of each instruction in the traversing process so as to measure the time length for executing the currently traversed instruction;

the counting part is configured to acquire the total execution duration of all the instructions in the instruction list executed by all the thread simulators when all the instructions in the instruction list are traversed;

wherein each of the thread simulators is configured to:

judging whether an instruction execution control value in an execution result of the current traversed instruction represents the execution of the current traversed instruction or not;

corresponding to the instruction execution control value, the current traversed instruction is not executed, and the time length for executing the fixed NOP instruction is used as the time length for executing the current traversed instruction;

determining an instruction type of the currently traversed instruction corresponding to the instruction execution control value indicating execution of the currently traversed instruction;

the instruction type corresponding to the current traversed instruction is a memory access instruction, and the time length for executing the current traversed instruction is measured according to the mode of executing the memory access instruction;

and taking the fixed time length for executing the arithmetic logic instruction as the time length for executing the current traversed instruction, wherein the instruction type corresponding to the current traversed instruction is the arithmetic logic instruction.

7. The apparatus according to claim 6, wherein the acquiring section is configured to execute the target program through a real environment or a simulation environment, and acquire an instruction list of the target program, the number of threads to be started, and an execution result of each thread executing each instruction during execution; wherein the execution result includes an operand register value and an instruction execution control value.

8. A computer storage medium storing a program for analyzing GPU performance, the program for analyzing GPU performance implementing the method steps of any of claims 1 to 5 when executed by at least one processor.

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