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CN1142476A - Semiconductor ceramics and manufacturing method thereof - Google Patents

Semiconductor ceramics and manufacturing method thereof Download PDF

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CN1142476A
CN1142476A CN96106935A CN96106935A CN1142476A CN 1142476 A CN1142476 A CN 1142476A CN 96106935 A CN96106935 A CN 96106935A CN 96106935 A CN96106935 A CN 96106935A CN 1142476 A CN1142476 A CN 1142476A
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resistance value
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semiconducting ceramic
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CN1065219C (en
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阿部吉晶
并阿康训
胜木隆与
鬼头范光
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Murata Manufacturing Co Ltd
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    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21VFUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V19/00Fastening of light sources or lamp holders
    • F21V19/0075Fastening of light sources or lamp holders of tubular light sources, e.g. ring-shaped fluorescent light sources
    • F21V19/008Fastening of light sources or lamp holders of tubular light sources, e.g. ring-shaped fluorescent light sources of straight tubular light sources, e.g. straight fluorescent tubes, soffit lamps
    • F21V19/0085Fastening of light sources or lamp holders of tubular light sources, e.g. ring-shaped fluorescent light sources of straight tubular light sources, e.g. straight fluorescent tubes, soffit lamps at least one conductive element acting as a support means, e.g. resilient contact blades, piston-like contact
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21VFUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
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Abstract

本发明提供一种即使施加以高电压也难以发生瓷器破坏、对冲击电流的破坏特性优良的半导体瓷器及其制造方法。该方法的步骤是:称量BaCO3、SrCO3、Pb3O4、CaCO3、TiO2、Er2O3、MnCO3和SiO2,使其形成(Ba0.0536Pb0.08Sr0.20Ca0.18Er0.04)TiO3+0.0004Mn+0.02SiO2的组成。经混合、脱水。干燥后,在1360℃假烧2小时,将所得的假烧粉末与黏合剂混合后,制成直径18mm、厚3.6mm的形成体,在1360℃烧成1小时,在表1所示的条件下冷却,从而获得半导体瓷器。

Figure 96106935

The present invention provides a semiconductor ceramic that is less likely to break even when a high voltage is applied and has excellent destructive properties against rush current, and a method for manufacturing the same. The steps of the method are: weighing BaCO 3 , SrCO 3 , Pb 3 O 4 , CaCO 3 , TiO 2 , Er 2 O 3 , MnCO 3 and SiO 2 to form (Ba 0.0536 Pb 0.08 Sr 0.20 Ca 0.18 Er 0.04 ) composition of TiO 3 +0.0004Mn+0.02SiO 2 . Mixed and dehydrated. After drying, it was calcined at 1360°C for 2 hours. After mixing the obtained calcined powder with a binder, it was made into a formed body with a diameter of 18mm and a thickness of 3.6mm, and fired at 1360°C for 1 hour. Cool down to obtain semiconductor porcelain.

Figure 96106935

Description

半导体瓷器及其制造方法Semiconductor porcelain and its manufacturing method

本发明涉及钛酸钡系列的半导体瓷器及其制造方法。The invention relates to barium titanate series semiconductor ceramics and a manufacturing method thereof.

具有正的电阻温度特性的钛酸钡系列的半导体瓷器(以下称作半导体瓷器),由于其具有在居里点以上的温度时其电阻值急剧增加的特性,所以现时被广泛地应用于电动机的起动、彩色电视显象管以及其他的用途。Barium titanate series semiconductor ceramics (hereinafter referred to as semiconductor ceramics) with positive resistance temperature characteristics are widely used in electric motors because of their sharp increase in resistance at temperatures above the Curie point. Starter, color TV picture tube and other uses.

可是,这种半导体瓷器,当对它施加电压而产生的冲击电流达到破坏其特性(以下称作冲击耐电压特性)以上的冲击电流值时,造成层状破坏。However, when the surge current generated by applying a voltage to the semiconductor ceramic reaches a value higher than that which destroys its characteristics (hereinafter referred to as the impulse withstand voltage characteristic), layer damage occurs.

引起这种现象的原因,一方面是由于半导体瓷器的外侧部分接触外气使热扩散加速,从而使该部分的温度低,电阻也随着变低;另一方面,半导体瓷器的内侧部分与外侧部分相比其热扩散较慢,从而使电阻增加,这样,使半导体瓷器的发热不均匀。The reason for this phenomenon, on the one hand, is that the outer part of the semiconductor ceramics contacts the outside air to accelerate the heat diffusion, so that the temperature of this part is low, and the resistance is also lower; on the other hand, the inner part of the semiconductor ceramics and the outer part Part of it is slower than its thermal diffusion, so that the resistance increases, so that the heating of the semiconductor ceramic is uneven.

作为不发生这样的瓷器破坏的半导体瓷器的制造方法,有如特开平4-154661号所记载那样,提出了在空气中烧成半导体瓷器后,进行还原处理,然后在大气中进行再氧化处理的方法。As a method of manufacturing semiconductor ceramics that does not cause such ceramic damage, as described in JP-A-4-154661, a method of firing semiconductor ceramics in air, followed by reduction treatment, and then reoxidation treatment in the atmosphere has been proposed. .

然而,在将半导体瓷器还原后再氧化的方法中,如再氧化处理不充分,则耐电压低,而在氧化处理加重时,在室温下其电阻率增大。However, in the method of reducing and then oxidizing semiconductor ceramics, if the reoxidation treatment is insufficient, the withstand voltage is low, and when the oxidation treatment is aggravated, its resistivity increases at room temperature.

本发明目的是提供一种冲击耐电压特性优良、难以发生瓷器破坏的半导体瓷器及其制造方法。The object of the present invention is to provide a semiconducting porcelain which is excellent in impulse withstand voltage characteristics and hardly breaks the porcelain, and a method for producing the same.

权利要求1所述的本发明,在具有正的电阻温度特性的钛酸钡系列的半导体瓷器中,半导体瓷器的表面部和中心部之间的电阻值高于半导体瓷器的表面部或中心部的电阻值。In the present invention according to claim 1, in barium titanate series semiconductor ceramics having positive resistance temperature characteristics, the resistance value between the surface part and the center part of the semiconductor ceramics is higher than that of the surface part or the center part of the semiconductor ceramics. resistance.

权利要求2所述的本发明的半导体瓷器,其表面部和中心部之间的电阻值比表面部或中心部的电阻值高15-68%。In the semiconductor porcelain of the present invention as claimed in claim 2, the resistance value between the surface part and the center part is 15-68% higher than the resistance value of the surface part or the center part.

权利要求3所述的本发明的钛酸钡系列半导体瓷器,含有氧化铅、氧化锶和氧化钙。The barium titanate series semiconductor porcelain of the present invention according to claim 3 contains lead oxide, strontium oxide and calcium oxide.

权利要求4所述的本发明的半导体瓷器的制造方法,在具有正的电阻温度特性的钛酸钡系列的半导体瓷器的烧成工序中,在达到最高烧成温度后的降温过程中,在1100~1200℃之间保持0.4~10小时。The manufacturing method of the semiconductor porcelain of the present invention described in claim 4, in the firing process of the barium titanate series semiconductor porcelain with positive resistance temperature characteristics, in the cooling process after reaching the highest firing temperature, at 1100 Keep at ~1200°C for 0.4 to 10 hours.

权利要求5所述的本发明的半导体瓷器的制造方法,在具有正的电阻温度特性的钛酸钡系列的半导体瓷器的烧成工序中,在达到最高烧成温度后的降温过程中,在1100~1200℃之间以少于1.0℃/min的降温速度徐徐冷却。The manufacturing method of the semiconductor porcelain of the present invention described in claim 5, in the firing process of the barium titanate series semiconductor porcelain with positive resistance temperature characteristics, in the cooling process after reaching the highest firing temperature, at 1100 Slowly cool at a cooling rate of less than 1.0°C/min between ~1200°C.

根据本发明半导体瓷器,通过改变它在厚度方向上的电阻值的分布,而可提高其冲击耐电压特性。According to the semiconductor porcelain of the present invention, its impulse withstand voltage characteristic can be improved by changing the distribution of its resistance value in the thickness direction.

根据本发明的半导体瓷器的制造方法,通过在降温过程慢慢冷却或保持温度,使半导体瓷器在厚度方向上具有不同的电阻值分布,从而可提高其冲击耐电压特性。According to the manufacturing method of the semiconductor ceramics of the present invention, by slowly cooling or maintaining the temperature during the cooling process, the semiconductor ceramics have different resistance value distributions in the thickness direction, thereby improving their impulse withstand voltage characteristics.

图1是根据本发明的半导体瓷器而获得的正温度系数热敏电阻从一方的主面至另一主面之间单位厚度的电阻值的变化模式图;Fig. 1 is the pattern diagram of the variation of the resistance value per unit thickness from one main surface to the other main surface of the positive temperature coefficient thermistor obtained according to the semiconductor porcelain of the present invention;

图2是表示本发明的半导体瓷器的电阻值比与冲击耐电压特性的关系图;Fig. 2 is the relationship figure that represents the resistance value ratio and the impulse withstand voltage characteristic of semiconductor ceramics of the present invention;

图3本发明的半导体瓷器的降温过程的温度与冲击耐电压特性的关系图。Fig. 3 is a graph showing the relationship between the temperature and the impulse withstand voltage characteristics of the semiconductor porcelain of the present invention during the cooling process.

下面对本发明的一实施例加以说明。An embodiment of the present invention will be described below.

首先,称量BaCO3、SrCO3、Pb3O4、CaCO3、TiO2、Er2O3、MnCO3及SiO2,使它们的组成成为:(Ba0.536Pb0.08Sr0.20Ca0.18Er0.004)TiO3+0.004Mn+0.02SiO2。将此组成及纯水和氧化锆珠放入聚乙烯制的壶中,经5小时粉碎混合后,脱水、干燥,在1150℃假烧2小时,以获得假烧粉。将该假烧粉与纯水及氧化锆珠一起放入聚乙烯制的壶中,粉碎5小时。然后,将它与醋酸乙烯树脂系列的粘合剂混合,造成粒状。First, weigh BaCO 3 , SrCO 3 , Pb 3 O 4 , CaCO 3 , TiO 2 , Er 2 O 3 , MnCO 3 and SiO 2 so that their composition becomes: (Ba 0.536 Pb 0.08 Sr 0.20 Ca 0.18 Er 0.004 ) TiO 3 +0.004Mn+0.02SiO 2 . The composition, pure water and zirconia beads were put into a polyethylene pot, pulverized and mixed for 5 hours, dehydrated, dried, and calcined at 1150° C. for 2 hours to obtain calcined powder. This calcined powder was put into a polyethylene pot together with pure water and zirconia beads, and pulverized for 5 hours. Then, it is mixed with a binder of the vinyl acetate resin series to create a granular form.

其次,用干式压力机制成直径18mm、厚度6.3mm的形成体,在1360℃烧成1小时,然后在表1所示的条件下冷却,以获得半导体瓷器。在所获得的半导体瓷器的两面上以非电解镀镍形成作为端子电极、具有电阻特性的镍层,在最外层涂上银膏,在600℃烘干30分钟,以获得正温度系数的热敏电阻。Next, a forming body with a diameter of 18 mm and a thickness of 6.3 mm was formed by a dry press, fired at 1360° C. for 1 hour, and then cooled under the conditions shown in Table 1 to obtain semiconductor ceramics. On both sides of the obtained semiconductor ceramics, electroless nickel plating is used to form a nickel layer with resistive properties as a terminal electrode, and silver paste is coated on the outermost layer, and it is dried at 600 ° C for 30 minutes to obtain a thermal conductivity with a positive temperature coefficient. Sensitive resistance.

表1所示的冷却条件是表示从最高烧成温度冷却至室温的条件,试料号1~26表示从最高烧成温度按降温速度的比例冷却,在保持温度将该温度保持所示的保持时间,然后从保持温度冷却至室温。The cooling conditions shown in Table 1 represent the conditions for cooling from the highest firing temperature to room temperature. Sample Nos. 1 to 26 represent cooling from the highest firing temperature in proportion to the cooling rate, and maintain the temperature at the holding temperature. time, then cooled from holding temperature to room temperature.

此外,试料号27~30表示从最高温度至1200℃按降温速度的比例冷却,而在1200~1100℃之间则按徐冷速度的比例冷却,然后从1100℃冷却至室温。In addition, sample numbers 27 to 30 represent cooling from the highest temperature to 1200°C in proportion to the cooling rate, and between 1200 and 1100°C, cooling in proportion to the slow cooling rate, and then cooling from 1100°C to room temperature.

再者,试料31、32表示从最高温度至室温按一定的降温速度冷却。表1 试料号 降温速度(℃/min)     徐冷条件 保持温度(℃) 保持时间(小时) 徐冷速度(℃/min)     1*     3     1300     1       -     2*     3     1280     1       -     3*     3     1260     1       -     4*     3     1240     1       -     5*     3     1220     1       -     6*     3     1200     0.2       -     7     3     1200     0.4       -     8     3     1200     1       -     9     3     1200     1O       -    10*     3     1200     15       -    11     3     1180     1       -    12     3     1170     1       -    13*     3     1160     0.2       -    14     3     1160     0.4       -    15     3     1160     1       -    16     3     1160     10       -    17*     3     1160     15       -    18     3     1140     1       -    19     3     1120     1       -    20*     3     1100     0.2       -    21     3     1100     0.4       -    22     3     1100     1       -    23     3     1100     10       -    24*     3     1100     15       -    25*     3     1050     1       -    26*     3     1000     1       -    27     3       -     -     0.1    28     3       -     -     0.5    29     3       -     -     1.O    30*     3       -     -     2.O    31*     1.6       -     -      -    32*     3       -     -      - In addition, samples 31 and 32 represent cooling at a constant cooling rate from the highest temperature to room temperature. Table 1 Sample No. Cooling rate (℃/min) Xu cold condition Keep temperature(℃) Hold time (hours) Slow cooling speed (℃/min) 1* 3 1300 1 - 2* 3 1280 1 - 3* 3 1260 1 - 4* 3 1240 1 - 5* 3 1220 1 - 6* 3 1200 0.2 - 7 3 1200 0.4 - 8 3 1200 1 - 9 3 1200 1O - 10* 3 1200 15 - 11 3 1180 1 - 12 3 1170 1 - 13* 3 1160 0.2 - 14 3 1160 0.4 - 15 3 1160 1 - 16 3 1160 10 - 17* 3 1160 15 - 18 3 1140 1 - 19 3 1120 1 - 20* 3 1100 0.2 - twenty one 3 1100 0.4 - twenty two 3 1100 1 - twenty three 3 1100 10 - twenty four* 3 1100 15 - 25* 3 1050 1 - 26* 3 1000 1 - 27 3 - - 0.1 28 3 - - 0.5 29 3 - - 1.O 30* 3 - - 2.O 31* 1.6 - - - 32* 3 - - -

对该正温度系数热敏电阻测定其电阻率、单位厚度的电阻值、冲击耐电压特性及电阻值比。这里,所述的冲击耐电压特性是用下述的等式求得的值;电阻值比是正温度系数热敏电阻的表面部与中心部之间的最大电阻值与正温度系数热敏电阻的中心部的最小电阻值的比值。The resistivity, the resistance value per unit thickness, the impulse withstand voltage characteristic, and the resistance value ratio of the positive temperature coefficient thermistor were measured. Here, the above-mentioned impulse withstand voltage characteristic is a value obtained by the following equation; the resistance value ratio is the maximum resistance value between the surface part and the center part of the positive temperature coefficient thermistor and the maximum resistance value of the positive temperature coefficient thermistor. The ratio of the minimum resistance value at the center.

冲击耐电压特性=(击穿电压)2/常温电阻值Impulse withstand voltage characteristics = (breakdown voltage) 2 / resistance value at room temperature

表2示出了上述的测定结果。其中带有★记号的表示不在本发明的范围内,而没有★记号的表示在本发明的范围内。表2    试料号     电阻率Ω·cm    冲击耐电压特性(kW)    电阻值比     1*     50.86     13.00     1.05     2*     49.13     12.00     1.02     3*     51.44     15.00     1.08     4*     47.97     16.00     1.08     5*     51.44     28.00     1.11     6*     29     20.00     -     7     35     40.00     -     8     53.75     42.00     1.15     9     70     44.00     -     10*     100     28.00     -     11     58.96     43.00     1.36     12     54.91     51.00     1.41     13*     20     18.00     -     14     25     46.00     -     15     31.79     48.00     1.53     16     48     48.00     -     17*     58     29.00     -     18     23.12     48.00     1.68     19     26.01     47.00     1.52     20*     18     21.00     -     21     20     39.00     -     22     28.90     48.00     1.45     23     40     46.00     -     24*     44     25.00     -     25*     31.79     23.00     1.06     26*     30.06     24.00     1.08     27     100     45.00     -     28     60     48.00     -     29     40     45.00     -     30*     35     30.00     -     31*     57.80     22.00     1.02     32*     28.90     21.00     1.05 Table 2 shows the above measurement results. Among them, the representation with ★ mark is not within the scope of the present invention, while the representation without ★ mark is within the scope of the present invention. Table 2 Sample No. ResistivityΩ·cm Impulse withstand voltage characteristics (kW) Resistance ratio 1* 50.86 13.00 1.05 2* 49.13 12.00 1.02 3* 51.44 15.00 1.08 4* 47.97 16.00 1.08 5* 51.44 28.00 1.11 6* 29 20.00 - 7 35 40.00 - 8 53.75 42.00 1.15 9 70 44.00 - 10* 100 28.00 - 11 58.96 43.00 1.36 12 54.91 51.00 1.41 13* 20 18.00 - 14 25 46.00 - 15 31.79 48.00 1.53 16 48 48.00 - 17* 58 29.00 - 18 23.12 48.00 1.68 19 26.01 47.00 1.52 20* 18 21.00 - twenty one 20 39.00 - twenty two 28.90 48.00 1.45 twenty three 40 46.00 - twenty four* 44 25.00 - 25* 31.79 23.00 1.06 26* 30.06 24.00 1.08 27 100 45.00 - 28 60 48.00 - 29 40 45.00 - 30* 35 30.00 - 31* 57.80 22.00 1.02 32* 28.90 21.00 1.05

图1模式地示出了本发明的正温度系数热敏电阻从一方的主面到另一方的主面之间单位厚度的电阻值的变化。从图1可以知道,该正温度系数热敏电阻的特性是中心部和两表面部的电阻值低,而中心部与两表面部之间的电阻值高。FIG. 1 schematically shows the change in the resistance value per unit thickness from one main surface to the other main surface of the positive temperature coefficient thermistor of the present invention. As can be seen from FIG. 1 , the characteristic of the positive temperature coefficient thermistor is that the resistance value between the center part and both surface parts is low, and the resistance value between the center part and both surface parts is high.

图2是表示电阻值比与冲击耐电压特性之间的关系图。图2中,示出了表面部与中心部之间的电阻值较中心部的电阻值高15~68%(电阻值比为1.15~1.68)的半导体瓷器具有优良的冲击耐电压特性的结果。Fig. 2 is a graph showing the relationship between the resistance value ratio and the impulse withstand voltage characteristic. In Fig. 2, it is shown that the resistance value between the surface part and the center part is higher than the resistance value of the center part by 15 to 68% (resistance value ratio is 1.15 to 1.68) and the result of excellent impulse withstand voltage characteristics of semiconductor ceramics.

图3示出了在降温过程中,保持温度与冲击耐电压特性的关系。从图3可以知道,在降温过程的保持温度为1100~1200°的范围,其冲击耐电压特性较好。还有,在该温度范围内,即使是徐冷,其冲击耐电压特性也是优良的。Figure 3 shows the relationship between the maintenance temperature and the impulse withstand voltage characteristics during the cooling process. It can be known from Figure 3 that the temperature maintained in the cooling process is in the range of 1100-1200°, and the impulse withstand voltage characteristics are better. Also, in this temperature range, even if it is slowly cooled, its impulse withstand voltage characteristic is excellent.

本发明的半导体瓷器通过使它单位厚度的电阻值的分布不同,而具有优良的耐电压特性,从而发挥即使在高电压下也不会被破坏的效果。The semiconductor porcelain of the present invention has excellent withstand voltage characteristics by making the distribution of the resistance value per unit thickness different, so that it will not be destroyed even under high voltage.

此外,由于半导体瓷器的表面部与中心部之间的电阻值较表面部或中心部的电阻值高15~68%,即使对于高电压也不会发生瓷器破坏,从而适用于电路的过电流保护。In addition, since the resistance value between the surface part and the center part of semiconductor ceramics is 15-68% higher than that of the surface part or the center part, the ceramics will not be damaged even for high voltage, so it is suitable for overcurrent protection of circuits .

还有,由于本发明的半导体瓷器是由含有氧化铅、氧化锶、氧化钙的钛酸钡系列的半导体瓷器构成,使半导体瓷器的表面部与中心部之间的电阻值较表面部或中心部的电阻值高15~68%,效果更加显著,对于高电压也不发生瓷器破坏,从而可被广泛地应用于电路的过电流保护及退磁等。Also, since the semiconductor ceramics of the present invention are made of barium titanate series semiconductor ceramics containing lead oxide, strontium oxide, and calcium oxide, the resistance value between the surface part and the central part of the semiconductor ceramics is higher than that of the surface part or the central part. The resistance value is 15-68% higher, the effect is more significant, and the porcelain will not be damaged for high voltage, so it can be widely used in over-current protection and demagnetization of circuits.

根据本发明的半导体瓷器的制造方法,通过在降温过程中的徐冷或保持温度,使半导体瓷器的单位厚度的电阻值分布不同,从而获得即使施加高电压也不容易发生瓷器破坏、冲击耐电压特性优良的半导体瓷器。According to the manufacturing method of the semiconductor ceramics of the present invention, the resistance value distribution per unit thickness of the semiconductor ceramics is made different by slow cooling or maintaining the temperature in the cooling process, so that even if a high voltage is applied, the ceramics are not easily broken, and the impact withstand voltage Semiconductor porcelain with excellent characteristics.

Claims (5)

1. the semiconducting ceramic with barium titanate series of positive resistance-temperature characteristic is characterized in that, the surface element of described semiconducting ceramic and the resistance value between the central part are higher than the resistance value of the surface element or the central part of described semiconducting ceramic.
2. semiconducting ceramic as claimed in claim 1 is characterized in that, the resistance value of the surface element of described semiconducting ceramic and more described surface element of the resistance value between the central part or described central part is high by 15~68%.
3. semiconducting ceramic as claimed in claim 1 or 2 is characterized in that, described semiconducting ceramic is the semiconducting ceramic that contains the barium titanate series of plumbous oxide, strontium oxide, calcium oxide.
4. the manufacture method of a semiconducting ceramic, it is characterized in that, in the firing process of the semiconducting ceramic of the barium titanate series that will have positive resistance-temperature characteristic, in the temperature-fall period after reaching maximum sintering temperature, between 1100~1200 ℃, kept 0.4~10 hour.
5. the manufacture method of a semiconducting ceramic, it is characterized in that, in the firing process of the semiconducting ceramic of the barium titanate series that will have positive resistance-temperature characteristic, in the temperature-fall period after reaching maximum sintering temperature, between 1100~1200 ℃, cooling rate is set at is less than 1.0 ℃/min, to carry out Xu Leng.
CN96106935A 1995-06-23 1996-06-22 Semiconductor ceramics and manufacturing method thereof Expired - Lifetime CN1065219C (en)

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JP15791995A JP3198876B2 (en) 1995-06-23 1995-06-23 Semiconductor porcelain, manufacturing method thereof, and positive temperature coefficient thermistor
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JP157919/1995 1995-06-23

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