CN114242889A - A memristor and method of making the same - Google Patents
A memristor and method of making the same Download PDFInfo
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- CN114242889A CN114242889A CN202111518851.1A CN202111518851A CN114242889A CN 114242889 A CN114242889 A CN 114242889A CN 202111518851 A CN202111518851 A CN 202111518851A CN 114242889 A CN114242889 A CN 114242889A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 230000008859 change Effects 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 32
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052718 tin Inorganic materials 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 230000002687 intercalation Effects 0.000 claims description 7
- 238000009830 intercalation Methods 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 229910004166 TaN Inorganic materials 0.000 claims description 4
- 229910003087 TiOx Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052593 corundum Inorganic materials 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 25
- 230000007547 defect Effects 0.000 abstract description 19
- 230000005684 electric field Effects 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 7
- 230000001808 coupling effect Effects 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 239000007789 gas Substances 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- -1 oxygen ions Chemical class 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 210000005036 nerve Anatomy 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
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Abstract
The invention provides a memristor and a manufacturing method thereof, and the memristor comprises the following steps: a substrate; the lower electrode is positioned on the substrate and is made of TiN, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive; the resistance change layer is positioned on one side of the lower electrode, which is far away from the substrate; and the upper electrode is positioned on one side of the resistance change layer, which is far away from the substrate. According to the technical scheme provided by the invention, the component ratio of Ti to N in the lower electrode of the memristor is adjusted to be 0.96-1.1, so that the resistivity and the thermal conductivity of the lower electrode are optimized, and the memristor forms a self-heating effect in the programming process. Furthermore, by adopting the thermoelectric coupling effect, the defect forming energy of the resistance change layer is reduced by the aid of a thermal field of the lower electrode, the defect forming probability is improved, the electric field intensity required in the programming process is reduced, the purpose of reducing the programming voltage is achieved, and therefore the reliability of the memristor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a memristor and a manufacturing method thereof.
Background
The resistive random access memory is a novel non-volatile memory technology, has a simple Metal-insulating layer-Metal sandwich structure, is completely compatible with a traditional CMOS (Complementary Metal-Oxide-Semiconductor) back-end process, and has lower working voltage and good reliability. Has important application prospect in embedded storage, logic circuit and nerve morphology calculation.
Under the excitation of an external electric field, the formation and the fracture process of a conductive filament can occur in a dielectric layer of the resistive random access memory, and the resistance value of the resistive random access memory is circularly switched between a high resistance state and a low resistance state. The process of first conductive filament formation in the resistive random access memory is called a forming process, and generally requires a higher voltage Vforming. Some devices may operate with Vforming of up to 3.5V or more alone and up to 4.5V in an array. This does not match the highest voltage that can be provided by the CMOS process nodes commonly used at the present stage, for example: the maximum working voltage of the MOS tube under the 28nm technology is 1.8V, and the working voltage of the MOS tube under the more advanced technology is lower. Therefore, in practical circuits, a plurality of voltages need to be provided to meet the requirements of different devices to work, thereby increasing the complexity of the circuit. In other words, the operating voltage of the resistive random access memory, especially the voltage Vforming, is too large, which may cause problems of compatibility and uniformity of the operating voltage, affect the practical application of the resistive random access memory, and is not beneficial to improving the reliability of the resistive random access memory.
Disclosure of Invention
In view of this, the invention provides a memristor and a manufacturing method thereof, which effectively solve the technical problems existing in the prior art, achieve the purpose of reducing programming voltage, and further improve the reliability of the memristor.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a memristor, comprising:
a substrate;
the lower electrode is positioned on the substrate and is made of TiN, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive;
the resistance change layer is positioned on one side of the lower electrode, which is far away from the substrate;
and the upper electrode is positioned on one side of the resistance change layer, which is far away from the substrate.
Optionally, the resistivity of the lower electrode is 250-350u Ω · cm, inclusive;
and the thermal conductivity of the lower electrode is 55-70W/m DEG C.
Optionally, the thickness of the lower electrode ranges from 20 nm to 500nm, inclusive;
and, the upper electrode has a thickness in the range of 20-500nm, inclusive.
Optionally, the upper electrode is made of Ir, Al, Ru, Pd, TiN or TaN.
Optionally, the material of the resistance change layer is a binary metal oxide.
Optionally, the binary metal oxide is HfOx、Ta2O5、Al2O3、WOx、TiOxOr CuO.
Optionally, the memristor further includes an intercalation layer between the resistive layer and the upper electrode, and the intercalation layer is a metal layer or a semiconductor layer.
Optionally, the memristor is a resistive random access memory.
Correspondingly, the invention also provides a preparation method of the memristor, which comprises the following steps:
providing a substrate;
forming a lower electrode made of TiN on the substrate, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive;
forming a resistance change layer on one side of the lower electrode, which is far away from the substrate;
and forming an upper electrode on the side of the resistance change layer, which is far away from the substrate.
Optionally, forming a lower electrode made of TiN on the substrate includes:
and when the lower electrode is formed on the substrate, introducing N gas and Ar gas, wherein the flow range of the N gas and the Ar gas is 8 sccm: 50scccm-8 sccm: 35scccm, inclusive.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a memristor and a manufacturing method thereof, and the memristor comprises the following steps: a substrate; the lower electrode is positioned on the substrate and is made of TiN, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive; the resistance change layer is positioned on one side of the lower electrode, which is far away from the substrate; and the upper electrode is positioned on one side of the resistance change layer, which is far away from the substrate.
According to the technical scheme provided by the invention, the component ratio of Ti to N in the lower electrode of the memristor is adjusted to be 0.96-1.1, so that the resistivity and the thermal conductivity of the lower electrode are optimized, and the memristor forms a self-heating effect in the programming process. Furthermore, by adopting the thermoelectric coupling effect, the defect forming energy of the resistance change layer is reduced by the aid of a thermal field of the lower electrode, the defect forming probability is improved, the electric field intensity required in the programming process is reduced, the purpose of reducing the programming voltage is achieved, and therefore the reliability of the memristor is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a memristor according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of another memristor according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of a method for fabricating a memristor according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of yet another method of fabricating a memristor provided by an embodiment of the present disclosure;
fig. 5 a-5 d are corresponding schematic structural diagrams of steps in fig. 3.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, under the excitation of an applied electric field, the formation and breaking process of a conductive filament occurs in the dielectric layer of the resistive random access memory, and the resistance value is cyclically switched between a high resistance state and a low resistance state. The process of first conductive filament formation in the resistive random access memory is called a forming process, and generally requires a higher voltage Vforming. Some devices may operate with Vforming of up to 3.5V or more alone and up to 4.5V in an array. This does not match the highest voltage that can be provided by the CMOS process nodes commonly used at the present stage, for example: the maximum working voltage of the MOS tube under the 28nm technology is 1.8V, and the working voltage of the MOS tube under the more advanced technology is lower. Therefore, in practical circuits, a plurality of voltages need to be provided to meet the requirements of different devices to work, thereby increasing the complexity of the circuit. In other words, the operating voltage of the resistive random access memory, especially the voltage Vforming, is too large, which may cause problems of compatibility and uniformity of the operating voltage, affect the practical application of the resistive random access memory, and is not beneficial to improving the reliability of the resistive random access memory.
Based on the above, the embodiment of the invention provides a memristor and a manufacturing method thereof, which effectively solve the technical problems in the prior art, achieve the purpose of reducing programming voltage, and further improve the reliability of the memristor.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 5 d.
Referring to fig. 1, a schematic structural diagram of a memristor provided in an embodiment of the present invention is shown, where the memristor provided in the embodiment of the present invention includes:
a substrate 100.
A lower electrode 200 of TiN on the substrate 100, wherein a ratio of the N component to the Ti component of the lower electrode 200 is 0.96-1.1, inclusive.
And the resistance change layer 300 is positioned on the side of the lower electrode 200, which faces away from the substrate 100.
And an upper electrode 400 positioned on a side of the resistance change layer 300 facing away from the substrate 100.
It can be appreciated that for a memristor, a formining process is typically required to trigger the resistance switching behavior of the subsequent cycle. This forming process can be understood as a soft breakdown process under the effect of electric field and heat, mainly related to the generation of oxygen ions and oxygen vacancies. Oxygen vacancies are understood to be defects in the material, and the probability of defect generation in the resistive layer is related to the electric field voltage and temperature. When the electric field voltage is the same, the probability of defect formation is increased along with the increase of the temperature; when the temperature is the same, the probability of defect formation increases as the electric field voltage increases.
By combining the principle, according to the technical scheme provided by the embodiment of the invention, the resistivity and the thermal conductivity of the lower electrode are further optimized by adjusting the component ratio of Ti to N in the lower electrode of the memristor to be 0.96-1.1, so that the memristor forms a self-heating effect in the programming process. Furthermore, by adopting the thermoelectric coupling effect, the defect forming energy of the resistance change layer is reduced by the aid of a thermal field of the lower electrode, the defect forming probability is improved, the electric field intensity required in the programming process is reduced, the purpose of reducing the programming voltage is achieved, and therefore the reliability of the memristor is improved.
In an embodiment of the invention, the resistivity of the bottom electrode provided in the embodiment of the invention may be 250-350u Ω · cm, inclusive.
And, the thermal conductivity of the lower electrode may be 55-70W/m.
Optionally, the thickness of the lower electrode provided by the embodiment of the present invention ranges from 20 nm to 500nm, inclusive.
And, the upper electrode has a thickness in the range of 20-500nm, inclusive.
In an embodiment of the invention, the material of the upper electrode provided by the invention is Ir, Al, Ru, Pd, TiN, TaN, or the like.
In an embodiment of the present invention, the material of the resistive layer provided in the embodiment of the present invention is binary metal oxide. The binary metal oxide provided by the embodiment of the invention can be HfOx、Ta2O5、Al2O3、WOx、TiOxOr CuO; or, the resistance change layer provided by the embodiment of the invention can be some organic resistance change materials.
Referring to fig. 2, a schematic structural diagram of another memristor is provided in an embodiment of the present invention, where the memristor further includes an insertion layer 500 located between the resistive layer 300 and the upper electrode 400, and the insertion layer 500 is a metal layer or a semiconductor layer.
It can be appreciated that the intercalation provided by the embodiment of the invention is used for providing a higher initial oxygen vacancy defect concentration, and is beneficial to reducing the operating voltage of the memristor. The intercalation layer provided by the embodiment of the invention has conductivity, and can be a metal layer or a semiconductor layer. Specifically, the intercalation layer may be Ta, Ti, or the like, or amorphous silicon, amorphous C, graphene, or the like.
In an embodiment of the present invention, the memristor provided by the present invention may be a resistance change memory, and the present invention is not limited to this, and may also be other types of devices.
Correspondingly, the embodiment of the invention also provides a preparation method of the memristor. As shown in fig. 3, a flowchart of a method for manufacturing a memristor according to an embodiment of the present invention is shown, where the method includes:
and S1, providing a substrate.
S2, forming a lower electrode made of TiN on the substrate, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive.
And S3, forming a resistance change layer on the side of the lower electrode, which faces away from the substrate.
And S4, forming an upper electrode on the side of the resistance change layer, which is far away from the substrate.
It can be appreciated that for a memristor, a formining process is typically required to trigger the resistance switching behavior of the subsequent cycle. This forming process can be understood as a soft breakdown process under the effect of electric field and heat, mainly related to the generation of oxygen ions and oxygen vacancies. Oxygen vacancies are understood to be defects in the material, and the probability of defect generation in the resistive layer is related to the electric field voltage and temperature. When the electric field voltage is the same, the probability of defect formation is increased along with the increase of the temperature; when the temperature is the same, the probability of defect formation increases as the electric field voltage increases.
By combining the principle, according to the technical scheme provided by the embodiment of the invention, the resistivity and the thermal conductivity of the lower electrode are further optimized by adjusting the component ratio of Ti to N in the lower electrode of the memristor to be 0.96-1.1, so that the memristor forms a self-heating effect in the programming process. Furthermore, by adopting the thermoelectric coupling effect, the defect forming energy of the resistance change layer is reduced by the aid of a thermal field of the lower electrode, the defect forming probability is improved, the electric field intensity required in the programming process is reduced, the purpose of reducing the programming voltage is achieved, and therefore the reliability of the memristor is improved.
In order to adjust the components of Ti and N in the lower electrode and further realize proper resistivity and thermal conductivity, the lower electrode made of TiN is formed on the substrate, and the method comprises the following steps:
and when the lower electrode is formed on the substrate, introducing N gas and Ar gas, wherein the flow range of the N gas and the Ar gas is 8 sccm: 50scccm-8 sccm: 35scccm, inclusive. The plasma is generated by glow discharge under low pressure through filling a certain amount of inert gas Ar, so that the film deposition rate is improved, and the aim of adjusting the concentration of N gas can be fulfilled.
Specifically, as shown in fig. 4, a flowchart of a preparation method of another memristor provided by the embodiment of the present invention is provided, where the preparation method includes:
and S1, providing a substrate.
S2, forming a lower electrode made of TiN on the substrate, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive. And when the lower electrode is formed on the substrate, introducing N gas and Ar gas, wherein the flow range of the N gas and the Ar gas is 8 sccm: 50scccm-8 sccm: 35scccm, inclusive.
And S3, forming a resistance change layer on the side of the lower electrode, which faces away from the substrate.
And S4, forming an upper electrode on the side of the resistance change layer, which is far away from the substrate.
The preparation method provided by the embodiment of the invention is described in more detail below with reference to fig. 5a to 5 d. Fig. 5 a-5 d are corresponding schematic structural diagrams of steps in fig. 3.
As shown in fig. 5a, corresponding to step S1, a substrate 100 is provided.
As shown in fig. 5b, corresponding to step S2, a lower electrode 200 made of TiN is formed on the substrate 100, wherein the ratio of the N component to the Ti component of the lower electrode 200 is 0.96-1.1, inclusive.
In an embodiment of the present invention, the lower electrode provided by the present invention can be prepared by sputtering, atomic layer deposition, physical vapor deposition, or chemical vapor deposition.
In an embodiment of the invention, the resistivity of the bottom electrode provided in the embodiment of the invention may be 250-350u Ω · cm, inclusive. And, the thermal conductivity of the lower electrode may be 55-70W/m. The thickness range of the lower electrode provided by the embodiment of the invention is 20-500nm, inclusive.
In order to adjust the components of Ti and N in the lower electrode and further realize proper resistivity and thermal conductivity, the lower electrode made of TiN is formed on the substrate, and the method comprises the following steps:
and when the lower electrode is formed on the substrate, introducing N gas and Ar gas, wherein the flow range of the N gas and the Ar gas is 8 sccm: 50scccm-8 sccm: 35scccm, inclusive. The plasma is generated by glow discharge under low pressure through filling a certain amount of inert gas Ar, so that the film deposition rate is improved, and the aim of adjusting the concentration of N gas can be fulfilled.
As shown in fig. 5c, corresponding to step S3, a resistance change layer 300 is formed on the side of the lower electrode 200 facing away from the substrate 100.
In an embodiment of the present invention, the material of the resistive layer provided in the embodiment of the present invention is binary metal oxide. The binary metal oxide provided by the embodiment of the invention can be HfOx、Ta2O5、Al2O3、WOx、TiOxOr CuO; or, the resistance change layer provided by the embodiment of the invention can be some organic resistance change materials.
As shown in fig. 5d, corresponding to step S4, an upper electrode 400 is formed on the side of the resistive layer 300 away from the substrate 100.
In one embodiment of the present invention, the upper electrode provided by the present invention has a thickness ranging from 20 to 500nm, inclusive. The upper electrode provided by the invention is made of Ir, Al, Ru, Pd, TiN or TaN and the like.
The embodiment of the invention provides a memristor and a manufacturing method thereof, and the method comprises the following steps: a substrate; the lower electrode is positioned on the substrate and is made of TiN, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive; the resistance change layer is positioned on one side of the lower electrode, which is far away from the substrate; and the upper electrode is positioned on one side of the resistance change layer, which is far away from the substrate.
According to the technical scheme provided by the embodiment of the invention, the component ratio of Ti to N in the lower electrode of the memristor is adjusted to be 0.96-1.1, so that the resistivity and the thermal conductivity of the lower electrode are optimized, and the memristor forms a self-heating effect in the programming process. Furthermore, by adopting the thermoelectric coupling effect, the defect forming energy of the resistance change layer is reduced by the aid of a thermal field of the lower electrode, the defect forming probability is improved, the electric field intensity required in the programming process is reduced, the purpose of reducing the programming voltage is achieved, and therefore the reliability of the memristor is improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A memristor, comprising:
a substrate;
the lower electrode is positioned on the substrate and is made of TiN, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive;
the resistance change layer is positioned on one side of the lower electrode, which is far away from the substrate;
and the upper electrode is positioned on one side of the resistance change layer, which is far away from the substrate.
2. The memristor according to claim 1, wherein the resistivity of the lower electrode is 250-350u Ω -cm, inclusive;
and the thermal conductivity of the lower electrode is 55-70W/m DEG C.
3. The memristor according to claim 1, wherein the thickness of the lower electrode ranges from 20 to 500nm, inclusive;
and, the upper electrode has a thickness in the range of 20-500nm, inclusive.
4. The memristor according to claim 1, wherein the upper electrode is made of Ir, Al, Ru, Pd, TiN or TaN.
5. The memristor according to claim 1, wherein the material of the resistive layer is a binary metal oxide.
6. The memristor according to claim 5, wherein the binary metal oxide is HfOx、Ta2O5、Al2O3、WOx、TiOxOr CuO.
7. The memristor according to claim 1, further comprising an intercalation layer between the resistive layer and the upper electrode, the intercalation layer being a metal layer or a semiconductor layer.
8. The memristor according to claim 1, wherein the memristor is a resistive random access memory.
9. A preparation method of a memristor is characterized by comprising the following steps:
providing a substrate;
forming a lower electrode made of TiN on the substrate, wherein the ratio of the N component to the Ti component of the lower electrode is 0.96-1.1, inclusive;
forming a resistance change layer on one side of the lower electrode, which is far away from the substrate;
and forming an upper electrode on the side of the resistance change layer, which is far away from the substrate.
10. The method of claim 9, wherein forming a bottom electrode of TiN on the substrate comprises:
and when the lower electrode is formed on the substrate, introducing N gas and Ar gas, wherein the flow range of the N gas and the Ar gas is 8 sccm: 50scccm-8 sccm: 35scccm, inclusive.
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