CN114242656A - P-type MOSFET device and preparation method thereof - Google Patents
P-type MOSFET device and preparation method thereof Download PDFInfo
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Abstract
The invention provides a P-type MOSFET device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, defining a plurality of active areas and shallow trench isolation structures, and forming a pad oxide layer on the surfaces of the active areas; carrying out N-type deep trap ion implantation on the active region; removing the pad oxide layer; forming a sacrificial oxide layer; sequentially performing isolation element injection, krypton element injection and threshold voltage adjusting element injection on the active region to sequentially form an isolation element injection layer, a krypton element injection layer and a threshold voltage adjusting element injection layer; performing high-temperature annealing to repair the damage and activate the impurities; removing the sacrificial oxide layer; and forming a gate dielectric, a gate and source and drain electrodes. According to the invention, the damaged pad oxide layer is removed firstly, then the sacrificial oxide layer is regenerated, and then one-step amorphous krypton ion implantation is added before the threshold voltage adjusting element is implanted into the N-type trap area, so that the uniformity of the ion implantation of the threshold voltage adjusting element can be obviously improved, the local fluctuation of the threshold voltage can be reduced, and the product yield can be improved.
Description
Technical Field
The invention relates to the technical field of power devices, in particular to a P-type MOSFET (metal oxide semiconductor field effect transistor) device and a preparation method thereof.
Background
The ion implantation technology is a material surface modification technology which is developed and widely applied internationally in the last 30 years. The basic principle is that ion beams with certain energy are incident into a material, the ion beams and atoms or molecules in the material generate a series of interactions, and incident ions gradually lose energy and finally stay in the material to cause the surface components, structures and properties of the material to change, so that the surface properties of the material are optimized or certain new excellent properties are obtained. Due to its unique and outstanding advantages, ion implantation has become a process used in most semiconductor devices during fabrication.
However, since the ion implantation adopts high-energy implantation, after the Deep well implantation layer (DNW) of the power device process of the current 28nm and above process is subjected to the high-energy ion implantation, the compactness of the pad oxide layer is damaged, the uniformity of the subsequent N/P well region ion implantation is affected, and the threshold voltage fluctuation of the prepared device is caused, so that the performance of the device is reduced.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a P-type MOSFET device and a method for manufacturing the same, which are used to solve the problems in the prior art that after a deep well implantation layer of a power device process of 28nm or above is subjected to high-energy ion implantation, compactness of a pad oxide layer is damaged, which affects uniformity of subsequent N/P well region ion implantation, resulting in threshold voltage fluctuation and device performance degradation of the manufactured device.
In order to achieve the above and other related objects, the present invention provides a method for fabricating a P-type MOSFET device, comprising the steps of:
providing a semiconductor substrate, wherein a plurality of active regions and a plurality of shallow trench isolation structures for separating the active regions from each other are defined in the semiconductor substrate, and a pad oxide layer is formed on the surface of each active region;
carrying out N-type deep trap ion implantation on the active region under the protection of the pad oxide layer;
removing the pad oxide layer;
forming a sacrificial oxide layer on the surface of the active region;
under the protection of the sacrificial oxide layer, sequentially performing isolation element injection, krypton element injection and threshold voltage adjusting element injection on the active region to sequentially form an isolation element injection layer, a krypton element injection layer and a threshold voltage adjusting element injection layer, wherein the krypton element is used for forming an amorphous layer in the semiconductor substrate so as to improve the injection uniformity of subsequent threshold voltage adjusting elements;
performing high-temperature annealing to repair the damage and activate the impurities;
removing the sacrificial oxide layer;
and forming a gate dielectric, a gate and source and drain electrodes.
Optionally, the isolation element comprises phosphorus and the threshold voltage adjustment element comprises arsenic.
More optionally, the implantation energy of the phosphorus element is 50 KeV-400 KeV, and the implantation dose is 1 x 1012/cm-2～1*1015/cm-2。
Optionally, the implantation energy of krypton element is 5 KeV-50 KeV, and the implantation dose is 1 x 1013/cm-2～1*1016/cm-2。
Optionally, the method for forming the sacrificial oxide layer is a wet oxidation process, the temperature of the wet oxidation process is 900-1200 ℃, and the thickness of the formed sacrificial oxide layer is 20-80 angstroms.
Optionally, the method for removing the pad oxide layer and the sacrificial oxide layer includes wet etching and/or dry etching.
Optionally, the temperature of the high-temperature annealing process is 1050-1250 ℃.
Optionally, after removing the pad oxide layer, an upper surface of the shallow trench isolation structure is higher than an upper surface of the active region, and a height difference is greater than or equal to 60 angstroms.
Optionally, an interconnection structure connected to the source and drain electrodes is formed after the source and drain electrodes are formed.
The invention also provides a P-type MOSFET device which is prepared based on the method in any scheme.
As described above, the P-type MOSFET device of the present invention has the following advantageous effects: the P-type MOSF provided by the inventionThe method for preparing the ET device comprises removing damaged pad oxide layer, regenerating sacrificial oxide layer, and implanting threshold voltage (V) into N-type well regionT) By adding one step of amorphous krypton ion implantation before adjusting elements, V can be obviously improvedTThe uniformity of element ion implantation is adjusted, so that local fluctuation of threshold voltage can be reduced, and the product yield is improved.
Drawings
Fig. 1 shows a transmission electron microscope image of a P-type MOSFET device fabricated using the prior art at the amorphous silicon-crystalline silicon interface.
Fig. 2-12 are schematic cross-sectional views of exemplary cross-sectional structures presented in steps of fabricating a P-type MOSFET device according to the method for fabricating a P-type MOSFET device of the present invention.
Fig. 13 is a transmission electron microscope image of a P-type MOSFET device fabricated by the fabrication method of the present invention at the amorphous silicon-crystalline silicon interface.
Description of the element reference numerals
11 active region
12 shallow trench isolation structure
13 pad oxide layer
14 sacrificial oxide layer
15 isolation element implant layer
16 Krypton injection layer
17 threshold voltage adjusting element injection layer
18 threshold voltage adjusting layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.
After a Deep well injection layer (DNW) of the current 28nm process is subjected to high-energy ion injection, the compactness of a cushion oxidation layer is damaged, so that the amorphous silicon-crystalline silicon interface is in a rough and uneven state as shown in fig. 1 after the subsequent N/P well region ion injection is completed, and a large damage layer is arranged at the interface, so that the finally formed device has threshold voltage fluctuation, the performance of the device is reduced and the like. In contrast, the inventors of the present application have made long-term studies and have proposed an improvement.
Please refer to fig. 2 to 12.
As shown in fig. 2 to 12, the present invention provides a method for manufacturing a P-type MOSFET device, comprising the steps of:
providing a semiconductor substrate, wherein a plurality of active regions 11 and a plurality of shallow trench isolation structures 12 for separating the active regions 11 from each other are defined in the semiconductor substrate, a pad oxide layer 13 is formed on the surface of the active region 11, or the active region 11 is defined by the pad oxide layer 13 formed on the semiconductor substrate, and a P-type MOSFET device is formed in the active region 11; the semiconductor substrate is preferably a silicon wafer, but not limited thereto, the pad oxide layer 13 is preferably a silicon oxide layer and can be formed by a thermal oxidation process, the thickness of the pad oxide layer 13 is preferably 100 angstroms to 200 angstroms, and the pad oxide layer 13 can prevent damage to the semiconductor substrate in a subsequent ion implantation process, which is helpful for improving implantation quality; the shallow trench isolation structure 12 is, for example, a silicon oxide isolation trench, the upper surface of the shallow trench isolation structure 12 is usually higher than the upper surface of the active region 11, so that the shallow trench isolation structure 12 can be prevented from being damaged in the subsequent process to form a hole to cause electric leakage, the shallow trench isolation structure 12 and the active region 11 are alternately arranged at intervals to isolate the active regions 11 from each other, and the structure obtained in this step is shown in fig. 2;
performing N-type deep well ion implantation on the active region 11 under the protection of the pad oxide layer 13 to form an N-type active region 11, which can be referred to as fig. 3; the N-type ion can be selected from one or more of nitrogen, phosphorus and arsenic, and the doping is usually light, such as doping energy of 1-2 KeV, and ion implantation dosage of 1 × 1010-1*1012/cm-2In the ion implantation process, the pad oxide layer 13 is severely damaged due to the high-speed impact of the high-energy particles on the pad oxide layer 13, so that after the ion implantation in this step is completed, in this embodiment, the pad oxide layer 13 is removed, for example, by using dry etching (i.e., plasma etching) or wet etching or first performing dry etching and then performing wet cleaning to remove the pad oxide layer 13, and the obtained structure is as shown in the figure4 is shown in the specification; it should be noted that, when the shallow trench isolation structure 12 is a silicon oxide filled trench and the pad oxide layer 13 is a silicon oxide layer, a part of the shallow trench isolation structure 12 may be removed in the process of removing the pad oxide layer 13, for example, the step height of the shallow trench isolation structure 12 may be damaged by about 10nm, but this influence is not great, and the loss amount may be adjusted by controlling the over-etching (over-etch) time of the acid; preferably, after the pad oxide layer 13 is removed, the upper surface of the shallow trench isolation structure 12 is higher than the upper surface of the active region 11, and the height difference is greater than or equal to 60 angstroms;
then, forming a sacrificial oxide layer 14 on the surface of the active region 11, preferably, forming the sacrificial oxide layer 14 by using a wet oxidation process, which is not only favorable for increasing the formation rate, but also favorable for increasing the uniformity of ion implantation because the surface of the sacrificial oxide layer 14 formed by using the wet oxidation process has a plurality of holes, and the structure obtained after this step is as shown in fig. 5;
under the protection of the sacrificial oxide layer 14, sequentially performing isolation element implantation, krypton element implantation, and threshold voltage adjustment element implantation on the active region 11 to sequentially form an isolation element implantation layer 15, a krypton element implantation layer 16, and a threshold voltage adjustment element implantation layer 17, where the krypton element is used to form an amorphous layer in the semiconductor substrate to improve the implantation uniformity of the subsequent threshold voltage adjustment element, so that local fluctuation of the threshold voltage can be reduced, which is helpful for improving the performance of the finally manufactured device, and ions related to the implanted threshold voltage (Vt) are used to form a threshold voltage adjustment region in the channel region; specifically, as shown in fig. 6, for example, phosphorus implantation is performed first to form an isolation element implantation layer 15 in the active region 11, the resulting structure is shown in fig. 7, then, as shown in fig. 8, krypton element implantation is performed, a krypton element implantation layer 16 is formed above the isolation element implantation layer 15, the resulting structure is shown in fig. 9, then, as shown in fig. 10, arsenic ion implantation is performed, the arsenic ion implantation is usually heavily doped, and by adjusting implantation energy, the formed threshold voltage adjustment element layer can be located between the isolation element implantation layer 15 and the krypton element implantation layer 16, and the resulting structure is shown in fig. 11; of course, it should be noted that, since ions are all diffusive, there is no particularly strict boundary between the ion-implanted layers, but the dispersion concentration of each element in each implanted layer is different, and therefore, a high temperature annealing process is performed, where the temperature of the high temperature annealing process is preferably 1050 ℃ to 1250 ℃, so that the isolation element, the krypton element, and the threshold voltage adjusting element are uniformly mixed to form an element mixed layer, which can be defined as the threshold voltage adjusting layer 18 (device channel region); the reason why the above-mentioned several injection elements are uniformly mixed after high-temperature annealing is related to the random distribution of different impurity elements in a semiconductor substrate (silicon wafer), after the high-temperature annealing, the polycrystalline silicon damaged by the high-energy injection ions is repaired into monocrystalline silicon, and simultaneously impurity atoms in the silicon are activated, all the impurity atoms occupy the lattice points of the silicon, all the impurity atoms at the same depth are randomly arranged on the lattice points of the silicon and staggered with each other, so that the impurity atoms at the same depth are uniformly distributed in the silicon macroscopically; more specifically, after the krypton ions are implanted into the silicon substrate, the single crystal silicon is broken into amorphous silicon, and the amorphization effect is much better than that of atoms with small mass, after the amorphous silicon layer (silicon atoms are randomly discharged) is formed within a certain depth range, the subsequently implanted impurity ions are randomly and uniformly distributed under the shielding effect of the amorphous silicon (the incident impurity ions collide with the silicon with random distribution, and the advancing path shows disorder homogenization) (if the impurity is implanted into the single crystal silicon, most impurities will advance along the channels between the silicon lattices, become heavily doped with a certain dimension, and lightly doped with a certain dimension, and finally cause uneven distribution of the impurity), the ions implanted after the krypton elements are ions for adjusting the threshold voltage, and the ions are uniformly distributed in the channels of the device, so that the error of the threshold voltage of a plurality of transistors distributed on the active region 11 can be greatly reduced, thereby improving the performance of the device;
then, removing the sacrificial oxide layer 14 by using wet etching and/or dry etching, including but not limited to;
then, a gate dielectric, a gate electrode, and a source/drain electrode are formed, for example, a gate oxide layer, a gate conductive layer, and a gate dielectric layer are sequentially formed on the active region 11, and then a source/drain metal electrode is formed to finally form a P-type MOSFET device with a desired structure. Since the preparation process of this part is basically similar to that of the prior art and is not the focus of the present invention, it is not expanded in detail.
The preparation method of the P-type MOSFET device provided by the invention comprises the steps of removing the damaged pad oxide layer, regenerating the sacrificial oxide layer, and then injecting a threshold voltage (V) into the N-type trap regionT) By adding one step of amorphous krypton ion implantation before adjusting elements, V can be obviously improvedTThe uniformity of element ion implantation is adjusted, so that local fluctuation of threshold voltage can be reduced, and the product yield is improved.
Of course, the isolation element is not limited to phosphorus, and may be, for example, arsenic, or the threshold voltage adjustment element is not limited to arsenic.
In the foregoing ion implantation processes, the implantation parameters of each element have a great influence on the performance of the finally formed device. The inventors have found through extensive experiments that, preferably, the phosphorus element is implanted at an implantation energy of 50KeV to 400KeV (inclusive, unless otherwise specified, inclusive) and at an implantation dose of 1 × 10 during the implantation of the isolation element, where the ranges are described herein as being related to numerical ranges12/cm-2～1*1015/cm-2。
Krypton is an inert element, krypton ions are accelerated to be thrown into a silicon substrate through an electric field, a krypton source used in an injection process is usually bottled krypton, the krypton is conveyed to an ion generation chamber through a gas path, the electric field and a magnetic field are installed outside the chamber, the krypton is ionized by a high-voltage electric field when passing through two high-voltage electrodes to generate krypton ions, the krypton ions can be driven to the next chamber through regulating the electric field and the magnetic field, ideal krypton ions can be screened out through screening of a plurality of groups of electric fields and magnetic fields, finally, after passing through the high electric field of an ion gun, numerous high-energy krypton ions are accelerated to vertically bombard the surface of the semiconductor substrate and enter the semiconductor substrate,distributed within a certain preset depth range. In the injection process, the kinetic energy of krypton ions is adjusted to adjust the arrival depth of the krypton ions, and the larger the kinetic energy is, the deeper the hitting depth is. After a lot of experiments, the implantation energy of krypton is preferably 5KeV to 50KeV, and the implantation dose is preferably 1 × 1013/cm-2～1*1016/cm-2。
In a preferred example, in the case of forming the sacrificial oxide layer 14 by a wet oxidation process, the temperature of the wet oxidation process is preferably 900-1200 ℃, and the sacrificial oxide layer 14 is formed to have a thickness of 20-80 angstroms, more preferably 40-60 angstroms.
Fig. 13 is a transmission electron microscope image of a P-type MOSFET device fabricated by the method of the present invention at the amorphous silicon-crystalline silicon interface, and it can be seen that, by the method of the present invention, the device is flatter at the amorphous silicon-crystalline silicon interface than the interface after silicon implantation, and the interface damage layer is thinner, which illustrates that introduction of krypton element achieves a relatively excellent amorphization effect, which will contribute to the improvement of the device performance.
The invention also provides a P-type MOSFET device prepared based on the method of any of the above schemes, so the foregoing can be incorporated herein in its entirety. The P-type MOSFET device provided by the invention is prepared by adopting the method, so the most important difference between the P-type MOSFET device and the P-type MOSFET device in the prior art is that krypton element injection is carried out before threshold voltage adjusting element injection, and after high-temperature annealing treatment, various elements such as krypton element, threshold voltage adjusting element, isolation element and the like are uniformly mixed, so that amorphous silicon-crystalline silicon interface damage can be effectively repaired, the interface flatness is improved, local fluctuation of the threshold voltage of the device can be reduced, and the product yield is improved.
In summary, the invention provides a P-type MOSFET device and a method for fabricating the same. The preparation method comprises the following steps: providing a semiconductor substrate, wherein a plurality of active regions and a plurality of shallow trench isolation structures for separating the active regions from each other are defined in the semiconductor substrate, and a pad oxide layer is formed on the surface of each active region; under the protection of the pad oxide layerCarrying out N-type deep trap ion implantation on the active region; removing the pad oxide layer; forming a sacrificial oxide layer on the surface of the active region; under the protection of the sacrificial oxide layer, sequentially performing isolation element injection, krypton element injection and threshold voltage adjusting element injection on the active region to sequentially form an isolation element injection layer, a krypton element injection layer and a threshold voltage adjusting element injection layer, wherein the krypton element is used for forming an amorphous layer in the semiconductor substrate so as to improve the injection uniformity of subsequent threshold voltage adjusting elements; performing high-temperature annealing to repair the damage and activate the impurities; removing the sacrificial oxide layer; and forming a gate dielectric, a gate and source and drain electrodes. The preparation method of the P-type MOSFET device provided by the invention comprises the steps of removing the damaged pad oxide layer, regenerating the sacrificial oxide layer, and then injecting a threshold voltage (V) into the N-type trap regionT) By adding one step of amorphous krypton ion implantation before adjusting elements, V can be obviously improvedTThe uniformity of element ion implantation is adjusted, so that local fluctuation of threshold voltage can be reduced, and the product yield is improved. The invention is especially suitable for the preparation of MOSFET devices with the manufacturing process of 28nm and higher. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A preparation method of a P-type MOSFET device is characterized by comprising the following steps:
providing a semiconductor substrate, wherein a plurality of active regions and a plurality of shallow trench isolation structures for separating the active regions from each other are defined in the semiconductor substrate, and a pad oxide layer is formed on the surface of each active region;
carrying out N-type deep trap ion implantation on the active region under the protection of the pad oxide layer;
removing the pad oxide layer;
forming a sacrificial oxide layer on the surface of the active region;
under the protection of the sacrificial oxide layer, sequentially performing isolation element injection, krypton element injection and threshold voltage adjusting element injection on the active region to sequentially form an isolation element injection layer, a krypton element injection layer and a threshold voltage adjusting element injection layer, wherein the krypton element is used for forming an amorphous layer in the semiconductor substrate so as to improve the injection uniformity of subsequent threshold voltage adjusting elements;
performing high-temperature annealing to repair the damage and activate the impurities;
removing the sacrificial oxide layer;
and forming a gate dielectric, a gate and source and drain electrodes.
2. The method of claim 1, wherein the isolation element comprises phosphorus and the threshold voltage adjustment element comprises arsenic.
3. The method of claim 2, wherein the phosphorus element is implanted at an energy of 50 KeV-400 KeV and at an implant dose of 1 x 1012/cm-2～1*1015/cm-2。
4. The method of claim 1, wherein the krypton is implanted at an energy of 5 KeV-50 KeV and at an implant dose of 1 x 1013/cm-2～1*1016/cm-2。
5. The method of claim 1, wherein the sacrificial oxide layer is formed by a wet oxidation process at 900-1200 ℃, and the sacrificial oxide layer is formed to a thickness of 20-80 angstroms.
6. The method of claim 1, wherein the removing the pad oxide layer and the sacrificial oxide layer comprises wet etching and/or dry etching.
7. The method of claim 1, wherein the high temperature annealing process is performed at a temperature of 1050 ℃ to 1250 ℃.
8. The method of claim 1, wherein after the pad oxide layer is removed, the upper surface of the shallow trench isolation structure is higher than the upper surface of the active region, and the height difference is greater than or equal to 60 angstroms.
9. The method of claim 1, wherein an interconnect structure electrically connected to the source and drain electrodes is formed after the source and drain electrodes are formed.
10. A P-type MOSFET device, characterized in that it is produced on the basis of the method according to any of claims 1-9.
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