CN114242586A

CN114242586A - Preparation method of RC-IGBT cell and RC-IGBT chip

Info

Publication number: CN114242586A
Application number: CN202111543886.0A
Authority: CN
Inventors: 余开庆; 朱利恒; 穆纳福·拉希莫; 王辉; 肖强; 覃荣震; 蔡海; 罗海辉
Original assignee: Zhuzhou CRRC Times Semiconductor Co Ltd
Current assignee: Zhuzhou CRRC Times Semiconductor Co Ltd
Priority date: 2021-12-16
Filing date: 2021-12-16
Publication date: 2022-03-25

Abstract

The application provides a preparation method of an RC-IGBT cell and an RC-IGBT chip, the preparation method includes: processing a semiconductor substrate and forming a gate composed of an oxide layer and polysilicon thereon; A plurality of hole regions are etched in the middle of the IGBT; N+ emitter is implanted in the hole region through a lithography plate with a preset structure, and the region where the N+ emitter is implanted is the IGBT region, and the N+ emitter is not injected into the hole region. The region of the N+ emitter is the FRD region. The preparation method provided by the present application divides the strip-shaped gate into segments, etches a plurality of hole regions in the middle of the gate, and uses a photolithography plate with a preset structure to reasonably arrange the position of the N+ emitter in the hole region, The diode part that is not short-circuited by the channel is the first to enter the conductance modulation state, which can effectively reduce VF and optimize VF‑shift.

Description

Preparation method of RC-IGBT cell and RC-IGBT chip

Technical Field

The invention relates to the technical field of semiconductors, in particular to a preparation method of an RC-IGBT cellular and an RC-IGBT chip.

Background

In a Reverse Conducting Insulated Gate Bipolar Transistor (RC-IGBT) module, an anti-parallel Fast Recovery Diode (FRD) is integrated inside a chip, so that the power level of the module can be greatly improved. The RC-IGBT has the forward conduction and reverse conduction capabilities, when the RC-IGBT is conducted in the forward direction, the RC-IGBT works in an IGBT mode, and when the RC-IGBT is conducted in the reverse direction, the RC-IGBT works in an FRD mode.

Generally, when the IGBT module works, an optimized grid control mode is adopted to obtain the lowest power loss. I.e. the low and high voltage sides of the device are provided with opposite gate voltage signals, respectively, and a blanking time must be required to ensure that the two switches cannot be turned on simultaneously in order to avoid short-circuiting the device. For the RC-IGBT, when the RC-IGBT works in an FRD mode, a grounded or negative grid Voltage signal is needed for a grid electrode of a device to ensure low FRD on-state loss, and because the positive grid Voltage can cause MOS channel inversion and a P well (namely an FRD anode) to be short-circuited, the injection efficiency of an FRD anode hole is greatly reduced, and the conduction Voltage drop (VF) is greatly increased when the FRD is conducted in the Forward direction. That is, when the RC-IGBT works in the FRD mode, conduction voltage drops VF of the FRD under positive gate voltage and negative gate voltage are different, and VF under positive gate voltage is larger than VF under negative gate voltage, which may cause an increase in loss of the FRD under positive gate voltage, and this phenomenon of VF difference under positive gate voltage and negative gate voltage is called VF-shift.

In the related art, in order to solve the problem of large VF-shift, the control signal of the gate is optimized from the outside. When the diode is in unipolar conduction at the initial working stage, although VF is large, no reverse recovery process exists during turn-off, so that reverse recovery loss is extremely low; after the diode has a conductivity modulation effect, although VF is large, the reverse recovery loss increases. The optimization principle of the driving control signal is shown in fig. 1, when the diode in the module freewheeling stage works, a negative gate voltage is driven to the grid electrode, the channel is not conducted, and the diode directly enters a bipolar working mode; when the device is about to finish follow current, the grid voltage is changed into positive grid voltage in advance, so that a channel is opened, the injection efficiency of P-region holes is reduced, the holes in a drift region are reduced, and the reverse recovery loss of a diode is greatly reduced when the IGBT is opened. The method can solve the problem of overlarge VF-shift of the reverse conducting IGBT to a certain extent, but puts higher requirements on a driver. Accordingly, there is a need to ameliorate one or more of the problems with the related art solutions described above.

It is noted that this section is intended to provide a background or context to the inventive concepts recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

Disclosure of Invention

In order to solve the problems, the application provides a preparation method of an RC-IGBT unit cell and an RC-IGBT chip.

The application firstly provides a preparation method of RC-IGBT unit cells, which comprises the following steps:

processing the semiconductor substrate and forming a grid consisting of an oxide layer and polycrystalline silicon on the semiconductor substrate;

etching a plurality of hole regions in the middle of the grid;

and injecting an N + emitter into the hole region through a photoetching plate with a preset structure, wherein the region in which the N + emitter is injected is an IGBT region, and the region in which the N + emitter is not injected is an FRD region.

In some embodiments, each of the aperture regions includes a first engraved region and a second engraved region distributed around the first engraved region.

In some embodiments, the number of the hole regions is at least two.

In some embodiments, the reticle includes: the plate comprises a plate body and a plurality of hole bodies arranged on the plate body;

the hole bodies are sequentially arranged along the length direction of the grid electrode, and the positions of the hole bodies correspond to the positions of the IGBT areas one by one.

In some embodiments, when the N + emitter is implanted, a position of each hole of the reticle corresponds to one of the hole regions, an aperture of each hole is smaller than a length of the corresponding hole region, a distance between the holes corresponds to a tail of a previous hole region and a head of a next hole region, and positions from the head and the tail of the hole to an edge of the reticle correspond to the head or the tail of one hole region.

In some embodiments, when the N + emitter is implanted, a position of each hole of the reticle corresponds to one or more complete hole regions, a position of a space between the holes corresponds to one or more complete hole regions, and a position from the head and the tail of the hole to the edge of the reticle corresponds to one or more complete hole regions.

In some embodiments, when the N + emitter is implanted, a position of each hole of the reticle corresponds to a middle of one of the hole regions, and a distance between the holes includes a first distance and a second distance, where the first distance corresponds to a tail of a previous hole region and a head of a next hole region, the second distance corresponds to a complete hole region and a head and a tail of a hole region adjacent to the previous hole region, and positions from the head and the tail of the hole to an edge of the reticle correspond to the head or the tail of one hole region.

In some embodiments, the total length of the unit cells ranges from 10-1000 μm.

In some embodiments, the total length of the unit cells ranges from 1 to 100 μm.

The embodiment of the application also provides an RC-IGBT chip, and the RC-IGBT unit cells prepared by the method based on any one of the embodiments are arranged in an active area of the chip in an array form.

According to the preparation method of the RC-IGBT unit cell and the RC-IGBT chip, the plurality of hole areas are etched in the middle of the grid electrode, the N + emitter electrode is reasonably distributed in the hole areas by using the photoetching plate with the preset structure, the part, which is not short-circuited by the channel, of the diode enters a conductance modulation state first, VF can be effectively reduced, and VF-shift is optimized.

Drawings

The present application will be described in more detail below on the basis of embodiments and with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a prior art drive control signal optimization principle provided in the background of the present application;

fig. 2 is a schematic flow chart illustrating an implementation of a method for manufacturing an RC-IGBT cell according to an embodiment of the present application;

fig. 3 is a schematic plan view of a cellular cell with a separated stripe-shaped gate according to an embodiment of the present disclosure;

fig. 4 is a schematic position diagram of a reticle and a split stripe gate cell according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a position of another reticle and a split stripe gate cell according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram illustrating a position of another reticle and a split stripe-shaped gate cell according to an embodiment of the present disclosure;

fig. 7 is a schematic plan view of an RC-IGBT cell array according to an embodiment of the present application.

Reference numerals: 100. an active region; 200. a gate electrode; 300. a hole area; 400. a first engraved area; 500. a second engraved area; 600. photoetching a plate; 610. a porous body; 620. the spacing between the aperture bodies; 630. the portion of the aperture body that is away from the edge of the reticle.

In the drawings, like parts are designated with like reference numerals, and the drawings are not drawn to scale.

Detailed Description

Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments of the present disclosure can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.

The disclosed embodiment provides a preparation method of an RC-IGBT cellular unit, and referring to FIG. 2, the method includes steps S1-S3. Wherein:

step S1 of processing the semiconductor substrate and forming a gate electrode composed of an oxide layer and polysilicon thereon;

step S2, etching a plurality of hole regions in the middle of the grid;

step S3, performing N + emitter implantation in the hole region through a photolithography mask having a preset structure, wherein the region where the N + emitter is implanted is an IGBT region, and the region where the N + emitter is not implanted is an FRD region.

According to the preparation method of the RC-IGBT unit cell, the plurality of hole areas are etched in the middle of the grid electrode, and the positions of the N + emitting electrodes are reasonably distributed in the hole areas by using the photoetching plate with the preset structure, so that the part, which is not short-circuited by the channel, of the diode enters a conductance modulation state first, VF can be effectively reduced, and VF-shift is optimized.

Next, a method for manufacturing an RC-IGBT cell provided by the present application will be described in detail with reference to fig. 2 to 6.

For step S1, in one embodiment, an N-type single crystal silicon material or an N-type epitaxial silicon material may be employed as the material of the semiconductor substrate and serve as the drift region of the RC-IGBT cell. According to the existing manufacturing method, after the steps of etching the active region 100, depositing an oxide layer, injecting P-body, pushing junction and the like are carried out on the drift region, a layer of polysilicon is deposited on the surface of the generated structure, or polysilicon is deposited and doped to form N-type polysilicon. For example, in one embodiment, N-type polysilicon can be formed by depositing polysilicon on the surface of the semiconductor substrate 100 through a high temperature furnace and in-situ doping, the polysilicon having a thickness of 1-2 μm and a concentration of 1E20cm^-3(ii) a And then activating the polysilicon at high temperature of 950 ℃ for 30 minutes. Finally form an oxide layer and a polycrystalA gate 200 of silicon.

For step S2, in one embodiment, referring to fig. 3, at least two hole regions 300 may be formed on the gate 200 by photolithography and etching of the gate 200. Therefore, compared with the structure with only one hole region in the middle, the gap part between the hole regions 300 still has the grid, so that in the signal transmission process, signals can reach the grids at the upper side and the lower side of the hole regions 300 at the same time, and the effect of enhancing the signal consistency of the grid can be achieved.

Of course, the number of the hole regions 300 is not limited in the present disclosure, and in one embodiment, only 2 hole regions 300 may be formed on one gate 200. In another embodiment, 3, 4, 5 or more hole regions 300 may be formed on one gate 200, and these structures all have the effect of enhancing the uniformity of gate signals compared to the single hole region.

In one embodiment, as shown in fig. 3, each of the hole regions 300 includes a first etched region 400 and second etched regions 500 distributed around the first etched region 400. Specifically, the first etched region 400 is a hole etched to a bare silicon, and the second etched region 500 is a hole etched to a polysilicon layer. In the etching, the first and second

engraved regions

400 and 500 may be formed at one time using the same specific reticle.

For step S3, in one embodiment, a reticle 600 having a predetermined structure may be designed in advance, and the reticle 600 includes a plate body and a plurality of hole bodies 610 disposed on the plate body. Specifically, the aperture 610 of the reticle 600 may be circular, rectangular, or other shapes, and the shape of the aperture 610 is not limited by the present disclosure as long as the N + emitter implantation can be performed. In one embodiment, the holes 610 on the reticle 600 are sequentially arranged along the length direction of the gate 200, and the positions of the holes 610 correspond to the positions of the IGBT regions one to one.

Thus, during ion implantation, the N + emitter can be implanted into each of the hole regions 300 through the plurality of holes 610. Specifically, N + emitters can be formed at the positions of the hole regions 300 corresponding to the hole bodies 610 on the reticle 600, and N + emitters are not formed at the positions of the hole body gaps on the reticle 600 and the hole regions 300 corresponding to the periphery of the reticle 600. Therefore, the region without the N + emitter does not flow in the IGBT working mode, the effect of enhancing hole injection can be achieved in the FRD working mode, meanwhile, the influence of grid voltage is avoided, VF can be effectively reduced, and VF-shift is optimized.

In one embodiment, the implanted ions of the N + emitter are high-energy arsenic ions and the high-temperature drive-in is performed, for example, the implanted dose of the arsenic ions is 1E15-8E15cm^-2The implantation energy is 80-120 Kev.

In one embodiment, when the N + emitter is implanted, each hole 610 of the reticle 600 is located corresponding to one hole area 300, the aperture of each hole 610 is smaller than the length of the corresponding hole area 300, the distance 620 between the holes corresponds to the tail of the previous hole area 300 and the head of the next hole area 300, and the part 630 from the head to the tail of the hole to the edge of the reticle corresponds to the head or the tail of one hole area 300. In this design, there are no independent FRD and IGBT regions, both regions being spaced within the same ring.

For example, referring to fig. 4, the split stripe gate cell of fig. 4 has 4 hole regions 300. When the N + emitter is implanted, the reticle 600 having 4 rectangular hole bodies 610 is used, the 4 hole bodies 610 on the reticle 600 correspond to the middle positions of the 4 hole regions 300, and the length of each rectangular hole body 610 in the reticle 600 along the length direction of the gate 200 is smaller than the length of the corresponding hole region 300. The distances between the 4 rectangular holes 610 may be equal or unequal, as long as the distances are located at positions that just cover the tail of the previous hole area 300 and the head of the next hole area 300. While the right edge of the reticle in fig. 4 covers the right end of the rightmost hole region 300, the left edge of the reticle covers the left end of the leftmost hole region 300. Of course, in the case of the split stripe gate cell having other number of hole regions 300, the structure of the reticle is similar when implanting the N + emitter of the design, and the description thereof is omitted.

In one embodiment, when the N + emitter is implanted, each hole 610 of the reticle 600 is located corresponding to one or more complete hole regions 300, the space 620 between the holes is located corresponding to one or more complete hole regions 300, and the portion 630 from the head to the tail of the hole to the edge of the reticle also corresponds to one or more complete hole regions 300. In this design, there are independent FRD and IGBT regions, and both regions are continuously distributed.

For example, referring to fig. 5, the split stripe gate cell of fig. 5 has 4 hole regions 300. When the N + emitter is implanted, the photolithography mask 600 having 1 rectangular hole 610 is used, and 1 hole 610 on the photolithography mask 600 corresponds to 2 complete hole regions 300, the right edge of the photolithography mask covers the rightmost complete hole region 300, and the left edge of the photolithography mask covers the leftmost complete hole region 300. Of course, in other embodiments, the hole 610 on the reticle 600 may only correspond to 1 complete hole area 300, and the design method is similar and will not be described again.

In one embodiment, when the N + emitter is implanted, each hole 610 of the reticle 600 is located at a position corresponding to a middle portion of one of the hole regions 300, and the pitch 620 between the holes includes a first pitch and a second pitch, where the first pitch is located at a position corresponding to a tail portion of a previous hole region 300 and a head portion of a subsequent hole region 300, the second pitch is located at a position corresponding to a complete hole region 300 and a head portion and a tail portion of a hole region 300 adjacent to the hole region 300, and a portion 630 from the head to the tail of the hole to the edge of the reticle corresponds to the head portion or the tail portion of one hole region 300. In the design, an independent FRD region and an independent IGBT region are arranged, and the two regions are distributed at intervals.

For example, referring to fig. 6, the split stripe gate cell of fig. 6 has 4 hole regions 300. When the N + emitter is implanted, the photoetching plate 600 with 3 rectangular hole bodies 610 is used, and the 3 hole bodies 610 on the photoetching plate 600 respectively correspond to the middle positions of the 3 hole regions 300. In the structure of the reticle 600, the 3 rectangular hole bodies 610 are not equally spaced, wherein the spacing between the first rectangular hole and the second rectangular hole from left to right is larger, covering a complete hole area 300 and the tail and head of the hole area 300 adjacent to the front and back of the hole area 300, and the spacing between the second rectangular hole and the third rectangular hole from left to right is smaller, covering only the tail of the previous hole area 300 and the head of the next hole area 300. While the right edge of the reticle in FIG. 6 covers the right end of the rightmost hole region 300, the left edge of the reticle covers the left end of the leftmost hole region 300. Of course, when the isolated stripe-shaped gate unit cell with other number of isolated stripes is implanted with the N + emitter of the design, the structure of the photolithography mask is similar, and the description is omitted here.

In one embodiment, to further reduce VF, the total length of the cells may be designed to be in the range of 10-1000 μm.

In one embodiment, to further reduce VF, the total width of the cells may be designed to be in the range of 1-100 μm. The gate width between the void regions 300 should be small to allow adjacent P-channels under the polysilicon to come together and not pass current.

The application also provides an RC-IGBT chip, wherein the RC-IGBT cells in the RC-IGBT chip are prepared by the method according to any one of the embodiments, and, referring to fig. 7, a plurality of RC-IGBT cells are arranged in an array in the active region of the RC-IGBT chip. The technical effects brought by the related structure of the RC-IGBT chip are consistent with the effects described above when the RC-IGBT unit cell is prepared, and the details are not repeated here.

In summary, according to the preparation method of the RC-IGBT unit cell and the RC-IGBT chip provided by the application, the strip-shaped grid is segmented, and the position of the N + emitter is reasonably distributed in the unit cell by using the photoetching plate with the preset structure, so that the part of the diode which is not short-circuited by the channel enters a conductance modulation state first, VF can be effectively reduced, and VF-shift is optimized.

The above is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, which may be variously modified and varied by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. Although the embodiments disclosed in the present disclosure are described above, the embodiments are merely used for understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.

Claims

1. a preparation method of RC-IGBT cell, is characterized in that, the method comprises:

processing a semiconductor substrate and forming a gate composed of an oxide layer and polysilicon thereon;

A plurality of hole regions are etched in the middle of the gate;

The N+ emitter is implanted in the hole region through a photolithography plate with a predetermined structure, wherein the region where the N+ emitter is implanted is the IGBT region, and the region where the N+ emitter is not implanted is the FRD region.

2 . The preparation method according to claim 1 , wherein each of the hole regions comprises a first incised region and a second incised region distributed around the first incised region. 3 .

3 . The preparation method according to claim 2 , wherein the number of the hole regions is at least two. 4 .

4. The preparation method according to claim 1, wherein the lithography plate comprises: a plate body and a plurality of hole bodies arranged on the plate body;

Wherein, the holes are arranged in sequence along the length direction of the gate, and the positions of the holes correspond to the positions of the IGBT regions one-to-one.

5 . The preparation method according to claim 4 , wherein when the N+ emitter is implanted, the position of each hole body of the lithography plate is made to correspond to one of the hole regions respectively, 6 . And the aperture of each said hole body is smaller than the length of its corresponding said hole area, and the spacing position between each said hole body corresponds to the tail of the previous hole area and the head of the latter hole area. The position to the edge of the photoresist corresponds to the head or tail of a hole area, respectively.

6 . The preparation method according to claim 4 , wherein, when the N+ emitter is implanted, the position of each hole body of the lithography plate is respectively matched with one or more complete hole regions. 7 . Correspondingly, the spacing positions between the hole bodies are respectively corresponding to one or more complete hole areas, and the positions of the head and tail hole bodies to the edge of the lithography plate are also respectively corresponding to one or more complete hole areas. correspond.

7 . The preparation method according to claim 4 , wherein when the N+ emitter is implanted, the position of each hole body of the lithography plate is respectively in phase with the middle of one of the hole regions. 8 . Correspondingly, the distance between each of the hole bodies includes a first distance and a second distance, wherein the position of the first distance corresponds to the tail of the previous hole area and the head of the latter hole area, and the second distance The position of the hole corresponds to a complete hole area and the head and tail of the hole area adjacent to the hole area.

8 . The preparation method according to claim 1 , wherein the total length of the cells ranges from 10 to 1000 μm. 9 .

9 . The preparation method according to claim 1 , wherein the total width of the cells ranges from 1 to 100 μm. 10 .

10 . An RC-IGBT chip, characterized in that the RC-IGBT cells obtained by the method according to any one of claims 1 to 9 are arranged in the active area of the chip in an array form.