CN114238167B - Information prefetching method, processor and electronic equipment - Google Patents

Abstract

Provided are an information prefetching method, a processor and an electronic device. The method is used for a processor. The processor includes a first level cache space, a first page table walker, a second page table walker, and at least one predetermined cache space. The at least one preset cache space comprises a target preset cache space, the first page table walker and the target preset cache space are arranged at the same path level, and the first page table walker is in communication connection with the target preset cache space. The information prefetching method comprises the following steps: responding to a first page table walker selected from a first page table walker and a second page table walker based on a preset rule to execute an address translation operation to obtain a physical address, and sending a pre-fetching request to a target preset cache space by the first page table walker; and responding to the prefetching request, and performing information prefetching operation on the target preset cache space based on the physical address. The method can reduce address translation time delay and simultaneously realize the data/instruction prefetching function, reduce the time delay of read-write operation and improve the overall performance of the system.

Description

Information prefetching method, processor, electronic device

technical field

Embodiments of the present disclosure relate to an information prefetching method, a processor, and an electronic device.

Background technique

In the field of computer technology, one of the important functions of a computer operating system is memory management. In a multi-process operating system, each process has its own virtual address space and can use any virtual address (Virtual Address) within the range specified by the system. An address used by a central processing unit (Central Processing Unit, CPU) to execute an application program is a virtual address. When the operating system allocates memory to a process, it needs to map the virtual address used to the physical address, and the physical address is the real physical memory access address. By distinguishing addresses into virtual addresses and physical addresses in this way, program compilation can be simplified, so that the compiler compiles programs based on a continuous and sufficient virtual address space, and the virtual addresses of different processes are assigned to different physical addresses, It enables the system to run multiple processes at the same time, thereby improving the operating efficiency of the entire computer system. In addition, since the address translation can be used by applications but cannot be changed, one process cannot access the memory contents of another process, thus increasing the security of the system.

SUMMARY OF THE INVENTION

At least one embodiment of the present disclosure provides an information prefetching method for a processor, wherein the processor includes a first-level cache space, a first page table walker, a second page table walker, and at least one preset Cache space, the first-level cache space and the at least one preset cache space are sequentially connected in communication to form a communication link, the at least one preset cache space includes a target preset cache space, the first page table The traverser and the target preset cache space are set at the same path level, the first page table traverser is in communication connection with the target preset cache space, and the second page table traverser is connected to the first level cache The space is set at the same path level, the second page table traverser is connected in communication with the first level cache space, and the method includes: in response to the first page table traverser and the first page table traverser based on a preset rule. Among the two page table walkers, the first page table walker is selected to perform an address translation operation to obtain a physical address, and the first page table walker sends a prefetch request to the target preset cache space, wherein the prefetch The request includes the physical address; in response to the prefetch request, the target preset cache space performs an information prefetch operation based on the physical address.

For example, in the method provided by an embodiment of the present disclosure, the processor further includes a processor core, wherein performing the information prefetching operation on the target preset cache space based on the physical address includes: determining a prefetch cache space , wherein the prefetch cache space is at least one of the first-level cache space and the at least one preset cache space; based on the physical address, the target preset cache space obtains the physical address corresponding to the stored target information; the target preset buffer space sends the target information to the prefetch buffer space.

For example, in the method provided by an embodiment of the present disclosure, determining the prefetching cache space includes: acquiring a preset identifier, where the preset identifier represents level information of the cache space, and the preset identifier is stored in a specified The storage space is either carried in the prefetch request; the prefetch cache space is determined according to the preset identifier.

For example, in the method provided by an embodiment of the present disclosure, the first-level cache space includes a first-level instruction space and a first-level data space, the level information indicates the first level, and the first level is determined according to the preset identifier. The prefetch cache space includes: in response to the target information being an instruction type, determining that the prefetch cache space is the first-level instruction space; in response to the target information being a data type, determining the prefetch cache space The space is the first level data space.

For example, in the method provided by an embodiment of the present disclosure, acquiring, by the target preset cache space, the target information stored corresponding to the physical address based on the physical address includes: based on the physical address, from the physical address The target information is acquired in a step-by-step query manner in the path from the target preset cache space to the memory.

For example, in the method provided by an embodiment of the present disclosure, the target preset cache space sending the target information to the prefetch cache space includes: from the target preset cache space to the prefetch cache space The target information is sent to the prefetch buffer space in a step-by-step manner in the path of the space.

For example, in the method provided by an embodiment of the present disclosure, the method further includes: sending the physical address to the processor core by the target preset cache space.

For example, in the method provided by an embodiment of the present disclosure, the sending, by the target preset cache space, the physical address to the processor core includes: the target preset cache space transfers the all The physical address is sent to the processor core.

For example, in the method provided by an embodiment of the present disclosure, the processor further includes a page table entry cache space, the processor core and the page table entry cache space are set at the same path level, and the processor core and the page table entry cache space are set at the same path level. The page table entry cache space communication connection, the method further includes: in response to the page table entry cache space does not exist in the page table entry data required for address translation, using the processor core to generate the address translation request .

For example, the method provided in an embodiment of the present disclosure further includes: in response to selecting the first page table traversal in the first page table traverser and the second page table traverser based on the preset rule The first page table walker performs the address translation operation in response to the address translation request to obtain the physical address.

For example, in the method provided by an embodiment of the present disclosure, the first page table walker performs the address translation operation in response to the address translation request to obtain the physical address, including: the first page table The traverser receives the address translation request generated by the processor core, obtains page table entry data from the memory via the target preset cache space, and uses the page table entry data to perform the address translation operation to obtain the address translation request. the physical address.

For example, in the method provided by an embodiment of the present disclosure, the first page table traverser obtains the page table entry data from the memory via the target preset cache space, and uses the page table entry data to perform The address translation operation includes: the first page table traverser obtains the page table entry data in a step-by-step query manner from the path from the target preset cache space to the memory according to the address translation request , and use the page table entry data for translation to obtain the physical address.

For example, the method provided in an embodiment of the present disclosure further includes: in response to the first page table walker being determined to perform the address translation operation, the first page table walker receives the second page table walker The address translation request forwarded by the server.

For example, in the method provided by an embodiment of the present disclosure, the address translation request includes translation information, and the translation information includes: the address translation request serial number, the virtual address value to be translated, and the initial address of the highest-level page table.

For example, in the method provided by an embodiment of the present disclosure, the translation information further includes a request type identifier, where the request type identifier indicates that the target information stored corresponding to the physical address is an instruction type or a data type.

For example, in the method provided in an embodiment of the present disclosure, the method further includes: determining, by the processor core, a cache for storing the target information according to the storage state of the first-level cache space and the at least one preset cache space space, and make the address translation request carry the level information of the cache space used to store the target information in the form of the preset identifier; the first page table traverser parses and obtains the preset identifier, and makes The prefetch request carries the preset identifier.

For example, the method provided in an embodiment of the present disclosure further includes: in response to selecting the second page table traversal in the first page table traverser and the second page table traverser based on the preset rule The second page table walker performs the address translation operation in response to the address translation request to obtain the physical address.

For example, in the method provided by an embodiment of the present disclosure, the second page table walker performs the address translation operation in response to the address translation request to obtain the physical address, including: the second page table The traverser receives the address translation request generated by the processor core, obtains page table entry data from the memory according to the address translation request, and performs address translation using the page table entry data to obtain the physical address.

For example, in the method provided by an embodiment of the present disclosure, the preset rule includes: when the page table entry data required for address translation does not exist in the page table entry cache space, or the page table entry cache space does not exist in the page table entry cache space When the page table level corresponding to the page table entry data required for address translation is greater than a threshold, it is determined that the address translation operation is performed by the first page table walker.

For example, in the method provided by an embodiment of the present disclosure, the processor further includes a request buffer area, the request buffer area and the first page table traverser are set at the same path level, the request buffer area and all The first page table traverser is communicatively connected, and is communicatively connected to the target preset buffer space, and the method further includes: using the processor core to send a pending address translation request queue to the request buffer area.

For example, in the method provided by an embodiment of the present disclosure, the at least one preset cache space includes a second-level cache space to an Nth-level cache space, where N is an integer greater than 2, and the Nth-level cache space is far from the memory The closest and farthest from the processor core, any level cache space from the second level cache space to the Nth level cache space is used as the target preset cache space.

For example, in the method provided by an embodiment of the present disclosure, the Nth level cache space is a shared type cache space, and the Nth level cache space is used as the target preset cache space.

For example, in the method provided by an embodiment of the present disclosure, the second-level cache space is a private-type or shared-type cache space, and the second-level cache space serves as the target preset cache space.

At least one embodiment of the present disclosure further provides a processor including a first-level cache space, a first page table walker, a second page table walker, and at least one preset cache space, wherein the first-level cache space and the at least one preset cache space is sequentially connected in communication to form a communication link, the at least one preset cache space includes a target preset cache space, and the first page table traverser is connected to the target preset cache space Set at the same path level, the first page table traverser is in communication connection with the target preset cache space, the second page table traverser and the first level cache space are set at the same path level, the Two page table walkers are connected in communication with the first-level cache space, and the first page table walker is configured to: in response to traversing the first page table walker and the second page table walker based on a preset rule The first page table traverser is selected to perform an address translation operation to obtain a physical address, and a prefetch request is sent to the target preset cache space, wherein the prefetch request includes the physical address; the target preset The cache space is configured to perform an information prefetch operation based on the physical address in response to the prefetch request.

For example, in the processor provided by an embodiment of the present disclosure, the target preset cache space is further configured to determine a prefetch cache space, obtain target information stored corresponding to the physical address based on the physical address, and store the The target information is sent to the prefetch buffer space, where the prefetch buffer space is at least one of the first level buffer space and the at least one preset buffer space.

At least one embodiment of the present disclosure further provides an electronic device, including the processor provided by any embodiment of the present disclosure.

Description of drawings

1 is a schematic diagram of an address translation process;

2 is a schematic diagram of the architecture of a multi-core processor;

Fig. 3 is the data flow schematic diagram that adopts the processor shown in Fig. 2 to carry out address translation;

Fig. 4 is the process schematic diagram that adopts the processor shown in Fig. 2 to carry out address translation and request data;

FIG. 5 is a schematic structural diagram of a processor according to some embodiments of the present disclosure;

6 is a schematic flowchart of a method for information prefetching provided by some embodiments of the present disclosure;

7 is a schematic diagram of a process for performing address translation and requesting data using the processor provided by an embodiment of the present disclosure;

Fig. 8 is an exemplary flowchart of step S20 in Fig. 6;

Fig. 9 is an exemplary flowchart of step S21 in Fig. 8;

Fig. 10 is an exemplary flowchart of step S212 in Fig. 9;

11 is a schematic flowchart of another information prefetching method provided by some embodiments of the present disclosure;

12 is a schematic flowchart of another information prefetching method provided by some embodiments of the present disclosure;

13 is a schematic flowchart of another information prefetching method provided by some embodiments of the present disclosure;

14 is a schematic flowchart of another information prefetching method provided by some embodiments of the present disclosure;

FIG. 15 is a schematic block diagram of an electronic device according to some embodiments of the present disclosure;

FIG. 16 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. As used in this disclosure, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. "Comprises" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to represent the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

FIG. 1 is a schematic diagram of an address translation process, showing an address translation process of a four-level page table. As shown in FIG. 1 , a virtual address is divided into several segments, such as EXT, OFFSET_lvl4, OFFSET_lvl3, OFFSET_lvl2, OFFSET_lvl1, and OFFSET_pg, respectively. In this example, the upper virtual address segment EXT is not used. The virtual address segments OFFSET_lvl4, OFFSET_lvl3, OFFSET_lvl2, and OFFSET_lvl1 respectively represent the offset value of the fourth-level page table, that is, the virtual address segment OFFSET_lvl4 represents the offset value of the fourth-level page table, and the virtual address segment OFFSET_lvl3 represents the third-level page table. The offset value of the virtual address segment OFFSET_lvl2 represents the offset value of the second-level page table, and the virtual address segment OFFSET_lvl1 represents the offset value of the first-level page table.

The initial address of the highest-level page table (ie, the fourth-level page table) is stored in the architecture register REG_pt, the content of which is set by the operating system and cannot be changed by the application program. In the second-level page table, the third-level page table, and the fourth-level page table, the page table entry of each level of page table stores the starting address of the next-level page table. The first-level page table entry (Page Table Entry, PTE) stores the high order of the physical address of the corresponding memory page, which is combined with the virtual address offset (OFFSET_pg) to obtain the physical address corresponding to the virtual address. Therefore, in this way, the starting address of the next-level page table is obtained step by step, and finally the first-level page table entry (PTE) can be obtained, thereby further obtaining the corresponding physical address, which realizes the transition from virtual address to physical address. translate.

It should be noted that although FIG. 1 shows a 4-level page table, embodiments of the present disclosure are not limited thereto, and any number of multi-level page tables may be used, such as a 2-level page table, a 3-level page table, and a 5-level page table. Tables, etc., a single-level page table may also be used, which may be determined according to actual requirements, which is not limited by the embodiments of the present disclosure. For example, a system may support pages of different sizes, the size of each page being represented by the number of bits of the virtual address offset OFFSET_pg. On the same system, larger pages require fewer address translation stages.

FIG. 2 is a schematic diagram of the architecture of a multi-core processor. For example, as shown in FIG. 2, the processor has 4 processor cores (CPU Core). At the same time, the processor also has multi-level caches, such as the first level cache (L1 Cache), the second level cache (L2 Cache) and the last level cache (Last Level Cache, LLC). In this example, the last level cache is actually the third level cache (L3 Cache). Of course, the embodiments of the present disclosure are not limited thereto, and the processor may have any number of multi-level caches, so the last level of cache may also be a cache of any level, which may be determined according to actual requirements.

For example, in this example, the last level cache is shared by multiple processor cores, and the second level cache is private to each processor core. That is, multiple processor cores share a last-level cache, while each processor core is provided with a dedicated second-level cache. The last level cache and the second level cache are used to store instructions and data, and the last level cache is connected to the memory. It should be noted that, in other examples, the second-level cache may also be a shared-type cache, which is not limited in this embodiment of the present disclosure.

For example, a dedicated first-level cache is separately set for each processor core, and the first-level cache is set inside the processor core. For example, the first-level cache may include a first-level instruction cache (L1I cache) and a first-level data cache (L1D cache) for caching instructions and data, respectively. The processor further includes a memory, and the processor core realizes instruction transfer and data reading through a multi-level cache and a data cache mechanism of the memory.

For example, a translation lookaside buffer (TLB) is separately provided for each processor core, and the translation lookaside buffer may include a translation lookaside buffer (ITLB) for instructions and a translation lookaside buffer (DTLB) for data. Both ITLB and DTLB are set inside the processor core.

Address translation is a very time-consuming process. For multi-level page tables, it usually requires multiple memory accesses to obtain the corresponding physical address. Taking the 4-level page table shown in Figure 1 as an example, it needs to access the memory 4 times to obtain the corresponding physical address. Therefore, in order to save address translation time and improve computer system performance, a TLB (for example, including ITLB and DTLB) may be set in the processor core to store previously used first-level page table entries (PTEs). When address translation is required, the TLB is firstly queried to see if there is a required PTE, and if it hits, the corresponding physical address can be obtained immediately. Similar to the CPU cache architecture, TLB can also have multiple architectures, such as Fully Associative, SetAssociative, Directly Indexed, and so on. The TLB architecture can also be a multi-level structure. The lowest level TLB has the smallest size and the fastest speed. When the lowest level TLB is not hit, the next level TLB is searched.

Although TLB can reduce the delay of a lot of address translation, in the process of executing the program, it is unavoidable to access the page table for address translation. In order to reduce the time required for the translation operation, a hardware page table walker (Hardware Page Table Walker, PTW) is usually set separately for the processor core, and the hardware page table walker is set inside the processor core. By using a hardware page table walker, a multi-level page table can be traversed to obtain the final physical address of a memory page.

L1I cache and L1D cache are accessed using physical addresses (physically indexed, virtually tagged), and the second-level cache, last-level cache, and memory are also accessed using physical addresses. Therefore, address translation through ITLB or DTLB is required before accessing data. Consistent with the normal data read request, the read request of the hardware page table walker can reach the memory through the first-level cache, the second-level cache, and the last-level cache at the farthest. If the data requested by the hardware page table walker exists in a certain level of cache, the cache returns the data, and no longer transmits the request of the hardware page table walker to the lower-level cache/memory.

FIG. 3 is a schematic diagram of a data flow for performing address translation using the processor shown in FIG. 2 . As shown in Figure 3, in a possible situation, the TLB is not hit and therefore needs to access the memory for address translation. At this time, it is necessary to access the memory 4 times to obtain the physical address of the final memory page. In new application scenarios such as big data, cloud computing, and artificial intelligence (AI), large instruction and data spaces are often used at the same time, and the number of hot instruction segments and data segments is large and scattered. Therefore, these new applications often have more cache misses (Cache Miss) and TLB misses (TLB Miss). This makes the data request of the hardware page table walker often not in a certain level of cache, but can only perform address translation through multiple memory accesses.

In the usual CPU architecture, the instructions and data of the program are stored in the memory, and the operating frequency of the processor core is much higher than the operating frequency of the memory. Therefore, it takes hundreds of clocks to obtain data or instructions from the memory, which often causes The processor core is idling because it cannot continue to run the relevant instructions, resulting in a performance loss. Therefore, modern high-performance processors contain multi-level cache architectures to save recently accessed data, while prefetching upcoming data and instructions into the cache in advance. By prefetching data and instructions to the cache in advance, the corresponding read and write operations can hit the cache, thereby reducing latency.

When the processor shown in FIG. 2 is used, the process of address translation and requesting data is shown in FIG. 4 . For example, when a TLB miss (TLB Miss) occurs in a data read request, it is necessary to traverse the page table first to obtain the physical address, that is, read the four-level page table entry from the memory for address translation, and then according to the translation obtained The physical address gets the corresponding data from cache/memory. The time between the two pentagrams in Figure 4 is all the delays for the operation, including the address translation delay (the longest distance between the solid lines) and the data read delay (the distance between the dashed lines).

In the example shown in Figure 4, a data read and write operation that requires address translation through page table traversal (the operation may itself be a data prefetch request) has no chance to perform data prefetch, only after obtaining the physical address , fetches data from memory through multi-level caches. This makes data prefetching ineffective, cannot reduce latency, and has a negative impact on the overall performance of the system.

At least one embodiment of the present disclosure provides an information prefetching method, a processor, and an electronic device. The information prefetching method can realize the data/instruction prefetching function while reducing the address translation time delay, effectively reduce the data/instruction read and write operation time delay, and improve the overall performance of the system.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used in different drawings to refer to the same elements that have been described.

At least one embodiment of the present disclosure provides an information prefetching method for a processor. The processor includes a first-level cache space, a first page table traverser, a second page table traverser and at least one preset cache space, the first-level cache space and the at least one preset cache space are sequentially connected in communication to form communication link. At least one preset cache space includes a target preset cache space, the first page table traverser and the target preset cache space are set at the same path level, and the first page table traverser is connected in communication with the target preset cache space. The second page table traverser and the first-level cache space are set at the same path level, and the second page table traverser is in communication connection with the first-level cache space. The information prefetching method includes: in response to selecting the first page table traverser from the first page table traverser and the second page table traverser to perform an address translation operation to obtain a physical address based on a preset rule, the first page table traverser sends a request to the physical address. The target preset cache space sends a prefetch request, wherein the prefetch request includes a physical address; in response to the prefetch request, the target preset cache space performs an information prefetch operation based on the physical address.

At least one embodiment of the present disclosure provides a processor. The processor includes a first level cache space, a first page table walker, a second page table walker and at least one preset cache space. The first-level buffer space and at least one preset buffer space are sequentially connected in communication to form a communication link. At least one preset cache space includes a target preset cache space, the first page table traverser and the target preset cache space are set at the same path level, and the first page table traverser is connected in communication with the target preset cache space. The second page table traverser and the first-level cache space are set at the same path level, and the second page table traverser is in communication connection with the first-level cache space. The first page table traverser is configured to, in response to selecting the first page table traverser from the first page table traverser and the second page table traverser to perform an address translation operation based on a preset rule, obtain a physical address, and send the physical address to the target preset cache space. A prefetch request is sent, and the prefetch request includes a physical address; the target preset cache space is configured to perform an information prefetch operation based on the physical address in response to the prefetch request.

FIG. 5 is a schematic structural diagram of a processor according to some embodiments of the present disclosure. The processor provided by the embodiment of the present disclosure is first described below with reference to FIG. 5 , and then the information prefetching method provided by the embodiment of the present disclosure is described.

As shown in FIG. 5 , in some embodiments of the present disclosure, the processor includes a processor core, a first-level cache space, a first page table walker, a second page table walker, and at least one preset cache space. In some examples, the first page table walker and the second page table walker may be the aforementioned hardware page table walkers (PTW). Here, the first page table traverser and the second page table traverser may be the aforementioned PTW, which means that the address translation functions implemented by them are similar, and the adopted address translation principles are similar, and the first page table traverser is the same as the aforementioned PTW. The hardware structure, setting location, etc. of the second page table traverser may be different, and the hardware structure, setting location, etc. of the second page table traverser and the aforementioned PTW may also be different, which is not limited by the embodiment of the present disclosure. The first page table walker is the newly added hardware page table walker (PTW). The table traverser can be set at the same path level as the first level cache space.

For example, the first level cache space is the L1 cache, which is set inside the processor core. For example, the first-level cache space and the processor core are set at the same path level, the first-level cache space is connected in communication with the processor core, and the processor core can directly obtain data or instructions from the first-level cache space. Here, "arranged at the same path level" means that the physical positions in the chip are adjacent or close, and data exchange and transfer can be performed directly. Therefore, setting the first-level cache space and the processor core at the same path level may mean that the first-level cache space is located next to the processor core and is relatively close to the processor core, and the processor core can be directly connected to the first-level cache space. Data exchange and transmission. For example, a "communication connection" means that data/instructions can be transferred directly.

For example, the second page table traverser and the first-level cache space are set at the same path level, and the second page table traverser is communicatively connected to the first-level cache space. The second page table traverser is set at the same path level as the first-level cache space. It may mean that the second page table traverser is set next to the first-level cache space, is close to the first-level cache space, and is located at the first-level cache space. The cache space can directly interact and transfer data with the second page table walker. For another example, the second page table walker may be disposed inside the processor core, the second page table walker may be logically disposed at the same path level as the processor core, and the second page table walker is communicatively connected to the processor core.

In some examples, the first level cache space includes an L1I cache for storing instructions and an L1D cache for storing data. Of course, the embodiments of the present disclosure are not limited to this, and in other examples, the L1I cache and the L1D cache may not be distinguished, but only one L1 cache is provided, which is used to store both data and instructions.

For example, in some examples, the at least one preset cache space includes the second level cache space to the Nth level cache space, where N is an integer greater than 2. The Nth level cache space is closest to the memory and farthest from the processor core. For example, in the example shown in FIG. 4 , at least one preset cache space may include a second-level cache space (L2 cache) and a last-level cache space (LLC), that is, N=3 at this time. Of course, the embodiments of the present disclosure are not limited to this, and N can be any integer greater than 2, such as 4, 5, 6, etc. Correspondingly, the processor has a level-4 cache architecture, a level-5 cache architecture, and a level-6 cache. architecture, etc. For example, in some other examples, the at least one preset cache space includes one cache space, that is, only includes the second-level cache space, and in this case, the processor is a level-2 cache architecture. It should be noted that, in the processor provided by the embodiments of the present disclosure, in addition to the first-level cache space, other levels of cache may be collectively referred to as a preset cache space.

For example, the first-level cache space and at least one preset cache space are sequentially connected in communication to form a communication link, so that data acquisition can be implemented in a step-by-step manner. For example, when the processor core needs to obtain data, it can first query the first-level cache space, if there is no hit, continue to the second-level cache space query, and if there is still no hit, then go to the last-level cache space query. If the last level of cache space is still not hit, go to the memory to get the data. Similarly, when the second page table traverser needs to obtain data, it can first query the first-level cache space. If there is no hit, it will continue to the second-level cache space to query. If there is still no hit, it will go to the last-level cache space. Inquire. If the last level of cache space is still not hit, go to the memory to get the data.

For example, the at least one preset cache space includes a target preset cache space, and the target preset cache space may be any one of a plurality of preset cache spaces. For example, any level cache space from the second level cache space to the Nth level cache space may be used as the target preset cache space. The first page table traverser and the target preset cache space are set at the same path level, and the first page table traverser is connected in communication with the target preset cache space.

For example, in the example of FIG. 5, the last level cache space is used as the target preset cache space, the first page table traverser and the last level cache space are set at the same path level, and the first page table traverser and the last level cache space are set at the same path level. Space communication connection. Here, "arranged at the same path level" means that the physical positions in the chip are adjacent or close, and data exchange and transfer can be performed directly. Therefore, setting the first page table traverser and the last level of cache space at the same path level may mean that the first page table traverser is set next to the last level of cache space, and is closer to the last level of cache space, and the last The first-level cache space can directly interact and transfer data with the first page table walker.

For example, in some examples, the Nth level cache space is a shared type of cache space, and the Nth level cache space is used as the target preset cache space, and this example is the situation shown in FIG. 5 . For example, in other examples, the second-level cache space is a private type or a shared type of cache space, and the second-level cache space is used as the target preset cache space. That is, in some processor architectures, the second-level cache space is provided separately for each processor core and is of a private type, while in other processor architectures, the second-level cache space is multiple processors. If the core is shared, it belongs to the shared type. Regardless of whether the second-level cache space is a private type or a shared type, the second-level cache space can be used as the target preset cache space.

It should be noted that although FIG. 5 shows that the last-level cache space is used as the target preset cache space and the first page table traverser is set beside the last-level cache space, this does not constitute a negative impact on the embodiment of the present disclosure. limits. In other examples, in the case where the second-level cache space is used as the target preset cache space, the first page table walker is disposed beside the second-level cache space and is communicatively connected with the second-level cache space. In some examples, when the processor includes more levels of cache, any other level-1 cache space except the first-level cache space can be used as the target preset cache space, and the first page table walker is adjusted accordingly setting location. It should be noted that the first page table walker is not set in the processor core, or the first page table walker is not set next to the first level cache space.

For example, the first page table walker is configured to, in response to selecting the first page table walker from the first page table walker and the second page table walker to perform an address translation operation based on a preset rule, obtains a physical address, and presets a physical address to the target. Cache space to send prefetch requests. For example, the prefetch request includes a physical address, that is, the prefetch request carries the physical address translated by the first page table walker. For example, when a virtual address needs to be translated to a physical address, if there is a miss in ITLB or DTLB, and it is determined that the address translation operation is performed by the first page table walker, the processor core will send the first page table walker to the first page table walker. Address translation request. The architecture of the TLB is not limited to the manners of ITLB and DTLB, and any applicable architecture may be adopted, which is not limited by the embodiments of the present disclosure.

For example, an address translation request may trigger the first page table walker to perform an address translation operation. The address translation request may be transmitted to the first page table traverser through a multi-level cache architecture, or may be transmitted to the first page table traverser through a pipeline inside the processor. The embodiment of the present disclosure does not limit the transmission method of the address translation request. In the case where the address translation request is passed to the first page table walker through the multi-level cache architecture, the address translation request adopts a data read request type recognizable by the multi-level cache architecture.

For example, the address translation operation may be an address translation process of a multi-level page table, and reference may be made to the description about FIG. 1 , which will not be repeated here. It should be noted that the page table for address translation is not limited to 4 levels, and any number of multi-level page tables can be used, such as 2-level page tables, 3-level page tables, 5-level page tables, etc., and single-level page tables can also be used. , which can be determined according to actual requirements, which is not limited by the embodiments of the present disclosure. For example, the greater the number of page table levels, the more times the memory is accessed for each address translation, and therefore the greater the performance improvement space that the processor provided by the embodiments of the present disclosure can provide. For example, the physical page size of the page table is not limited and can be determined according to actual needs.

The address translation request may include translation information. The translation information may include: address translation request sequence number, virtual address value to be translated, and initial address of the top-level page table. After the first page table traverser receives the address translation request, it will be triggered to perform the address translation operation, and based on the translation information, it can obtain the content required for the address translation operation, such as the virtual address value, the initial address of the highest-level page table, and so on. In some examples, Addr_Trans_Req may be used to indicate that the request is an address translation request, Addr_Trans_SN may be used to indicate the address translation request sequence number, REG_pt may be used to indicate the initial address of the highest level page table (ie, the REG_pt value of the process), and VA may be used to indicate that translation is required virtual address value.

For example, the translation information may also include a request type identification. The request type identifier indicates that the target information stored corresponding to the physical address is an instruction type or a data type. In some examples, I/D may be used to indicate whether the request corresponds to an instruction or data, for example, I may be used to indicate an instruction, and D may be used to indicate data.

Since the first page table walker is set next to the target preset cache space (the last level cache space in this example), the first page table walker is relatively close to the memory. The time to obtain the page table entry is shorter, which significantly improves the efficiency of address translation and greatly reduces the time spent in address translation. The first page table walker is not located next to the first-level cache space (L1 cache), getting rid of the constraints of usually setting the first page table walker in the processor core, and because the first page table walker can be more It is close to the memory, so it can reduce the delay of the first page table traverser to access the memory and address translation, and improve the system performance of the processor. This setting method of the first page table walker is suitable for various new application scenarios (such as big data, cloud computing, AI, etc.) and various CPU architectures, which can further improve the performance of these new application scenarios.

It should be noted that, in the embodiments of the present disclosure, the first page table traverser may be set beside any level of cache space except the first level cache space, or the first page table traverser may be set directly in Next to the memory, this can be determined according to actual needs, for example, according to various factors such as processor architecture, technology, cache size and delay, memory delay, whether to support cache coherence, common application characteristics and other factors. This is not limited.

For example, the target preset cache space is configured to perform an information prefetch operation based on a physical address in response to a prefetch request. For example, the target preset buffer space is further configured to: determine the prefetch buffer space, obtain target information stored corresponding to the physical address based on the physical address, and send the target information to the prefetch buffer space. For example, the prefetch cache space is at least one of the first-level cache space and at least one preset cache space, that is, it may be any one or more cache spaces of the first-level cache space and the preset cache space. For example, in some examples, the prefetch cache space is the cache space that is closer to the processor core than the target preset cache space in the communication link formed by the first level cache space and the at least one preset cache space, thereby Prefetching efficiency can be improved. Of course, in other examples, the prefetch cache space may also be a cache space farther from the processor core than the target preset cache space.

That is, before the processor core receives the physical address and requests information (such as data or instructions), the target preset cache space performs an information prefetch operation according to the physical address, and stores the target information corresponding to the physical address in the prefetch. cache space. Therefore, when the processor core requests information based on the physical address, it can hit in the prefetch cache space, thereby effectively reducing the time delay and realizing data/instruction prefetching.

For example, as shown in FIG. 5 , the processor further includes a page table entry cache space, and the page table entry cache space may be the aforementioned translation lookaside buffer (TLB). For example, the page table entry cache space may include a translation lookaside buffer (ITLB) for instructions and a translation lookaside buffer (DTLB) for data. For example, the processor core and the page table entry cache space are set at the same path level, and the processor core is communicatively connected to the page table entry cache space. Here, "arranged at the same path level" means that the physical positions in the chip are adjacent or close, and data exchange and transfer can be performed directly. Therefore, setting the processor core and the page table entry cache space at the same path level may mean that the page table entry cache space is set next to the processor core, which is close to the processor core, and the processor core can be connected to the page table entry cache space. Direct data interaction and transmission. For example, a "communication connection" means that data/instructions can be transferred directly. For another example, the page table entry cache space may be set in the processor core, and may be at the same path level as the second page table traverser also set in the processor core, and the second page table traverser communicates with the page table entry cache space. connect. For example, the second page table walker is placed at the same path level as the translation lookaside buffer (ITLB) for instructions and the translation lookaside buffer (DTLB) for data. For example, page table entry cache space can be located inside the processor core.

For example, the page table entry cache space, the first-level cache space, and the at least one preset cache space are sequentially connected in communication to form a communication link, so that data acquisition can be achieved step by step downward. For example, when the second page table traverser set in the processor core needs to obtain data (such as page table entry data), it can first query the page table entry cache space, and if there is no hit, continue to the first level cache space query , if there is no hit, continue to the second level cache space query, if there is still no hit, then go to the last level cache space query. If the last level of cache space is still not hit, go to the memory to get the data.

For example, the page table entry cache space stores at least part of the page table entry data of the page table entry data of the first level page table to the page table entry data of the Mth level page table, where M is an integer greater than 1. That is, the page table entry cache space can store any recently used page table entry data, such as PTE and so on.

For example, as shown in FIG. 5, the processor may also include a request buffer. The request buffer area may also be called a page request buffer (Page Request Buffer, PRB), and the request buffer area and the first page table traverser are set at the same path level. The request buffer area is connected in communication with the first page table traverser, and is in communication connection with the target preset buffer space, and the request buffer area is, for example, set between the first page table traverser and the target preset buffer space. Here, "arranged at the same path level" means that the physical positions in the chip are adjacent or close, and data exchange and transfer can be performed directly. Therefore, setting the request buffer area and the first page table traverser at the same path level may mean that the request buffer area is set next to the first page table traverser, and is closer to the first page table traverser, and the first page table traversal area is The server can directly interact and transmit data with the request buffer. At the same time, the request buffer area can also directly interact and transmit data with the target preset buffer space.

The request buffer is configured to store a queue of pending address translation requests sent by the processor core. When the processor provided by the embodiment of the present disclosure includes multiple processor cores, the first page table walker cannot process address translation requests sent by multiple processor cores at the same time, so a request buffer area can be used to store pending address translations request queue. The first page table traverser can sequentially obtain address translation requests from the request buffer and perform corresponding address translation operations.

For example, in some examples, the processor core is configured to perform an address translation operation in response to selecting a first page table walker among the first page table walker and the second page table walker based on preset rules, and the first page table The traverser performs an address translation operation in response to an address translation request to obtain a physical address. For example, the processor dynamically selects to use the first page table walker or the second page table walker to process a new address translation request based on a preset rule, and selects a more suitable page table walker to reduce the delay of address translation. For example, the preset rules include: when the page table entry data required for address translation does not exist in the page table entry cache space, or the page table level in the page table entry cache space corresponding to the page table entry data required for address translation is greater than a threshold When it is determined that the address translation operation is performed by the first page table walker, otherwise, it is determined that the address translation operation is performed by the second page table walker. For example, the threshold is related to the CPU architecture and various factors in the chip process, and can be arbitrarily set according to actual requirements, which is not limited in the embodiments of the present disclosure.

For example, in some examples, if the page table entry data required for the address translation does not exist in the page table entry cache space, it is determined that the address translation operation is performed by the first page table walker. For example, in other examples, if the page table level in the page table entry cache space corresponding to the page table entry data required for address translation is greater than a threshold, it is determined that the address translation operation is performed by the first page table walker. Assuming that the threshold is 2, when the page table entry data corresponding to the address translation required in the page table entry cache space is the third-level page table entry data or the fourth-level page table entry data, it is determined that the first page table is traversed. The processor performs address translation operations. It should be noted that the preset rules are not limited to the methods described above, and any applicable rules can be used to select one of the first page table traverser and the second page table traverser to perform address translation operations, which can be based on actual needs. Rather, the embodiments of the present disclosure do not limit this.

For example, the processor core is configured to generate an address translation request in response to the absence of page table entry data required for the address translation in the page table entry cache space, and if it is determined that the address translation operation is performed by the first page table walker The first page table walker sends an address translation request. For example, when a virtual address needs to be translated into a physical address, if the page table entry data required for the address translation is not hit in the ITLB or DTLB, an address translation operation is required. At this time, the processor determines one of the first page table traverser and the second page table traverser to perform the address translation operation based on a preset rule. When it is determined that the address translation operation is performed by the first page table walker, the processor core sends an address translation request to the first page table walker. When it is determined that the address translation operation is performed by the second page table walker, the processor core sends an address translation request to the second page table walker. For example, the architecture of the TLB is not limited to the manner of ITLB and DTLB, and any applicable architecture may be adopted, which is not limited by the embodiments of the present disclosure.

For example, in some examples, the first page table walker is further configured to receive an address translation request generated by the processor core, obtain page table entry data from memory via the target preset cache space, and perform address translation operations using the page table entry data , to get the physical address.

For example, in this example, the first page table walker is not directly connected to the memory in communication, and does not directly access the memory, but indirectly accesses the memory through the target preset cache space to obtain page table entry data. For example, the first page table traverser is further configured to obtain page table entry data in a step-by-step query manner from the path from the target preset cache space to the memory according to the address translation request. The way of this level-by-level query is similar to the way of acquiring data level-by-level through a multi-level cache. For example, when the target preset cache space is the last level cache space, the first page table traverser accesses the memory through the last level cache space; when the target preset cache space is the second level cache space or other level cache space, The first page table traverser accesses memory by querying down level by level through the target preset cache space. For example, the first level cache space to the Nth level cache space store at least part of the page table entry data from the page table entry data of the first level page table to the page table entry data of the Mth level page table, where M is greater than 1 Integer.

Therefore, the page table entry data read by the first page table traverser can be stored in the target preset cache space and the cache space between the target preset cache space and the memory, which can facilitate the query of the cache in the next address translation process. If the page table entry that may exist in the space is hit, there is no need to access the memory, so as to further improve the efficiency of address translation and obtain less latency than memory access. Moreover, in the embodiment of the present disclosure, under the multi-core architecture, since the page table entry data read by the first page table traverser is stored in the target preset cache space, the cache coherency mechanism can ensure the first page table The traverser gets the correct page table entry content.

For example, in some examples, the first page table walker may include a multi-level page table cache (Page WalkCache, PWT). The multi-level page table cache area is configured to cache at least part of the page table entry data of the page table entry data of the first level page table to the page table entry data of the Mth level page table, where M is an integer greater than 1. For example, the multi-level page table cache area is a cache inside the page table walker, which is used to save the most recently used first-level page tables, second-level page table entries, third-level page table entries, and fourth-level page tables. entry and other arbitrary page table entries. If an address translation finds the corresponding page table entry in the multi-level page table cache, it can skip higher-level page table accesses, thereby reducing the number of memory accesses and address translation latency. It should be noted that the multi-level page table cache area is optimized for the micro-architecture of the page table traverser, and may also be omitted, which may be determined according to actual requirements, which is not limited by the embodiments of the present disclosure. Similarly, the second page table walker may also include a multi-level page table cache area.

For example, the first page table walker is further configured to send an error feedback instruction to the processor core to determine a page table entry read error in response to failing to obtain page table entry data required for address translation. That is, under the processor architecture, when the page table accessed at a certain level is not in memory, or the data operation does not match the attributes of the page table entry to which the data belongs, a page fault (Page Fault) will be triggered, and the operating system will to handle the exception. Therefore, when the page table entry data required for address translation cannot be obtained, the first page table traverser will send an error feedback instruction to the processor core. The error feedback instruction is, for example, an interrupt instruction or other types of instructions, indicating that there is a page table entry. Read error, which triggers Page Fault.

For example, in some examples, the first page table walker is further configured to send a data return instruction to the processor core. After the first page table walker completes the address translation operation, the corresponding physical address can be obtained. Therefore, the first page table walker sends a data return instruction to the processor core, thereby passing the physical address to the processor core. The data return instruction may be delivered to the processor core through a multi-level cache architecture, or may be delivered to the processor core through a pipeline inside the processor. The embodiment of the present disclosure does not limit the delivery manner of the data return instruction. In the case where the data return instruction is delivered to the processor core through the multi-level cache architecture, the data return instruction adopts a request-response type recognizable by the multi-level cache architecture.

For example, the data return instruction includes the address translation request sequence number, the physical address and attributes of the memory page, and the like. For example, in some examples, Addr_Trans_Resp may be used to indicate that the information is a reply to an address translation request Addr_Trans_SN (that is, to indicate that the information is a data return instruction), Addr_Trans_SN may be used to indicate the address translation request sequence number, and PTE may be used to indicate the corresponding first level Contents of page table entries, such as physical addresses and attributes of memory pages.

For example, the processor core is configured to generate an address translation request in response to selecting a second page table walker among the first page table walker and the second page table walker to perform an address translation operation based on a preset rule, and the second page table The traverser performs an address translation operation in response to an address translation request to obtain a physical address. Please refer to FIG. 2 for the process of performing the address translation operation by the second page table traverser, which will not be repeated here.

For example, in some examples, the second page table walker receives an address translation request generated by the processor core, obtains page table entry data from memory according to the address translation request, and performs address translation using the page table entry data to obtain a physical address. For example, where it is determined that the address translation operation is performed by the first page table walker, the second page table walker may receive the address translation request from the processor core and then forward the address translation request to the first page table walker , thus providing a variety of transmission methods for address translation requests. The first page table traverser performs an address translation operation after receiving the address translation request. For the specific address translation operation process, please refer to the above embodiment, and details are not repeated here.

It should be noted that, in the embodiment of the present disclosure, the processor may be a single-core architecture or a multi-core architecture, which is not limited by the embodiment of the present disclosure. The number of caches and how they are set are also unlimited, which can be determined according to actual needs. The processor is not limited to the structure shown in FIG. 5 , and may include more or less components, and the connection manner between the components is not limited.

FIG. 6 is a schematic flowchart of an information prefetching method provided by some embodiments of the present disclosure. This information prefetching method can be used for the processor shown in FIG. 5 . In some embodiments, as shown in FIG. 6 , the information prefetching method includes the following operations.

Step S10: In response to selecting the first page table traverser from the first page table traverser and the second page table traverser to perform the address translation operation based on the preset rule to obtain the physical address, the first page table traverser sends the target preset cache to the physical address. Space sends a prefetch request, wherein the prefetch request includes a physical address;

Step S20: In response to the prefetch request, the target preset cache space performs an information prefetch operation based on the physical address.

For example, in step S10, the processor selects the first page table traverser from the first page table traverser and the second page table traverser to perform the address translation operation based on a preset rule to reduce the delay of address translation and generate address translation ask. The first page table traverser receives the address translation request sent by the processor and performs an address translation operation to obtain a physical address.

For example, the preset rules include: when the page table entry data required for address translation does not exist in the page table entry cache space, or the page table level in the page table entry cache space corresponding to the page table entry data required for address translation is greater than a threshold When it is determined that the address translation operation is performed by the first page table walker, otherwise, it is determined that the address translation operation is performed by the second page table walker. For example, the threshold is related to the CPU architecture and various factors in the chip process, and can be arbitrarily set according to actual requirements, which is not limited in the embodiments of the present disclosure.

For example, after the first page table traverser obtains the physical address by performing the address translation operation, the first page table traverser sends a prefetch request to the target preset cache space. For example, the prefetch request includes a physical address, that is, the prefetch request carries the physical address, so that the target preset cache space can obtain the physical address.

For example, in step S20, after receiving the prefetch request, the target preset cache space will perform an information prefetch operation according to the physical address carried in the prefetch request. For example, the prefetch request is a request for triggering the target preset cache space to perform an information prefetch operation, and any applicable request type may be used, which is not limited in the embodiments of the present disclosure. For example, the information prefetching operation is used to implement information prefetching, and the prefetched target information may be data or an instruction, and the target information is stored in the storage space indicated by the physical address.

FIG. 7 is a schematic diagram of a process of performing address translation and requesting data by using a processor provided by an embodiment of the present disclosure. As shown in FIG. 7 , when a TLB miss (TLB Miss) occurs in a data read request, it is necessary to traverse the page table first to obtain the physical address. For example, in the case of address translation by the first page table walker, the first page table walker reads the four-level page table entry from memory for address translation, thereby obtaining the physical address. The physical address is sent to the processor core, and then the processor core obtains the corresponding data from the cache/memory according to the physical address.

Since the first page table traverser is set next to the target preset cache space (such as LLC), when the first page table traverser performs address translation in the way of page table traversal, the first page table traverser and the target preset cache space Obtain the requested physical address earlier than the processor core. At this time, before the processor core requests data based on the physical address, the target preset cache space can obtain the corresponding data from the memory according to the physical address in advance, and send it to the processor core (or can also send it to the designated cache, such as L1 cache or L2 cache, etc.) to achieve data prefetching. The time between the two pentagrams in Figure 7 is all the delays for this operation, including the address translation delay (the longest distance between the solid lines) and the data prefetch delay (the distance between the dashed lines).

In this example, the time of data prefetching is shown by the dotted line in FIG. 7 . Compared with the time to request data in Figure 4 (the time shown by the dotted line in Figure 4), the time saved by data prefetching is roughly equal to the delay from the processor core to the target preset cache space (eg LLC). Therefore, on the basis that the first page table walker is close to the memory to save the address translation delay, the data prefetching method can further save the delay of acquiring data.

In the above manner, the information prefetching method can realize the data/instruction prefetching function while reducing the address translation time delay, effectively reduce the data/instruction read and write operation time delay, and improve the overall performance of the system.

FIG. 8 is an exemplary flowchart of step S20 in FIG. 6 . In some examples, the above step S20 may further include the following operations.

Step S21: determine the prefetch cache space;

Step S22: Based on the physical address, the target preset cache space obtains the target information stored corresponding to the physical address;

Step S23: The target preset buffer space sends the target information to the prefetch buffer space.

For example, in step S21, a prefetch cache space needs to be determined first, and the prefetch cache space is used to cache the target information stored corresponding to the physical address. For example, the prefetch cache space is at least one of the first-level cache space and at least one preset cache space, that is, it may be any one or more cache spaces of the first-level cache space and the preset cache space. For example, in some examples, the prefetch cache space is the cache space that is closer to the processor core than the target preset cache space in the communication link formed by the first level cache space and the at least one preset cache space, thereby Prefetching efficiency can be improved. In the processor architecture shown in FIG. 5, the prefetch cache space may be an L2 cache or an L1 cache (L1I cache or L1D cache).

FIG. 9 is an exemplary flowchart of step S21 in FIG. 8 . In some examples, as shown in FIG. 9 , the above step S21 may further include the following operations.

Step S211: obtaining a preset identifier;

Step S212: Determine the prefetch cache space according to the preset identifier.

For example, in step S211, the preset identifier indicates the level information of the cache space, that is, indicates which level of cache space the prefetch cache space is. For example, when the preset identifier is 1, it means that the prefetch cache space is the L1 cache; when the preset identifier is 2, it means that the prefetch cache space is the L2 cache, and so on. It should be noted that the embodiment of the present disclosure does not limit the specific data format and representation of the preset identifier, as long as it can determine which level of cache space the prefetch cache space is based on the preset identifier.

For example, the preset identifier is stored in the designated storage space or carried in the prefetch request.

For example, in some examples, the preset identifier is stored in a designated storage space, that is, the preset identifier may be set in advance and is fixed. When you need to obtain the preset ID, you only need to read it from the specified storage space. In this way, the way of obtaining the preset identifier can be simplified.

For example, in other examples, the preset identifier is carried in the prefetch request. When the first page table traverser sends a prefetch request to the target preset cache space, the prefetch request carries the preset identifier, so that the target preset cache space can obtain the preset identifier to determine which prefetch cache space is. level cache space. The manner in which the first page table traverser determines the preset identifier will be described later, and will not be repeated here. In this way, the prefetching cache space can be dynamically selected, so that the prefetching cache space is not fixed to a certain level of cache space, and can be set flexibly in each prefetching, thereby improving the overall processing efficiency.

It should be noted that, in the embodiment of the present disclosure, the manner of acquiring the preset identifier is not limited to the manner described above, and may also be any other applicable manner, which may be determined according to actual needs, and the embodiment of the present disclosure is not limited to this. No restrictions apply.

For example, in step S212, after the preset identifier is acquired, the prefetch cache space may be determined according to the preset identifier. For example, when the preset identifier is 1, the prefetch cache space is determined to be the L1 cache; when the preset identifier is 2, the prefetch cache space is determined to be the L2 cache, and so on. In the processor architecture shown in FIG. 5 , the target preset cache space is LLC, so the determined prefetch cache space L1 cache or L2 cache is closer to the processor core than LLC, thereby improving prefetch efficiency.

For example, in some examples, the first-level cache space includes a first-level instruction space (eg, L1I cache) and a first-level data space (eg, L1D cache). In a possible situation, the level information represented by the preset identifier indicates the first level, that is, the preset identifier is 1, and the above step S212 may further include the following operations, as shown in FIG. 10 .

Step S212a: in response to the target information being the instruction type, determine that the prefetch cache space is the first-level instruction space;

Step S212b: In response to the target information being the data type, determine that the prefetch buffer space is the first-level data space.

For example, in step S212a and step S212b, since the first-level cache space includes L1I cache and L1D cache, which respectively cache different types of information, it is necessary to further determine which of the L1I cache and L1D cache the prefetch cache space is. . If the target information stored corresponding to the physical address is an instruction type, the prefetch cache space is determined to be an L1I cache; if the target information stored corresponding to the physical address is a data type, the prefetch cache space is determined to be an L1D cache. This allows the target information to be prefetched into the correct cache.

Returning to FIG. 8 , in step S22 , based on the physical address, the target preset cache space acquires target information stored corresponding to the physical address. For example, in some examples, step S22 may include: based on the physical address, acquiring target information in a step-by-step query manner from the path from the target preset cache space to the memory. If the target information is hit in a certain level of cache, it can be obtained directly. If the target information is not hit in the cache, it needs to be retrieved from memory. The way of level-by-level query is similar to the way of acquiring data level by level through multi-level cache.

For example, in some examples, the physical address PA may be expressed as: PA=(first-level PTE value)<<X|OFFSET_pg. Here, OFFSET_pg represents the virtual address offset, and X represents the log value of the memory page size. For example, for a 4KB page, its X value is 12. It should be noted that this is only an example of a physical address calculation method, and does not constitute a limitation on the embodiments of the present disclosure.

For example, in step S23, after acquiring the target information, the target preset buffer space sends the target information to the prefetch buffer space, so as to cache the target information in the prefetch buffer space. For example, in some examples, step S23 may include: sending the target information to the prefetch buffer space in a step-by-step manner in the path from the target preset buffer space to the prefetch buffer space. The way of passing level by level is similar to the way of passing data level by level through multi-level cache.

In the above way, the target information is cached in the prefetch cache space. When the processor core requests the target information according to the physical address, it can hit the prefetch cache space, thereby effectively reducing the latency of data/instruction read and write operations. Improve overall system performance. This prefetching method requires few hardware changes, and only needs to add less hardware resources, so it is easy to implement.

FIG. 11 is a schematic flowchart of another information prefetching method provided by some embodiments of the present disclosure. In some embodiments, in addition to including steps S10-S20, the information prefetching method may further include steps S30-S40. Steps S10-S20 in this embodiment are basically the same as steps S10-S20 shown in FIG. 6, and are not repeated here.

Step S30: In response to selecting the first page table traverser among the first page table traverser and the second page table traverser to perform the address translation operation based on the preset rule, the first page table traverser performs address translation in response to the address translation request operation to get the physical address;

Step S40: The target preset cache space sends the physical address to the processor core.

For example, in step S30, when a virtual address needs to be translated into a physical address, if there is a miss in the ITLB or DTLB, when it is determined according to a preset rule that the address translation operation is performed by the first page table walker, the processor core An address translation request is sent to the first page table walker. The architecture of the TLB is not limited to the manners of ITLB and DTLB, and any applicable architecture may be adopted, which is not limited by the embodiments of the present disclosure. For example, an address translation request may trigger the first page table walker to perform an address translation operation. For example, the address translation operation may be an address translation process of a multi-level page table, and reference may be made to the description about FIG. 1 , which will not be repeated here. It should be noted that the page table for address translation is not limited to 4 levels, and any number of multi-level page tables can be used, such as 2-level page tables, 3-level page tables, 5-level page tables, etc., and single-level page tables can also be used. , which can be determined according to actual requirements, which is not limited by the embodiments of the present disclosure. For example, the greater the number of page table levels, the more times the memory is accessed for each address translation, and therefore the greater the performance improvement space that the processor provided by the embodiments of the present disclosure can provide. For example, the physical page size of the page table is not limited and can be determined according to actual needs.

For example, in some examples, step S30 may include: the first page table traverser receives the address translation request generated by the processor core, obtains page table entry data from the memory via the target preset cache space, and uses the page table entry data for address translation Translate operations to obtain physical addresses. For example, the first page table traverser obtains page table entry data in a step-by-step query manner from the path from the target preset cache space to the memory according to the address translation request, and uses the page table entry data for translation to obtain the physical address.

For example, the address translation request includes translation information, and the translation information includes: the address translation request serial number, the virtual address value to be translated, and the initial address of the top-level page table. In some examples, Addr_Trans_Req may be used to indicate that the request is an address translation request, Addr_Trans_SN may be used to indicate the address translation request sequence number, REG_pt may be used to indicate the initial address of the highest level page table (ie, the REG_pt value of the process), and VA may be used to indicate that translation is required virtual address value.

For example, the translation information may further include a request type identifier, where the request type identifier indicates that the target information stored corresponding to the physical address is an instruction type or a data type. In some examples, I/D may be used to indicate whether the request corresponds to an instruction or data, eg, I for an instruction and D for data. Therefore, in the case where the preset cache space is the first-level cache space, the preset cache space may be determined to be the L1I cache or the L1D cache according to the type of target information.

For example, in step S40, after the first page table traverser performs an address translation operation to obtain a physical address and sends a prefetch request to the target preset cache space, the target preset cache space sends the physical address to the processor core. Since the prefetch request carries the physical address, the target preset cache space can obtain the physical address. Of course, the embodiment of the present disclosure is not limited to this, and the first page table walker can also send the physical address to the target preset cache space independently, which can be determined according to actual requirements.

For example, in some examples, step S40 may include: the target preset cache space transmits the physical address to the processor core in a level-by-level transfer manner, that is, transferred to the processor core through a multi-level cache architecture. Of course, the embodiment of the present disclosure is not limited to this, and the physical address may also be delivered to the processor core through a pipeline inside the processor, which is not limited in the embodiment of the present disclosure. For example, the transfer of the physical address can be accomplished using a data return instruction. For example, the data return instruction includes the address translation request sequence number, the physical address and attributes of the memory page, and the like. For example, in some examples, Addr_Trans_Resp may be used to indicate that the information is a reply to an address translation request Addr_Trans_SN (that is, to indicate that the information is a data return instruction), Addr_Trans_SN may be used to indicate the address translation request sequence number, and PTE may be used to indicate the corresponding first level Contents of page table entries, such as physical addresses and attributes of memory pages.

It should be noted that, after the target preset cache space receives the prefetch request, steps S20 and S40 may be performed in parallel, that is, the information prefetch operation is performed while the physical address is sent to the processor core. Here, "simultaneously" may mean that the execution starts at the same time, or may mean that there is a small time difference between two operations, which is not limited in this embodiment of the present disclosure. Of course, the embodiment of the present disclosure is not limited to this, and steps S20 and S40 can also be performed in a certain order, for example, step S20 is performed first and then step S40 is performed, or step S40 is performed first and then step S20 is performed, which may be determined according to actual needs.

FIG. 12 is a schematic flowchart of another information prefetching method provided by some embodiments of the present disclosure. For example, in some examples, the processor further includes a page table entry cache space and a request cache area, the processor core and the page table entry cache space are set at the same path level, and the processor core is communicatively connected to the page table entry cache space. For example, the page table entry cache space can be set inside the processor core. The request buffer is set at the same path level as the first page table walker. Steps S10-S40 in this embodiment are basically the same as steps S10-S40 shown in FIG. 11, and are not repeated here. In some embodiments, in addition to steps S10-S40, the information prefetching method may further include:

Step S50: In response to the page table entry data required for address translation not existing in the page table entry cache space, use the processor core to generate an address translation request.

Step S60: Using the processor core to send the pending address translation request queue to the request buffer.

For example, in step S50, when a virtual address needs to be translated into a physical address, if there is a miss in the ITLB or DTLB, that is, the page table entry data required for address translation does not exist in the page table entry cache space, then processing The core will generate an address translation request.

For example, in step S60, when the processor includes multiple processor cores, the first page table walker cannot process the address translation requests sent by the multiple processor cores at the same time, so the processor core is used to send the pending request to the request buffer area. address translation request queue. The first page table traverser can sequentially obtain address translation requests from the request buffer and perform corresponding address translation operations.

For example, in some examples, the information prefetching method may further include: in response to the first page table walker being determined to perform an address translation operation, the first page table walker receiving an address translation request forwarded by the second page table walker .

For example, in the case where the first page table walker is selected to perform the address translation operation, the second page table walker may receive the address translation request from the processor core, and then forward the address translation request to the first page table walker, This provides a variety of transmission methods for address translation requests. The first page table traverser performs an address translation operation after receiving the address translation request. For the specific address translation operation process, please refer to the above embodiment, and details are not repeated here.

FIG. 13 is a schematic flowchart of another information prefetching method provided by some embodiments of the present disclosure. As shown in FIG. 13 , in some examples, the information prefetching method may further include steps S70 and S80.

Step S70: The processor core determines the cache space for storing the target information according to the storage state of the first-level cache space and at least one preset cache space, and makes the address translation request carry the cache space for storing the target information in the form of a preset identifier. Level information of cache space;

Step S80: The first page table traverser obtains the preset identifier by parsing, and makes the prefetch request carry the preset identifier.

For example, in step S70, when the virtual address needs to be translated into a physical address and it is determined that the address translation operation is performed by the first page table walker, the processor core generates an address translation request and sends it to the first page table walker. At this time, the processor core determines the cache space for storing the target information according to the storage state of the first-level cache space and the preset cache space, and makes the address translation request carry a preset identifier, and the preset identifier indicates that the target information is stored. The level information of the cache space. For example, a corresponding field may be added to the address translation request to represent the preset identifier, which is used to specify the prefetch buffer space. Thus, the preset identification can be passed to the first page table walker. It should be noted that the cache space for storing target information can be determined according to the number of cache misses per 1000 instructions (Misses Per Thousand Instructions, MPKI). The cache space for storing the target information is determined by factors such as the validity of the data and the hit rate, which is not limited in this embodiment of the present disclosure.

For example, in some examples, if the MPKI value of the first-level cache space is relatively large, the first-level cache space is determined to be used as the prefetch cache space, that is, the target information stored corresponding to the physical address is prefetched and cached to the first level. Level 1 cache space. At this time, the processor core sets the preset flag to 1 and sends it to the page table walker along with the address translation request. For example, in this case, combined with the method for determining the L1I cache and the L1D cache shown in FIG. 10 , the prefetch cache space can be further specifically determined.

For example, in other examples, if the MPKI value of the second-level cache space is relatively large, the second-level cache space is determined to be used as the prefetch cache space, that is, the target information stored corresponding to the physical address is prefetched and cached to Second level cache space. At this time, the processor core sets the preset flag to 2 and sends it to the first page table walker along with the address translation request.

For example, in step S80, when the first page table traverser needs to send a prefetch request to the target preset cache space, the first page table traverser will accompany the prefetch request with the preset identifier obtained by parsing the address translation request It is sent to the target preset cache space, so that the target preset cache space can determine the prefetch cache space according to the preset identifier. For example, a corresponding field may be added to the prefetch request to represent the preset identifier, which is used to specify the prefetch buffer space.

In the above manner, the processor core can determine the cache space used for this prefetch and transmit the preset identifier to the target preset cache space through the first page table traverser, so that the target preset cache space can know this prefetch. Take the buffer space used. Therefore, the prefetching cache space can be dynamically selected, so that the prefetching cache space is not fixed to a certain level of cache space, and can be flexibly set in each prefetching, thereby improving the overall processing efficiency.

FIG. 14 is a schematic flowchart of another information prefetching method provided by some embodiments of the present disclosure. As shown in FIG. 14, in some examples, the information prefetching method may further include steps S90 and S100.

Step S90: In response to selecting the second page table traverser among the first page table traverser and the second page table traverser to perform the address translation operation based on the preset rule, the second page table traverser performs address translation in response to the address translation request operation to get the physical address.

For example, the processor core generates an address translation request in response to the absence of page table entry data required for the address translation in the page table entry cache space, and if it is determined that the address translation operation is performed by the second page table walker The page table walker sends an address translation request. For example, the architecture of the TLB is not limited to the manner of ITLB and DTLB, and any applicable architecture may be adopted, which is not limited by the embodiments of the present disclosure. In the case where it is determined that the address translation operation is performed by the second page table walker, the second page table walker receives the address translation request generated by the processor core, obtains the page table entry data from the memory according to the address translation request, and uses the page table entry The data is address translated to obtain the physical address.

For example, in some examples, the method may also include:

Step S100: In response to the first page table walker being determined to perform the address translation operation, use the second page table walker to forward the address translation request to the first page table walker.

For example, the processor core generates an address translation request in response to the absence of page table entry data required for address translation in the page table entry cache space, and in the case where it is determined that the address translation operation is performed by the first page table walker, can pass The second page table walker forwards the address translation request to the first page table walker. For example, when a virtual address needs to be translated into a physical address, if the page table entry data required for the address translation is not hit in the ITLB or DTLB, an address translation operation is required. At this time, the processor determines one of the first page table traverser and the second page table traverser to perform the address translation operation based on a preset rule. When it is determined that the address translation operation is performed by the first page table walker, the processor core triggers the second page table walker to forward the address translation request to the first page table walker.

It should be noted that, in the embodiments of the present disclosure, the information prefetching method is not limited to the steps described above, but may also include more or less steps, and the execution order of each step is not limited, which can be determined according to actual requirements. Certainly. For a detailed description of the method, reference may be made to the above description of the processor, which will not be repeated here.

At least one embodiment of the present disclosure further provides an electronic device, where the electronic device includes the processor provided by any embodiment of the present disclosure. The electronic device can realize the data/instruction prefetch function while reducing the address translation time delay, effectively reduce the data/instruction read and write operation time delay, and improve the overall performance of the system.

FIG. 15 is a schematic block diagram of an electronic device according to some embodiments of the present disclosure. As shown in FIG. 15 , the electronic device 100 includes a processor 110, and the processor 110 is a processor provided by any embodiment of the present disclosure, for example, the processor shown in FIG. 5 . The electronic device 100 can be used in new application scenarios such as big data, cloud computing, artificial intelligence (AI), etc. Correspondingly, the electronic device 100 can be a big data computing device, a cloud computing device, an artificial intelligence device, etc. This is not limited.

FIG. 16 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. As shown in FIG. 16 , the electronic device 200 is, for example, suitable for implementing the information prefetching method provided by the embodiment of the present disclosure. The electronic device 200 may be a terminal device or a server or the like. It should be noted that the electronic device 200 shown in FIG. 16 is only an example, which does not impose any limitation on the function and scope of use of the embodiments of the present disclosure.

As shown in FIG. 16 , the electronic device 200 may include a processing device (eg, a central processing unit, a graphics processor, etc.) 21 that may be loaded into random access according to a program stored in a read only memory (ROM) 22 or from a storage device 28 Various appropriate operations and processes are executed by the programs in the memory (RAM) 23 . For example, the processing device 21 may be a processor provided by any embodiment of the present disclosure, such as the processor shown in FIG. 5 . In the RAM 23, various programs and data necessary for the operation of the electronic device 200 are also stored. The processing device 21 , the ROM 22 , and the RAM 23 are connected to each other through a bus 24 . An input/output (I/O) interface 25 is also connected to the bus 24 .

Typically, the following devices may be connected to the I/O interface 25: input devices 26 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; including, for example, a liquid crystal display (LCD), speakers, vibration an output device 27 of a computer or the like; a storage device 28 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 29 . The communication means 29 may allow the electronic device 200 to communicate wirelessly or by wire with other electronic devices to exchange data. While FIG. 16 shows electronic device 200 having various means, it should be understood that not all of the illustrated means are required to be implemented or provided, and electronic device 200 may alternatively implement or implement more or less means.

For the detailed description and technical effects of the electronic device 100/200, reference may be made to the above description of the processor and the information prefetching method, which will not be repeated here.

The following points need to be noted:

(1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to obtain new embodiments without conflict.

The above descriptions are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (25)

1. An information prefetching method for a processor, wherein the processor comprises a first-level cache space, a first page table traverser, a second page table traverser, and at least one preset cache space, the The first level cache space and the at least one preset cache space are sequentially connected in communication to form a communication link, the at least one preset cache space includes a target preset cache space, and the first page table traverser is connected to the The target preset cache space is set at the same path level, the first page table traverser is connected in communication with the target preset cache space, and the second page table traverser and the first level cache space are set on the same path level, the second page table traverser is communicatively connected to the first level cache space, and the same path level is physically adjacent or close and can directly perform data interaction and transfer, The method includes: In response to selecting the first page table walker among the first page table walker and the second page table walker to perform an address translation operation to obtain a physical address based on a preset rule, the first page table walker sending a prefetch request to the target preset cache space, wherein the prefetch request includes the physical address; In response to the prefetch request, the target preset cache space performs an information prefetch operation based on the physical address; Alternatively, in response to selecting the second page table walker among the first page table walker and the second page table walker to perform the address translation operation based on the preset rule, the second page A table walker performs the address translation operation in response to an address translation request to obtain the physical address. 2. The method of claim 1, wherein the processor further comprises a processor core, The target preset cache space performs the information prefetching operation based on the physical address, including: determining a prefetch cache space, wherein the prefetch cache space is at least one of the first level cache space and the at least one preset cache space; Based on the physical address, the target preset cache space obtains target information stored corresponding to the physical address; The target preset buffer space sends the target information to the prefetch buffer space. 3. The method of claim 2, wherein determining the prefetch cache space comprises: Acquiring a preset identifier, wherein the preset identifier represents the level information of the cache space, and the preset identifier is stored in the designated storage space or carried in the prefetch request; The prefetch buffer space is determined according to the preset identifier. 4. The method according to claim 3, wherein the first-level cache space comprises a first-level instruction space and a first-level data space, and the level information indicates the first level, Determining the prefetch cache space according to the preset identifier includes: In response to the target information being an instruction type, determining that the prefetch cache space is the first-level instruction space; In response to the target information being a data type, it is determined that the prefetch buffer space is the first-level data space. 5. The method according to claim 2, wherein, based on the physical address, the target preset cache space obtains the target information stored corresponding to the physical address, comprising: Based on the physical address, the target information is acquired from the path from the target preset cache space to the memory in a step-by-step query manner. 6. The method according to claim 2, wherein the target preset buffer space sends the target information to the prefetch buffer space, comprising: The target information is sent to the prefetching buffer space in a step-by-step manner in the path from the target preset buffer space to the prefetching buffer space. 7. The method of claim 2, further comprising: The target preset buffer space sends the physical address to the processor core. 8. The method of claim 7, wherein the target preset cache space sends the physical address to the processor core, comprising: The target preset buffer space sends the physical address to the processor core in a stage-by-stage manner. 9. The method according to claim 3, wherein the processor further comprises a page table entry cache space, the processor core and the page table entry cache space are set at the same path level, and the processor core and the page table entry cache space are set at the same path level. the page table entry cache space communication connection, The method also includes: In response to the page table entry data required for address translation not existing in the page table entry cache space, the address translation request is generated by the processor core. 10. The method of claim 9, further comprising: in response to selecting the first page table walker among the first page table walker and the second page table walker to perform the address translation operation based on the preset rule, the first page table walker The processor performs the address translation operation in response to the address translation request to obtain the physical address. 11. The method of claim 10, wherein the first page table walker performs the address translation operation in response to the address translation request to obtain the physical address, comprising: The first page table traverser receives the address translation request generated by the processor core, obtains page table entry data from memory via the target preset cache space, and uses the page table entry data to perform the address translation. translate operation to obtain the physical address. 12. The method of claim 11, wherein the first page table walker obtains the page table entry data from the memory via the target preset cache space, and uses the page table entry data to perform The address translation operation includes: The first page table traverser obtains the page table entry data in a step-by-step query manner from the path from the target preset cache space to the memory according to the address translation request, and uses the page table entry The data is translated to obtain the physical address. 13. The method of claim 12, further comprising: In response to the first page table walker being determined to perform the address translation operation, the first page table walker receives the address translation request forwarded by the second page table walker. 14. The method according to claim 12, wherein the address translation request includes translation information, and the translation information includes: address translation request serial number, virtual address value to be translated, and initial address of the top-level page table. 15. The method of claim 14, wherein the translation information further comprises a request type identifier, the request type identifier indicating that the target information stored corresponding to the physical address is an instruction type or a data type. 16. The method of claim 9, further comprising: The processor core determines a cache space for storing the target information according to the storage state of the first-level cache space and the at least one preset cache space, and makes the address translation request use the preset identifier way to carry the level information of the cache space used to store the target information; The first page table traverser obtains the preset identifier by parsing, and causes the prefetch request to carry the preset identifier. 17. The method of claim 1, wherein the second page table walker performs the address translation operation to obtain the physical address in response to the address translation request, comprising: The second page table traverser receives the address translation request generated by the processor core, obtains page table entry data from memory according to the address translation request, and uses the page table entry data to perform address translation to obtain the physical address. 18. The method according to claim 10, wherein the preset rule comprises: when the page table entry data required for address translation does not exist in the page table entry cache space, or the page table entry cache space does not exist in the page table entry cache space When the page table level corresponding to the page table entry data required for address translation is greater than a threshold, it is determined that the address translation operation is performed by the first page table walker. 19. The method of claim 9, wherein the processor further comprises a request buffer, the request buffer and the first page table traverser are set at the same path level, the request buffer and the the first page table traverser is communicatively connected, and is communicatively connected with the target preset cache space, The method also includes: Send a queue of pending address translation requests to the request buffer using the processor core. 20. The method of claim 2, wherein the at least one preset cache space includes a second level cache space to an Nth level cache space, N is an integer greater than 2, The Nth level cache space is closest to the memory and farthest from the processor core, and any level cache space from the second level cache space to the Nth level cache space is used as the target preset cache space . 21. The method according to claim 20, wherein the Nth level cache space is a shared type cache space, and the Nth level cache space is used as the target preset cache space. 22. The method according to claim 20, wherein the second level cache space is a private type or a shared type cache space, and the second level cache space is used as the target preset cache space. 23. A processor comprising a first level cache space, a first page table traverser, a second page table traverser and at least one preset cache space, Wherein, the first-level cache space and the at least one preset cache space are sequentially connected in communication to form a communication link, the at least one preset cache space includes a target preset cache space, and the first page table traverses The first page table traverser is connected to the target preset cache space in communication, and the second page table traverser is connected to the first level cache space. Set at the same path level, the second page table traverser is in communication connection with the first level cache space, and the same path level is physically adjacent or close to and can directly perform data interaction and transfer, The first page table walker is configured to: in response to selecting the first page table walker from the first page table walker and the second page table walker based on a preset rule to perform an address translation operation to obtain a physical address, sending a prefetch request to the target preset cache space, wherein the prefetch request includes the physical address; The target preset cache space is configured to: in response to the prefetch request, perform an information prefetch operation based on the physical address; The second page table walker is configured to execute the second page table walker in response to selecting the second page table walker among the first page table walker and the second page table walker based on the preset rule An address translation operation is performed in response to an address translation request to obtain the physical address. 24. The processor of claim 23, wherein the target preset cache space is further configured to determine a prefetch cache space, obtain target information stored corresponding to the physical address based on the physical address, and store the The target information is sent to the prefetch buffer space, The prefetch cache space is at least one of the first level cache space and the at least one preset cache space. 25. An electronic device comprising a processor according to claim 23 or 24.

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