CN114220734B - Method for manufacturing trench gate - Google Patents
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- CN114220734B CN114220734B CN202111514005.2A CN202111514005A CN114220734B CN 114220734 B CN114220734 B CN 114220734B CN 202111514005 A CN202111514005 A CN 202111514005A CN 114220734 B CN114220734 B CN 114220734B
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000007789 sealing Methods 0.000 claims abstract description 3
- 239000007772 electrode material Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a trench gate, which comprises the following steps: step one, forming a groove on the surface of a semiconductor substrate. And secondly, forming a first oxide layer, wherein the top of the groove needs to be kept in an opening state after the first oxide layer is formed. And thirdly, depositing a second dielectric layer, wherein after the second dielectric layer is formed, the top opening of the groove is required to be closed, and a cavity surrounded by the second dielectric layer is formed inside the groove. And fourthly, performing first etching back on the second dielectric layer to remove the exposed second dielectric layer outside the cavity and ensure that the second dielectric layer at the sealing position at the top of the cavity is reserved. And fifthly, performing second etching on the first oxide layer from top to bottom by taking the second dielectric layer at the periphery of the cavity as a mask to form a grid bottom oxide layer. And step six, removing the second dielectric layer. And step seven, growing a gate oxide layer. The invention can simplify the formation process of BTO, thereby reducing the process cost.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a trench gate.
Background
In a MOS transistor, a gate structure includes a gate oxide layer and a polysilicon gate formed on a surface of the gate oxide layer, the polysilicon gate generally covering a channel region and being used to form a channel connecting a source and a drain on the surface of the channel region, a thinner gate oxide layer is generally required in order to provide high controllability of the gate, but a thick gate oxide layer is required for high gate reliability and small miller capacitance. That is, a thinner gate oxide layer is advantageous for controlling the channel opening, but the etching property of the thinner gate oxide layer is reduced and the miller capacitance is increased.
The gate structure comprises a planar gate and a trench gate, and the trench gate can obtain larger current density and smaller on-resistance and is often applied to power devices.
For trench gates, a trench is typically included, a gate oxide layer formed on the inside surface of the trench, including the bottom surface and sides, and a polysilicon gate that completely fills the trench. The trench gate needs to pass through the channel region so that the polysilicon gate laterally covers the channel region so that a channel can be formed in the surface of the channel region laterally covered by the polysilicon gate when the gate is turned on.
As it is clear from the above description, there is a conflict between the gate control and reliability and the requirements of the miller capacitance for the gate oxide thickness, for trench gates, in order to compromise in this conflict. It is often desirable to employ a trench bottom thick oxide (Bottom Thick Oxide, BTO) process in the trench gate, in this specification BTO is referred to as gate bottom oxide, with "thick" in the trench bottom thick oxide meaning that the thickness of the trench bottom thick oxide is thicker than the gate oxide.
Thus, there are two post-oxide layers in the trench gate, one BTO and one gate oxide. The oxide layer between the polysilicon gate and the channel region is a thinner gate oxide layer, so that the gate control force of the manuscript can be ensured. While thick oxide layers, i.e., BTO, are used at the bottom and bottom corners (Corner) where reliability problems are likely to occur to ensure high reliability of the device.
However, the BTO process increases the process flow, which results in an increase in manufacturing costs. How to realize this structure at low cost is very important. There are two main approaches to BTO in the prior art.
The first method is to fill the trench with a High Density Plasma (HDP) Oxide layer (Oxide) and then to implement it by Chemical Mechanical Polishing (CMP) planarization and back-etching techniques, which is very costly.
The existing second method comprises the steps of firstly forming a thicker BTO layer, after the BTO layer is formed, being located on the whole inner side surface and the outer surface of a groove, coating photoresist to completely fill the whole groove, meanwhile filling the photoresist on the surface outside the groove, adjusting the exposure quantity through the thickness difference of the photoresist on the outer surface of the groove and the inner part of the groove, guaranteeing complete exposure of the surface, ensuring underexposure in the groove, keeping the photoresist with required thickness in the groove after development, protecting a thick gate oxide layer formed in advance, namely the BTO layer, removing thick gate oxide in other areas through a wet process through the photoresist remained in the groove, and then forming a thin gate oxide layer of a channel area, namely the gate oxide layer through film formation again. As can be seen from the above, the second method requires one more photolithography and has a relatively high cost. Moreover, due to the coating characteristics of photoresist, this approach is also difficult to achieve for low aspect ratio trench structures.
As shown in fig. 1, which is a schematic diagram of a trench gate with BTO formed by the prior art method, it can be seen that a thicker BTO layer 102 is formed at the bottom of the trench 101, a thinner gate oxide layer 103 is formed on the side of the trench 101 at the top of the BTO layer 102, and finally the polysilicon gate 104 completely fills the trench 101.
As shown in fig. 2, which is a schematic diagram of a photoresist pattern in a second conventional method for forming a trench gate with BTO, it can be seen that the trench 201 has a small aspect ratio, that is, a shallow depth and a wide width, and the photoresist 203 is coated after the formation of the thicker oxide layer 202 for forming the BTO layer, and it can be seen that the filling of the trench 201 by the photoresist 203 is not good due to the small aspect ratio of the trench 201, and a recess as shown by a dummy coil 204 is formed at the top of the trench 201, which is disadvantageous for the subsequent exposure and development of the photoresist 203 and the subsequent wet etching of the oxide layer 202.
Disclosure of Invention
The invention aims to provide a manufacturing method of a trench gate, which can simplify the formation process of a gate bottom oxide layer (BTO) so as to reduce the process cost.
In order to solve the technical problems, the manufacturing method of the trench gate provided by the invention comprises the following steps:
Step one, forming a groove on the surface of a semiconductor substrate.
And step two, forming a first oxide layer on the bottom surface and the side surface of the groove and the surface outside the groove.
The growth rate of the first oxide layer at the top angle of the groove is larger than that at the side surface of the groove, and the top of the groove needs to be kept in an opening state after the first oxide layer is formed.
And thirdly, depositing a second dielectric layer on the surface of the first oxide layer.
The growth rate of the second dielectric layer at the top angle of the groove is larger than that of the second dielectric layer at the side face of the groove, the top opening of the groove is required to be closed after the second dielectric layer is formed, and a cavity surrounded by the second dielectric layer is formed inside the groove.
And fourthly, carrying out first etching back on the second dielectric layer.
And removing the exposed second dielectric layer outside the cavity by the first etching back, and ensuring that the second dielectric layer at the sealing position at the top of the cavity is reserved, so that the cavity is still surrounded and sealed by the second dielectric layer.
And fifthly, performing second etching on the first oxide layer, wherein the first oxide layer only remains on the bottom surface and the bottom area of the side surface of the groove after the second etching, and forms a grid bottom oxide layer, and the second etching uses the second dielectric layer at the periphery of the cavity as a mask to realize etching of the first oxide layer from top to bottom.
And step six, removing the second dielectric layer.
And step seven, growing a gate oxide layer, wherein the gate oxide layer is positioned on the side surface of the groove at the top of the gate bottom oxide layer, and the thickness of the gate oxide layer is smaller than that of the gate bottom oxide layer.
Further improvement is that the method further comprises the following steps:
And step eight, filling a gate electrode material layer in the groove.
The further improvement is that the gate electrode material layer is a polysilicon gate.
Further improvement is that the semiconductor substrate is a silicon substrate.
The first oxide layer is silicon oxide, and the gate oxide layer is silicon oxide.
The further improvement is that the process of forming the first oxide layer in the second step adopts a thermal oxidation process or a chemical vapor deposition process or a thermal oxidation process and a chemical vapor deposition process.
In a further improvement, the gate oxide layer is formed by adopting a thermal oxidation process in the step seven.
In a further improvement, in the second step, after the first oxide layer is formed, the width of the top opening of the trench is
A further improvement is that after the deposition in the third step is completed, the thickness of the second dielectric layer on the surface of the first oxide layer outside the trench is
A further improvement is that the material of the second dielectric layer comprises silicon nitride.
The further improvement is that in the fourth step, dry etching is adopted for the first etching.
In the sixth step, the second dielectric layer is removed by wet etching.
In a further improvement, in the fifth step, wet etching is adopted for the second etching.
The further improvement is that the trench gate is a gate structure of a MOS transistor, and the method further comprises the following steps:
And step nine, forming a channel region, wherein the depth of the channel region is smaller than that of the gate oxide layer, the gate electrode material layer covers the channel region through the side face of the gate oxide layer, the surface of the channel region covered by the side face of the gate electrode material layer is used for forming a channel, the semiconductor substrate is doped with a first conductive type, and the channel region is doped with a second conductive type.
And step ten, forming a source region with the first conductive type heavily doping on the surface of the channel region.
And eleventh, forming a first conductive type heavily doped drain region on the back surface of the semiconductor substrate.
The MOS transistor is an NMOS transistor, the first conduction type is N-type, the second conduction type is P-type, the MOS transistor is a PMOS transistor, the first conduction type is P-type, and the second conduction type is N-type.
According to the invention, by utilizing the characteristics that the growth rate at the top angle of the groove is larger than the growth rate of the side face of the groove when the dielectric layer is filled in the groove and the seal is generated at the top of the groove along with the increase of the thickness of the dielectric layer, after the first oxide layer which does not seal the top of the groove is formed, a layer of second dielectric layer is formed to seal the top of the groove, a cavity surrounded by the second dielectric layer is formed inside the groove, then the second dielectric layer on the surface of the first oxide layer outside the cavity can be removed by back etching the second dielectric layer, so that the exposed first oxide layer can be etched from top to bottom by taking the remaining second dielectric layer which surrounds the cavity as a mask, namely the second etching is performed from top to bottom, so that the needed gate bottom oxide layer can be obtained.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic illustration of a trench gate with BTO formed by a prior art method;
FIG. 2 is a schematic illustration of a photoresist pattern in a second prior art method of forming a trench gate with BTO;
FIG. 3 is a flow chart of a method of fabricating a trench gate in accordance with an embodiment of the present invention;
fig. 4A to 4G are schematic structural views of a device according to a method for manufacturing a trench gate according to an embodiment of the present invention.
Detailed Description
Fig. 3 is a flowchart of a method for manufacturing a trench gate according to an embodiment of the present invention, and fig. 4A to 4G are schematic structural diagrams of a device according to a method for manufacturing a trench gate according to an embodiment of the present invention, where the method for manufacturing a trench gate according to an embodiment of the present invention includes the following steps:
step one, as shown in fig. 4A, a trench 302 is formed in the surface of a semiconductor substrate 301.
In the method of the embodiment of the present invention, the semiconductor substrate 301 is a silicon substrate.
In the second step, as shown in fig. 4A, a first oxide layer 303 is formed on the bottom surface and the side surface of the trench 302 and the surface outside the trench 302.
The growth rate of the first oxide layer 303 at the top corner of the trench 302 is greater than the growth rate at the side of the trench 302, and the first oxide layer 303 needs to be formed so that the top of the trench 302 is kept in an open state.
In the method of the embodiment of the present invention, the first oxide layer 303 is silicon oxide.
The first oxide layer 303 is formed by a thermal oxidation process, a chemical vapor deposition process, or a combination of a thermal oxidation process and a chemical vapor deposition process.
Preferably, after the first oxide layer 303 is formed, the width of the top opening of the trench 302 is A typical value is. The thicker the first oxide layer 303 is, the smaller the top opening of the trench 302 is.
Step three, as shown in fig. 4B, a second dielectric layer 304 is deposited on the surface of the first oxide layer 303.
The growth rate of the second dielectric layer 304 at the top corner of the trench 302 is greater than the growth rate at the side of the trench 302, the second dielectric layer 304 needs to be formed to close the top opening of the trench 302, and the second dielectric layer 304 forms a cavity 305 surrounded by the second dielectric layer 304 inside the trench 302.
In the method of the embodiment of the present invention, after the deposition in the third step is completed, the thickness of the second dielectric layer 304 on the surface of the first oxide layer 303 outside the trench 302 isA typical value isTo ensure that the top opening of the trench 302 is closed.
The material of the second dielectric layer 304 includes silicon nitride.
Step four, as shown in fig. 4C, the second dielectric layer 304 is etched back for the first time.
The first etching back removes the second dielectric layer 304 exposed outside the cavity 305 and ensures that the second dielectric layer 304 at the top seal of the cavity 305 remains, so that the cavity 305 is still enclosed and sealed by the second dielectric layer 304.
In the method of the embodiment of the invention, the first back etching in the step four adopts dry etching.
Step five, as shown in fig. 4D, a second etching is performed on the first oxide layer 303, where after the second etching, the first oxide layer 303 is only remained on the bottom surface and the bottom area of the side surface of the trench 302, and a gate bottom oxide layer 303a is formed, and the second etching uses the second dielectric layer 304 on the peripheral side of the cavity 305 as a mask to implement etching of the first oxide layer 303 from top to bottom.
In the method of the embodiment of the invention, wet etching is adopted for the second etching.
Step six, as shown in fig. 4E, the second dielectric layer 304 is removed.
In the method of the embodiment of the present invention, the second dielectric layer 304 is removed by wet etching.
Step seven, as shown in fig. 4F, a gate oxide layer 306 is grown, where the gate oxide layer 306 is located on the side surface of the trench 302 on top of the gate bottom oxide layer 303a, and the thickness of the gate oxide layer 306 is smaller than the thickness of the gate bottom oxide layer 303 a.
In the method of the embodiment of the present invention, the gate oxide layer 306 is silicon oxide.
Preferably, the gate oxide layer 306 is formed using a thermal oxidation process.
Before the gate oxide 306 is performed, a sacrificial oxide layer is further formed, and then the sacrificial oxide layer is removed to eliminate defects on the sides of the trench 302.
Step eight, as shown in fig. 4F, a gate electrode material layer 307 is filled in the trench 302.
In the method of the embodiment of the present invention, the gate electrode material layer 307 is a polysilicon gate.
The trench gate is a gate structure of the MOS transistor, and further comprises the following steps:
step nine, as shown in fig. 4G, a channel region 308 is formed, the depth of the channel region 308 is smaller than the depth of the gate oxide 306, the gate electrode material layer 307 laterally covers the channel region 308 through the gate oxide 306, the surface of the channel region 308 laterally covered by the gate electrode material layer 307 is used to form a channel, the semiconductor substrate 301 is doped with a first conductivity type, and the channel region 308 is doped with a second conductivity type.
Step ten, as shown in fig. 4G, a source region 309 heavily doped with the first conductivity type is formed on the surface of the channel region 308.
And step eleven, forming a first conductive type heavily doped drain region on the back surface of the semiconductor substrate 301.
In the embodiment of the invention, the MOS transistor is an NMOS transistor, the first conduction type is N type, and the second conduction type is P type. In other embodiments, the MOS transistor may be a PMOS transistor, the first conductive type may be a P-type, and the second conductive type may be an N-type.
According to the embodiment of the invention, by utilizing the characteristics that the growth rate at the top angle of the groove 302 is larger than the growth rate of the side face of the groove 302 when the dielectric layer is filled in the groove 302 and the seal is generated at the top of the groove 302 along with the increase of the thickness of the dielectric layer, after the first oxide layer 303 which does not seal the top of the groove 302 is formed, a layer of second dielectric layer 304 is formed to seal the top of the groove 302 and form the cavity 305 surrounded by the second dielectric layer 304 inside the groove 302, then the second dielectric layer 304 is etched back to remove the second dielectric layer 304 on the surface of the first oxide layer 303 outside the cavity 305, so that the exposed first oxide layer 303 can be etched from top to bottom by using the remaining second dielectric layer 304 which surrounds the cavity 305 as a mask, namely the second etch from top to bottom is realized, and the needed gate bottom oxide layer 303a can be obtained.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. The manufacturing method of the trench gate is characterized by comprising the following steps:
step one, forming a groove on the surface of a semiconductor substrate;
Step two, forming a first oxide layer on the bottom surface and the side surface of the groove and the surface outside the groove;
The growth rate of the first oxide layer at the top angle of the groove is larger than that at the side surface of the groove, and the top of the groove needs to be kept in an opening state after the first oxide layer is formed;
Step three, depositing a second dielectric layer on the surface of the first oxide layer;
the growth rate of the second dielectric layer at the top angle of the groove is larger than that of the second dielectric layer at the side surface of the groove, the top opening of the groove is required to be closed after the second dielectric layer is formed, and a cavity surrounded by the second dielectric layer is formed inside the groove;
fourthly, carrying out first back etching on the second dielectric layer;
The first etching back removes the exposed second dielectric layer outside the cavity and ensures that the second dielectric layer at the sealing position at the top of the cavity is reserved, so that the cavity is still surrounded and sealed by the second dielectric layer;
step five, performing second etching on the first oxide layer, wherein the first oxide layer only remains on the bottom surface of the groove and the bottom area of the side surface after the second etching and forms a grid bottom oxide layer, and the second etching uses the second dielectric layer at the periphery of the cavity as a mask to realize etching of the first oxide layer from top to bottom;
step six, removing the second dielectric layer;
And step seven, growing a gate oxide layer, wherein the gate oxide layer is positioned on the side surface of the groove at the top of the gate bottom oxide layer, and the thickness of the gate oxide layer is smaller than that of the gate bottom oxide layer.
2. The method of fabricating a trench gate as defined in claim 1 further comprising the steps of:
And step eight, filling a gate electrode material layer in the groove.
3. The method of manufacturing a trench gate as set forth in claim 2, wherein the gate electrode material layer is a polysilicon gate.
4. The method of manufacturing a trench gate according to claim 1, wherein the semiconductor substrate is a silicon substrate.
5. The method of manufacturing a trench gate as claimed in claim 4, wherein the first oxide layer is silicon oxide and the gate oxide layer is silicon oxide.
6. The method of manufacturing a trench gate as claimed in claim 5, wherein the second step of forming the first oxide layer is performed by a thermal oxidation process, a chemical vapor deposition process, or a combination of a thermal oxidation process and a chemical vapor deposition process.
7. The method of manufacturing a trench gate as claimed in claim 5, wherein the gate oxide layer is formed by a thermal oxidation process in step seven.
8. The method of manufacturing a trench gate according to claim 1, wherein in the second step, after the first oxide layer is formed, a width of a top opening of the trench is
9. The method of manufacturing a trench gate as claimed in claim 8, wherein the second dielectric layer on the surface of the first oxide layer outside the trench has a thickness of
10. The method of manufacturing a trench gate of claim 1 wherein the material of the second dielectric layer comprises silicon nitride.
11. The method of manufacturing a trench gate as claimed in claim 10, wherein the first etching back in the fourth step is dry etching.
12. The method of manufacturing a trench gate as claimed in claim 10, wherein in step six, the second dielectric layer is removed by wet etching.
13. The method of manufacturing a trench gate as claimed in claim 1, wherein in the fifth step, the second etching is wet etching.
14. The method of manufacturing a trench gate according to claim 2, wherein the trench gate is a gate structure of a MOS transistor, further comprising the steps of:
forming a channel region, wherein the depth of the channel region is smaller than that of the gate oxide layer, the gate electrode material layer covers the channel region through the side surface of the gate oxide layer, and the surface of the channel region covered by the side surface of the gate electrode material layer is used for forming a channel;
step ten, forming a source region with heavy doping of the first conduction type on the surface of the channel region;
And eleventh, forming a first conductive type heavily doped drain region on the back surface of the semiconductor substrate.
15. The method of manufacturing a trench gate as set forth in claim 14, wherein the MOS transistor is an NMOS transistor, the first conductivity type is N-type, the second conductivity type is P-type, the MOS transistor is a PMOS transistor, the first conductivity type is P-type, and the second conductivity type is N-type.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101341590A (en) * | 2005-12-22 | 2009-01-07 | Nxp股份有限公司 | Method of manufacturing a semiconductor device |
| CN103065951A (en) * | 2011-10-21 | 2013-04-24 | 上海华虹Nec电子有限公司 | Trench gate formation method |
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| JP2004055812A (en) * | 2002-07-19 | 2004-02-19 | Renesas Technology Corp | Semiconductor device |
| JP4041785B2 (en) * | 2003-09-26 | 2008-01-30 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
| CN109216449B (en) * | 2017-06-30 | 2021-07-30 | 帅群微电子股份有限公司 | Trench type power semiconductor device and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101341590A (en) * | 2005-12-22 | 2009-01-07 | Nxp股份有限公司 | Method of manufacturing a semiconductor device |
| CN103065951A (en) * | 2011-10-21 | 2013-04-24 | 上海华虹Nec电子有限公司 | Trench gate formation method |
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