CN114217193B - NAND Gate Tree Structure - Google Patents
NAND Gate Tree Structure Download PDFInfo
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- CN114217193B CN114217193B CN202010923207.1A CN202010923207A CN114217193B CN 114217193 B CN114217193 B CN 114217193B CN 202010923207 A CN202010923207 A CN 202010923207A CN 114217193 B CN114217193 B CN 114217193B
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- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000012360 testing method Methods 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 238000012795 verification Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
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Abstract
本公开提供了一种与非门树结构，与非门树结构包括：多个与非门；其中，第一个与非门的第一输入端连接第一输入信号，第一个与非门的输出端作为整个与非门树结构的输出，第一个与非门的第二输入端连接第二个与非门的输出端。本公开的优点在于，本公开为了实现无环形振荡器的面积增加，因此，将输入信号分为与非门树测定用和环形振荡器用两种，两种情况下，均采用包含在输入输出端子内部的与非门电路。两种情况下的输出结果都可以得到。因此，本公开不必扩大的产品的尺寸，利于半导体器件的小型化及成本抑制。
The present disclosure provides a NAND gate tree structure, the NAND gate tree structure includes: a plurality of NAND gates; wherein the first input end of the first NAND gate is connected to the first input signal, the output end of the first NAND gate is used as the output of the entire NAND gate tree structure, and the second input end of the first NAND gate is connected to the output end of the second NAND gate. The advantage of the present disclosure is that in order to achieve the area increase without the ring oscillator, the present disclosure divides the input signal into two types: for NAND gate tree measurement and for the ring oscillator. In both cases, the NAND gate circuit contained in the input and output terminals is used. The output results in both cases can be obtained. Therefore, the present disclosure does not need to enlarge the size of the product, which is conducive to the miniaturization and cost control of semiconductor devices.
Description
Technical Field
The disclosure relates to the technical field of semiconductor manufacturing, in particular to a NAND tree structure and a testing method using the NAND tree structure.
Background
In the case of the ultra-micro semiconductor process, since ac performance is important, it is often necessary to use a ring oscillator circuit for measurement and management, because the dc parameter values and ac performance of the ultra-micro process and the semiconductor device are not equal. However, in order to test the ac performance, it is sometimes necessary to leave room for measurement circuitry in the product, with the remaining pads. Therefore, the size of the product thus enlarged is disadvantageous in miniaturization and cost reduction of the semiconductor device.
Disclosure of Invention
The object of the present disclosure is to provide a nand gate tree structure, which aims at overcoming the defects of the prior art, and the object is achieved by the following technical scheme.
A first aspect of the present disclosure proposes a nand gate tree structure, comprising:
a plurality of nand gates, wherein,
The first input end of the first NAND gate is connected with a first input signal, the output end of the first NAND gate is used as the output of the whole NAND gate tree structure, and the second input end of the first NAND gate is connected with the output end of the second NAND gate.
A second aspect of the present disclosure proposes a nand gate tree structure, comprising:
a plurality of NAND gates;
the first input end of the first NAND gate is connected with a first input signal, the output end of the first NAND gate is used as the output of the whole NAND gate tree structure, the second input end of the first NAND gate is connected with the output end of the first delay unit, and the input end of the delay unit is connected with the output end of the second NAND gate.
A third aspect of the present disclosure proposes a semiconductor device group comprising a nand gate tree structure according to the first or second aspect.
The present disclosure has an advantage in that in order to achieve an increase in area without a ring oscillator, an input signal is divided into two types, i.e., a NAND tree measurement type and a ring oscillator type, and in both cases, a NAND circuit included in an input/output terminal is used. The output results in both cases can be obtained. Therefore, the present disclosure does not have to expand the size of the product, facilitating miniaturization and cost reduction of the semiconductor device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate and explain the present disclosure, and together with the description serve to explain the present disclosure. In the drawings:
fig. 1 is a schematic diagram of a nand gate tree structure for verifying a connection state of an input signal terminal in a first embodiment of the present disclosure;
FIG. 2 is a schematic diagram showing the output variation of an input signal during measurement;
FIG. 3 is a schematic diagram of a logic circuit within a product employing a standard NAND tree structure in a second embodiment of the present disclosure;
Fig. 4 is an enlarged schematic diagram of a delay cell structure employed in a second embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a NAND tree verification scenario.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
In the prior art, ring oscillators are used to measure the ac performance of semiconductor devices. This type of ring oscillator is formed inside the product or in a void around the product. The ac performance measured by the ring oscillator thus formed is used as an index of the management process after performing a work conforming to the product performance. Also in order to measure these ring oscillators, additional space is required, as are additional pads.
As the process is refined, the alternating current (AC Performance) characteristics of the transistors measured by dicing lanes (dicing Lane) are not representative of product Performance issues. Therefore, it occurs when a special test circuit is added inside the product for evaluation, and in this case, a reserved space is required according to the addition inside the product. In particular, the test circuit thus implemented can be tested at the wafer level evaluation stage, with a delay in the feedback time.
Ring oscillators that manage the process are formed on the extra area and are electrically connected on the input-output pads. The same input-output pad is an extra pad required for connecting a ring oscillator formed in an extra area or an extra area required for connecting an existing input-output port. Forming such additional areas and additional pads has the problem of increasing the product area. For all semiconductor memory products, the input-output pads have NAND gate (NAND) circuits inside.
Fig. 1 is a first embodiment of the present disclosure, in order to verify a NAND gate Tree (NAND Tree) structure of an input signal terminal connection state, the present disclosure connects a NAND circuit (NAND gate circuit) built on a product pad with the NAND circuit, and verifies an input output pad design using the NAND gate Tree structure. In fig. 1, 20 nand gates are included in total. However, those skilled in the art will appreciate that the inventive concepts of the present disclosure are not limited to 20 nand gates, and that a greater or lesser number of nand gate structures are possible to implement the present disclosure. In fig. 1, a first INPUT terminal of the uppermost first nand gate is connected to the INPUT signal input_00, and an output terminal thereof is used as an output of the entire nand gate tree structure, and a second INPUT terminal of the first nand gate is connected to an output terminal of a second nand gate below. The first INPUT end of the second NAND gate is connected with the INPUT signal INPUT_01, the output end of the second NAND gate is connected with the second INPUT end of the first NAND gate, and the second INPUT end of the second NAND gate is connected with the output end of the third NAND gate. And so on, the connection modes of the 2 nd to 19 th NAND gates are the same, and the first INPUT ends are respectively connected with the INPUT signals INPUT_01 to INPUT_18. The first INPUT end and the second INPUT end of the 20 th NAND gate are connected with an INPUT signal INPUT_19, and the output end of the 20 th NAND gate is connected with the second INPUT end of the 19 th NAND gate.
Thus, in the first embodiment, the NAND circuit confirms the connection state of the input-output Pads (I/O Pads), and the connected NAND circuits constitute a NAND tree, and the output signal is measured from the variation of the input signal. Thus, the present disclosure connects the NAND circuits inside the input-output pads and allows the process to be monitored directly inside the product when it is used in a process-management ring oscillator. In particular, the measuring circuit can be realized without requiring additional areas and additional pads and without requiring an increase in area.
Fig. 2 shows the output variation of the input signal during measurement in the first embodiment. Wherein the first left column represents the pad INPUT/output signal, OUT represents the output signal, INPUT_00 through INPUT_19 represent the INPUT signal, letter L represents the low level, letter H represents the high level, and 1 and 0 represent the values of the INPUT signals. In this way, the NAND tree loop can verify the performance of the product. The NAND tree loop thus constructed is not completed by the input/output pad connection verification in the simple wafer level test, but is in the dc test stage before the wafer level test, so that it is desired to verify ac characteristics in advance.
Fig. 3 is a logic circuit inside a product employing a standard NAND Tree structure. In fig. 3, 20 nand gates are included in total. However, those skilled in the art will appreciate that the inventive concepts of the present disclosure are not limited to 20 nand gates, and that a greater or lesser number of nand gate structures are possible to implement the present disclosure. In fig. 3, a first INPUT terminal of the uppermost first nand gate is connected to the INPUT signal input_00, an output terminal thereof is used as an output of the entire nand gate tree structure, and a second INPUT terminal of the first nand gate is connected to an output terminal of the first delay unit, and an INPUT terminal of the first delay unit is connected to an output terminal of the second nand gate. The first INPUT end of the second NAND gate is connected with the INPUT signal INPUT_01, the output end of the second NAND gate is used as the INPUT end connected with the first delay unit, the second INPUT end of the second NAND gate is connected with the output end of the second delay unit, and the INPUT end of the second delay unit is connected with the output end of the third NAND gate. And so on, the connection modes of the 2 nd to 19 th NAND gates are the same, and the first INPUT ends are respectively connected with the INPUT signals INPUT_01 to INPUT_18. The first INPUT end and the second INPUT end of the 20 th NAND gate are connected with an INPUT signal INPUT_19, and the output end of the 20 th NAND gate is connected with the 19 th delay unit.
In a second embodiment, the result of the formulation of the connected ring oscillator occurs. In this way, when the NAND inside the input terminal and the logic inside the product are woven to form the NAND tree structure, NAND tree verification can be performed. Meanwhile, when the input signals of all the input ends are 1, the ring oscillator can be used for starting and testing the alternating current performance.
As shown in fig. 4, in the second embodiment of the present disclosure, a schematic enlarged view of the delay cell structure is used. As shown in fig. 4, the delay cell employed in the present disclosure includes two series-connected not gates/nand gates/nor gates. A resistor and capacitor are connected between the first and second nor/nor gates. One end of the resistor is connected with the output end of the first NOT gate/NAND gate/NOR gate, the other end of the resistor is connected with the input end of the second NOT gate/NAND gate/NOR gate, one end of the first capacitor is connected with the output end of the first NOT gate/NAND gate/NOR gate, the other end of the first capacitor is grounded, VDD or other signal nodes, one end of the second capacitor is connected with the input end of the second NOT gate/NAND gate/NOR gate, and the other end of the second capacitor is grounded, VDD or other signal nodes. τ d1 and τ d2 represent the delay times of the nand gate and the delay unit, respectively.
As shown in fig. 5, that is, in the NAND tree verification, if the input signals of the input and output terminals are sequentially exchanged by 1 and 0, the exchanged values are sequentially detected based on the signals of the output terminals, and if a ring oscillator for measuring ac performance is used, the NAND circuit measures the frequency of the output signals of the output terminals based on the inverter circuit operation if all the input signals are set to 1. When the output frequency of the output terminal is high, ac performance of the management process can be evaluated by measuring the output frequency by a periodic method. In FIG. 5, OUTPUT is an OUTPUT signal of the NAND tree structure, and INPUT_x-1, INPUT_x, and INPUT_x+1 are INPUT signals.
In order to achieve an increase in area without a ring oscillator, the present disclosure divides an input signal into two types, namely, a NAND tree measurement and a ring oscillator, and in both cases, uses a NAND circuit included in an existing input/output terminal. The output results in both cases can be obtained. Therefore, the present disclosure does not have to expand the size of the product, facilitating miniaturization and cost reduction of the semiconductor device.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (6)
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6105153A (en) * | 1995-09-28 | 2000-08-15 | Nec Corporation | Semiconductor integrated circuit and its evaluating method |
| CN105811931A (en) * | 2015-01-20 | 2016-07-27 | 联发科技（新加坡）私人有限公司 | Tunable delay circuit and operating method thereof |
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| US4251884A (en) * | 1979-02-09 | 1981-02-17 | Bell Telephone Laboratories, Incorporated | Parity circuits |
| JPS60123775A (en) * | 1983-12-08 | 1985-07-02 | Nec Corp | Lsi circuit |
| JPS639311A (en) * | 1986-06-30 | 1988-01-16 | Nec Corp | Ring oscillator circuit |
| JP3052798B2 (en) * | 1995-08-16 | 2000-06-19 | 日本電気株式会社 | Semiconductor device |
| JP2872138B2 (en) * | 1996-08-29 | 1999-03-17 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor integrated circuit |
| JP4034886B2 (en) * | 1998-10-13 | 2008-01-16 | 富士通株式会社 | Semiconductor device |
| JP2001230661A (en) * | 2000-02-15 | 2001-08-24 | Matsushita Electric Ind Co Ltd | Driver circuit, i/o cell and layout designing method |
| US7710208B2 (en) * | 2007-04-18 | 2010-05-04 | Vns Portfolio Llc | Multi-speed ring oscillator |
| CN102664623B (en) * | 2012-05-09 | 2015-02-18 | 龙芯中科技术有限公司 | Digital delay device |
| JP2016010004A (en) * | 2014-06-24 | 2016-01-18 | マイクロン テクノロジー， インク． | Ring oscillator and semiconductor including the same |
| US10156605B2 (en) * | 2014-08-29 | 2018-12-18 | Semitronix Corporation | Addressable ring oscillator test chip |
| CN208272951U (en) * | 2018-06-27 | 2018-12-21 | 无锡麟力科技有限公司 | A kind of enabled shutdown sequential logical circuit for PWM type synchronous pressure-boosting converter |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6105153A (en) * | 1995-09-28 | 2000-08-15 | Nec Corporation | Semiconductor integrated circuit and its evaluating method |
| CN105811931A (en) * | 2015-01-20 | 2016-07-27 | 联发科技（新加坡）私人有限公司 | Tunable delay circuit and operating method thereof |
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