CN114203647A - VDMOS ceramic packaging structure - Google Patents
VDMOS ceramic packaging structure Download PDFInfo
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- CN114203647A CN114203647A CN202111448058.9A CN202111448058A CN114203647A CN 114203647 A CN114203647 A CN 114203647A CN 202111448058 A CN202111448058 A CN 202111448058A CN 114203647 A CN114203647 A CN 114203647A
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- 239000000919 ceramic Substances 0.000 title claims abstract description 113
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 229910000679 solder Inorganic materials 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 20
- 238000003466 welding Methods 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910000833 kovar Inorganic materials 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 238000005245 sintering Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 238000012858 packaging process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
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Abstract
本发明公开了一种VDMOS陶瓷封装结构，包括：第一金属框架、第二金属框架、陶瓷外壳、导热一体式盖板和VDMOS芯片；其中，第一金属框架包括第一支撑段、第一上横段和第一下横段；第二金属框架包括第二支撑段、第二上横段和第二下横段。本发明在保证器件优良的电学和散热性能的同时，大大提高在高温、高湿度等恶劣环境下的可靠性。
The invention discloses a VDMOS ceramic packaging structure, comprising: a first metal frame, a second metal frame, a ceramic shell, a heat-conducting integrated cover plate and a VDMOS chip; wherein, the first metal frame includes a first support section, a first upper A transverse section and a first lower transverse section; the second metal frame includes a second supporting section, a second upper transverse section and a second lower transverse section. The invention greatly improves the reliability in harsh environments such as high temperature and high humidity while ensuring the excellent electrical and heat dissipation performance of the device.
Description
技术领域technical field
本发明属于半导体封装技术领域，尤其涉及一种VDMOS陶瓷封装结构。The invention belongs to the technical field of semiconductor packaging, and in particular relates to a VDMOS ceramic packaging structure.
背景技术Background technique
VDMOS大功率器件有工作电流大、功耗大等特点，要求器件封装的导通电阻小、电流承载能力强、散热性能优良，因此通常的解决方案是采用框架类塑封封装工艺。但在高温、高湿度等一些恶劣环境下，塑封器件的可靠性不能满足使用要求，而陶瓷类封装却在相关方面有很强的优势。VDMOS high-power devices have the characteristics of large operating current and high power consumption, requiring small on-resistance of the device package, strong current carrying capacity, and excellent heat dissipation performance. Therefore, the usual solution is to use frame-type plastic packaging technology. However, in some harsh environments such as high temperature and high humidity, the reliability of plastic packaged devices cannot meet the requirements of use, while ceramic packages have strong advantages in related aspects.
但是现有的陶瓷封装结构采用印刷布线、层压烧结的工艺。封装内的布线层很薄，不能满足大电流承载要求，常会出线布线层熔化的失效情况；并且陶瓷外壳的布线为W/Mo等电阻率很高的材料，路径的导通电阻较高，将对VDMOS器件性能造成很大影响。陶瓷封装的以上缺点制约着其在大电流类器件方面的应用。However, the existing ceramic packaging structure adopts the process of printed wiring and lamination and sintering. The wiring layer in the package is very thin and cannot meet the high current carrying requirements, and the wiring layer of the outgoing wire is often melted. It has a great impact on the performance of VDMOS devices. The above shortcomings of ceramic packaging restrict its application in high-current devices.
目前，塑料封装和陶瓷封装都无法同时兼顾可靠性与性能两方面，这严重影响着VDMOS器件在高可靠领域的应用。At present, neither plastic package nor ceramic package can take into account both reliability and performance, which seriously affects the application of VDMOS devices in the field of high reliability.
发明内容SUMMARY OF THE INVENTION
本发明解决的技术问题是：克服现有技术的不足，提供了一种VDMOS陶瓷封装结构，在保证器件优良的电学和散热性能的同时，大大提高在高温、高湿度等恶劣环境下的可靠性。The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, a VDMOS ceramic packaging structure is provided, which greatly improves the reliability in harsh environments such as high temperature and high humidity while ensuring the excellent electrical and heat dissipation performance of the device. .
本发明目的通过以下技术方案予以实现：一种VDMOS陶瓷封装结构，包括：第一金属框架、第二金属框架、陶瓷外壳、导热一体式盖板和VDMOS芯片；其中，第一金属框架包括第一支撑段、第一上横段和第一下横段；其中，第一上横段的一端和第一支撑段的顶端相连接；第一下横段的一端和第一支撑段的中部相连接；第一上横段的另一端穿过陶瓷外壳的一个侧壁与VDMOS芯片的一端的上部相连接；第一下横段的另一端穿过陶瓷外壳的一个侧壁与VDMOS芯片的一端的下部相连接；第二金属框架包括第二支撑段、第二上横段和第二下横段；其中，第二上横段的一端和第二支撑段的顶端相连接；第二下横段的一端和第二支撑段的中部相连接；第二上横段的另一端穿过陶瓷外壳的另一个侧壁与VDMOS芯片的另一端的上部相连接；第二下横段的另一端穿过陶瓷外壳的另一个侧壁与VDMOS芯片的另一端的下部相连接；所述导热一体式盖板设置于所述陶瓷外壳的开口处，并且所述导热一体式盖板的下端与VDMOS芯片的上表面相连接。The object of the present invention is achieved through the following technical solutions: a VDMOS ceramic packaging structure, comprising: a first metal frame, a second metal frame, a ceramic shell, a thermally conductive integrated cover plate and a VDMOS chip; wherein, the first metal frame includes a first metal frame. Supporting segment, first upper transverse segment and first lower transverse segment; wherein, one end of the first upper transverse segment is connected with the top end of the first supporting segment; one end of the first lower transverse segment is connected with the middle of the first supporting segment ; The other end of the first upper cross section is connected to the upper part of one end of the VDMOS chip through a side wall of the ceramic shell; the other end of the first lower cross section passes through a side wall of the ceramic shell and the lower part of one end of the VDMOS chip The second metal frame includes a second support section, a second upper transverse section and a second lower transverse section; wherein, one end of the second upper transverse section is connected with the top end of the second supporting section; One end is connected to the middle of the second support section; the other end of the second upper cross section is connected to the upper part of the other end of the VDMOS chip through the other side wall of the ceramic shell; the other end of the second lower cross section passes through the ceramic The other side wall of the casing is connected to the lower part of the other end of the VDMOS chip; the thermally conductive integrated cover plate is arranged at the opening of the ceramic casing, and the lower end of the thermally conductive integrated cover plate is connected to the upper surface of the VDMOS chip connected.
上述VDMOS陶瓷封装结构中，第一上横段的另一端穿过陶瓷外壳的一个侧壁通过焊点与VDMOS芯片的一端的上部相连接；第一下横段的另一端穿过陶瓷外壳的一个侧壁通过焊点与VDMOS芯片的一端的下部相连接；第二上横段的另一端穿过陶瓷外壳的另一个侧壁通过焊点与VDMOS芯片的另一端的上部相连接；第二下横段的另一端穿过陶瓷外壳的另一个侧壁通过焊点与VDMOS芯片的另一端的下部相连接。In the above-mentioned VDMOS ceramic package structure, the other end of the first upper transverse section passes through one side wall of the ceramic shell and is connected to the upper part of one end of the VDMOS chip through a solder joint; the other end of the first lower transverse section passes through one of the ceramic shells. The side wall is connected with the lower part of one end of the VDMOS chip through the solder joint; the other end of the second upper cross section passes through the other side wall of the ceramic shell and is connected with the upper part of the other end of the VDMOS chip through the solder joint; The other end of the segment is connected to the lower part of the other end of the VDMOS chip through the other side wall of the ceramic shell through a solder joint.
上述VDMOS陶瓷封装结构中，所述导热一体式盖板通过粘接胶设置于所述陶瓷外壳的开口处，并且所述导热一体式盖板的下端通过粘接胶与VDMOS芯片的上表面相连接。In the above-mentioned VDMOS ceramic package structure, the thermally conductive integrated cover plate is disposed at the opening of the ceramic shell through adhesive, and the lower end of the thermally integrated cover plate is connected to the upper surface of the VDMOS chip through the adhesive. .
上述VDMOS陶瓷封装结构中，第一金属框架和第二金属框架均为可伐或铜材料，并且第一金属框架和第二金属框架的表面均镀镍镀金。In the above VDMOS ceramic package structure, the first metal frame and the second metal frame are made of Kovar or copper, and the surfaces of the first metal frame and the second metal frame are both plated with nickel and gold.
上述VDMOS陶瓷封装结构中，第一金属框架和第二金属框架的横截面均为圆形或矩形，横截面积应满足0.06mm2～0.6mm2。In the above-mentioned VDMOS ceramic package structure, the cross sections of the first metal frame and the second metal frame are both circular or rectangular, and the cross-sectional area should satisfy 0.06mm 2 -0.6mm 2 .
上述VDMOS陶瓷封装结构中，陶瓷外壳加工采用多层陶瓷层压工艺，将第一金属框架和第二金属框架用陶瓷片压实，并通过烧结形成。In the above-mentioned VDMOS ceramic package structure, the ceramic shell is processed by a multi-layer ceramic lamination process, and the first metal frame and the second metal frame are compacted with ceramic sheets, and formed by sintering.
上述VDMOS陶瓷封装结构中，VDMOS芯片与第一金属框架、第二金属框架互连采用涂覆焊料回流焊工艺。In the above-mentioned VDMOS ceramic package structure, the interconnection between the VDMOS chip, the first metal frame and the second metal frame adopts a solder coating reflow process.
上述VDMOS陶瓷封装结构中，VDMOS芯片焊接过程中，先将焊料涂覆在VDMOS芯片对应焊盘，再将VDMOS芯片放置在第一金属框架和第二金属框架的对应位置，最后加热回流形成牢固焊点。In the above VDMOS ceramic package structure, during the welding process of the VDMOS chip, the solder is first coated on the corresponding pad of the VDMOS chip, and then the VDMOS chip is placed in the corresponding position of the first metal frame and the second metal frame, and finally heated and reflowed to form a firm solder joint. point.
上述VDMOS陶瓷封装结构中，导热一体式盖板为可伐或铜材料，并且导热一体式盖板的表面镀镍镀金。In the above VDMOS ceramic package structure, the thermally conductive integrated cover plate is made of Kovar or copper, and the surface of the thermally conductive integrated cover plate is plated with nickel and gold.
上述VDMOS陶瓷封装结构中，在导热一体式盖板粘接过程中，先将粘接胶涂覆在VDMOS芯片上侧和陶瓷外壳封口环的位置，再将导热一体式盖板对准放置到相应位置，保证导热一体式盖板导热区域和VDMOS芯片表面接触、导热一体式盖板的封口区域和陶瓷外壳表面接触，最后通过高温固化在两个区域同时形成粘接。In the above VDMOS ceramic package structure, during the bonding process of the thermally integrated cover plate, the adhesive is first coated on the upper side of the VDMOS chip and the position of the sealing ring of the ceramic shell, and then the thermally integrated cover plate is aligned and placed in the corresponding position. position, to ensure that the thermal conduction area of the thermally integrated cover plate is in contact with the surface of the VDMOS chip, and the sealing area of the thermally integrated cover plate is in contact with the surface of the ceramic shell. Finally, the two areas are bonded at the same time through high temperature curing.
本发明与现有技术相比具有如下有益效果：Compared with the prior art, the present invention has the following beneficial effects:
(1)本发明采用粗金属框架替代陶瓷印刷布线，并通过层压工艺嵌入到陶瓷体中，框架作为电流通路能够显著提高封装的大电流承载能力；(1) The present invention uses a thick metal frame to replace the ceramic printed wiring, and is embedded in the ceramic body through a lamination process, and the frame can significantly improve the large current carrying capacity of the package as a current path;
(2)本发明采用焊接工艺实现VDMOS与框架的互连，VDMOS源极和漏级直接连接到外部通路，使整体导通电阻显著降低；(2) The present invention adopts the welding process to realize the interconnection between the VDMOS and the frame, and the VDMOS source and drain are directly connected to the external path, so that the overall on-resistance is significantly reduced;
(3)本发明采用直接接触式盖板，使器件热量直接有效的导出到封装顶部，显著减小了器件热阻；(3) The present invention adopts a direct contact cover plate, so that the heat of the device can be directly and effectively exported to the top of the package, and the thermal resistance of the device is significantly reduced;
(4)本发明相比同类型塑料封装，这种结构能够在保证器件优良的电学和散热性能的同时，大大提高在高温、高湿度等恶劣环境下的可靠性；(4) Compared with the same type of plastic package, this structure can greatly improve the reliability in harsh environments such as high temperature and high humidity while ensuring the excellent electrical and heat dissipation performance of the device;
(5)本发明采用的封装工艺步骤简单，减少了芯片粘片和固化等时间，封装工艺效率大大提升。(5) The packaging process steps adopted by the present invention are simple, the time for chip bonding and curing, etc. is reduced, and the packaging process efficiency is greatly improved.
附图说明Description of drawings
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for the purpose of illustrating preferred embodiments only and are not to be considered limiting of the invention. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:
图1为本发明一种VDMOS陶瓷封装结构的陶瓷封装结构剖面示意图；1 is a schematic cross-sectional view of a ceramic packaging structure of a VDMOS ceramic packaging structure of the present invention;
图2为本发明一种VDMOS陶瓷封装结构的陶瓷封装结构侧面示意图；2 is a schematic side view of a ceramic packaging structure of a VDMOS ceramic packaging structure of the present invention;
图3为本发明一种VDMOS陶瓷封装结构的陶瓷外壳剖面示意图；3 is a schematic cross-sectional view of a ceramic shell of a VDMOS ceramic packaging structure of the present invention;
图4为本发明一种VDMOS陶瓷封装结构的VDMOS芯片和陶瓷外壳焊接后剖面示意图；4 is a schematic cross-sectional view after welding of a VDMOS chip and a ceramic shell of a VDMOS ceramic packaging structure of the present invention;
图5为本发明一种VDMOS陶瓷封装结构的VDMOS芯片和陶瓷外壳焊接后顶视图。FIG. 5 is a top view after welding of a VDMOS chip and a ceramic shell of a VDMOS ceramic package structure of the present invention.
图6为本发明一种VDMOS陶瓷封装结构的陶瓷封装盖板示意图；6 is a schematic diagram of a ceramic package cover plate of a VDMOS ceramic package structure of the present invention;
图7为本发明一种VDMOS陶瓷封装结构的盖板粘接后顶示图；7 is a top view after bonding of a cover plate of a VDMOS ceramic packaging structure of the present invention;
图8为本发明一种VDMOS陶瓷封装结构的陶瓷封装结构的另一剖面示意图。8 is another schematic cross-sectional view of a ceramic packaging structure of a VDMOS ceramic packaging structure of the present invention.
具体实施方式Detailed ways
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
如图1、图2、图3、图4和图5所示，该VDMOS陶瓷封装结构包括：第一金属框架11、第二金属框架12、陶瓷外壳2、导热一体式盖板3和VDMOS芯片4；其中，As shown in Figure 1, Figure 2, Figure 3, Figure 4 and Figure 5, the VDMOS ceramic package structure includes: a
第一金属框架11包括第一支撑段111、第一上横段112和第一下横段113；其中，第一上横段112的一端和第一支撑段111的顶端相连接；第一下横段113的一端和第一支撑段111的中部相连接；第一上横段112的另一端穿过陶瓷外壳2的一个侧壁与VDMOS芯片4的一端的上部相连接；第一下横段113的另一端穿过陶瓷外壳2的一个侧壁与VDMOS芯片4的一端的下部相连接；The
第二金属框架12包括第二支撑段121、第二上横段122和第二下横段123；其中，第二上横段122的一端和第二支撑段121的顶端相连接；第二下横段123的一端和第二支撑段121的中部相连接；第二上横段122的另一端穿过陶瓷外壳2的另一个侧壁与VDMOS芯片4的另一端的上部相连接；第二下横段123的另一端穿过陶瓷外壳2的另一个侧壁与VDMOS芯片4的另一端的下部相连接；The
所述导热一体式盖板3设置于所述陶瓷外壳2的开口处，并且所述导热一体式盖板3的下端与VDMOS芯片4的上表面相连接。The thermally conductive integrated cover plate 3 is disposed at the opening of the
第一上横段112的另一端穿过陶瓷外壳2的一个侧壁通过焊点5与VDMOS芯片4的一端的上部相连接；第一下横段113的另一端穿过陶瓷外壳2的一个侧壁通过焊点5与VDMOS芯片4的一端的下部相连接；The other end of the first upper
第二上横段122的另一端穿过陶瓷外壳2的另一个侧壁通过焊点5与VDMOS芯片4的另一端的上部相连接；第二下横段123的另一端穿过陶瓷外壳2的另一个侧壁通过焊点5与VDMOS芯片4的另一端的下部相连接。The other end of the second upper
所述导热一体式盖板3通过粘接胶6设置于所述陶瓷外壳2的开口处，并且所述导热一体式盖板3的下端通过粘接胶6与VDMOS芯片4的上表面相连接。The thermally conductive integrated cover plate 3 is disposed at the opening of the
如图4所示，需要精确控制一体式盖板3的平板尺寸L和导热柱高度H，其约束关系如下：As shown in Figure 4, it is necessary to precisely control the plate size L and the height H of the heat conduction column of the integrated cover plate 3, and the constraint relationship is as follows:
L1+2×1.2≥L≥L1+2×0.8L1+2×1.2≥L≥L1+2×0.8
H＝H1+Z1+Z2-Z3H=H1+Z1+Z2-Z3
其中，L为一体式盖板3的尺寸，L1为陶瓷外壳2的腔体尺寸；H为一体式盖板3的导热柱高度，H1为陶瓷外壳2腔体表面到第二上横段122下表面距离，Z1为框架与芯片焊点高度，Z2为盖板和陶瓷外壳粘接厚度，Z3为导热柱和芯片的粘接厚度。Among them, L is the size of the one-piece cover plate 3, L1 is the cavity size of the
通过上述公式能保证腔体气密性，导热柱粘接可靠。The above formula can ensure the air tightness of the cavity, and the bonding of the thermal conductive column is reliable.
如图5和图8所示，需要精确控制第一金属框架11/第二金属框架12和芯片4焊接的焊料量厚度Z1和焊料量V，其约束关系如下：As shown in FIG. 5 and FIG. 8 , it is necessary to precisely control the amount of solder, the thickness Z1 and the amount of solder V for welding the
其中，M为金属框的有效焊接长度，W为金属框的宽度，D为上下框架间的间距，D1为芯片厚度。Among them, M is the effective welding length of the metal frame, W is the width of the metal frame, D is the distance between the upper and lower frames, and D1 is the thickness of the chip.
通过该公式能保证芯片与上下金属框架形成牢固焊接，且不会由于焊料过多、溢出，造成相邻焊点短路。This formula can ensure that the chip and the upper and lower metal frames are firmly welded, and the adjacent solder joints will not be short-circuited due to excess and overflow of solder.
本实施例采用粗金属框架替代陶瓷印刷布线，并通过层压工艺嵌入到陶瓷体中；VDMOS上下的源极和漏级与框架互连改为焊接工艺，VDMOS源极和漏级直接连接到外部通路；采用直接接触式盖板，使器件热量直接有效的导出到封装顶部。In this embodiment, a thick metal frame is used to replace the ceramic printed wiring, and it is embedded in the ceramic body through a lamination process; the interconnection between the source and drain stages of the VDMOS and the frame is changed to a welding process, and the VDMOS source and drain are directly connected to the outside. Via; direct contact cover plate is adopted, so that the heat of the device can be directly and effectively exported to the top of the package.
本实施例的粗金属框架的横截面远大于陶瓷印刷布线，能够显著提高互连的大电流承载能力；VDMOS与外壳互连由键合丝改为焊接工艺，减少了键合丝的导通电阻，并且框使本身的导通电阻也显著降低；并且散热盖板和芯片直接接触，使器件热量直接有效的导出到封装顶部，显著减小了器件热阻。The cross section of the thick metal frame in this embodiment is much larger than that of the ceramic printed wiring, which can significantly improve the large current carrying capacity of the interconnection; the interconnection between the VDMOS and the shell is changed from a bonding wire to a welding process, which reduces the on-resistance of the bonding wire , and the on-resistance of the frame itself is also significantly reduced; and the heat dissipation cover plate and the chip are in direct contact, so that the heat of the device is directly and effectively exported to the top of the package, which significantly reduces the thermal resistance of the device.
本实施例将常规陶瓷外壳的印刷走线改成粗金属框架；陶瓷外壳作为绝缘材料起到支撑框架与形成腔体空间的作用；盖板在封装腔体内与VDMOS芯片连接，在外与陶瓷外壳表面共同形成密闭空间；VDMOS芯片在外壳中，芯片上下两极分别与上下的金属框架互连；VDMOS芯片与金属框架采用焊接工艺进行互连；盖板与外壳表面和芯片上侧采用粘接工艺进行互连。In this embodiment, the printed wiring of the conventional ceramic casing is changed to a thick metal frame; the ceramic casing acts as an insulating material to support the frame and form the cavity space; the cover plate is connected to the VDMOS chip in the packaging cavity, and is externally connected to the surface of the ceramic casing A closed space is formed together; the VDMOS chip is in the casing, and the upper and lower poles of the chip are respectively interconnected with the upper and lower metal frames; the VDMOS chip and the metal frame are interconnected by welding; even.
如图3所示是陶瓷外壳剖面示意图，可根据实际情况选择可伐或铜等作为框架材料，并且在表面镀镍镀金；金属框架的横截面可为圆形或矩形，并根据所承载电流的大小选择合适的横截面积(一般大于0.06mm2)；要求金属框架必须为上下2层，而且框架在外壳内要足够长，在外壳内部要延伸至芯片上方。As shown in Figure 3 is a schematic cross-sectional view of the ceramic shell. Kovar or copper can be selected as the frame material according to the actual situation, and the surface is plated with nickel and gold; the cross-section of the metal frame can be circular or rectangular, and according to the current carried Select the appropriate cross-sectional area for the size (generally greater than 0.06mm 2 ); the metal frame must be two layers up and down, and the frame must be long enough in the casing and extend above the chip inside the casing.
如图3所示是陶瓷外壳剖面示意图，要求陶瓷外壳加工必须采用多层陶瓷层压工艺，将两层金属框架用上下两层陶瓷片压实，并通过烧结形成牢固、密闭的完整框架结构。Figure 3 is a schematic cross-sectional view of the ceramic shell. It is required that the ceramic shell must be processed by a multi-layer ceramic lamination process. The two-layer metal frame is compacted with the upper and lower layers of ceramic sheets, and a firm and airtight complete frame structure is formed by sintering.
如图4和图5所示是VDMOS芯片和陶瓷外壳焊接后剖面示意图和顶视图，VDMOS芯片必须为源极与漏级各在上下表面的VDMOS器件；并且芯片与金属框架互连采用涂覆焊料回流焊工艺：在芯片焊接过程中，先将焊料涂覆在芯片对应焊盘，再将芯片放置在金属框架对应位置，最后加热回流完成焊接。As shown in Figure 4 and Figure 5 are the schematic cross-sectional view and top view of the VDMOS chip and the ceramic shell after welding. The VDMOS chip must be a VDMOS device with the source and drain levels on the upper and lower surfaces; and the chip and the metal frame are interconnected by coating solder. Reflow soldering process: In the process of chip soldering, the solder is first coated on the corresponding pads of the chip, then the chip is placed in the corresponding position of the metal frame, and finally the soldering is completed by heating and reflowing.
如图6所示是陶瓷封装盖板示意图，盖板材料为可伐或铜材料，并在表面镀镍镀金；盖板应该为中间凸起、四周较薄的形态，尺寸要能覆盖陶瓷外壳的腔体，并足够和瓷体边缘形成可靠连接；要保证组装后盖板粘接后中间凸起恰好和芯片表面牢固接触。As shown in Figure 6 is a schematic diagram of the ceramic package cover. The material of the cover is kovar or copper, and the surface is plated with nickel and gold; the cover should be convex in the middle and thin around it. The cavity is sufficient to form a reliable connection with the edge of the porcelain body; it is necessary to ensure that the middle protrusion is in firm contact with the surface of the chip after the cover plate is glued after assembly.
如图7所示是盖板粘接后顶示图，盖板与芯片和外壳表面的粘接采用非导电胶；在盖板粘接过程中，先将非导电胶涂覆在芯片上侧和陶瓷外壳封口环的位置，再将盖板对准放置到相应位置，保证盖板导热区域和芯片表面接触、盖板的封口区域和陶瓷外壳表面接触，最后通过高温固化在两个区域同时形成可靠粘接。As shown in Figure 7, it is the top view after the cover plate is bonded. The bonding between the cover plate and the chip and the surface of the shell adopts non-conductive adhesive; Position the sealing ring of the ceramic shell, and then align the cover plate to the corresponding position to ensure that the heat conduction area of the cover plate is in contact with the surface of the chip, and the sealing area of the cover plate is in contact with the surface of the ceramic shell. bonding.
综上所述，本发明的VDMOS陶瓷封装结构，采用粗金属框架替代陶瓷印刷布线，能够显著提高封装的大电流承载能力；采用焊接工艺实现VDMOS源极和漏级直接连接到外部通路，使整体导通电阻显著降低；采用直接接触式盖板，使器件热量直接有效的导出到封装顶部，显著减小了器件热阻；这种结构能够在保证器件优良的电学和散热性能的同时，大大提高在高温、高湿度等恶劣环境下的可靠性；并且相应封装工艺步骤简单，减少了芯片粘片和固化等时间，封装工艺效率大大提升。To sum up, the VDMOS ceramic package structure of the present invention uses a thick metal frame to replace the ceramic printed wiring, which can significantly improve the large current carrying capacity of the package; the VDMOS source and drain are directly connected to the external path by the welding process, so that the overall The on-resistance is significantly reduced; the direct contact cover plate is used to directly and effectively conduct the heat of the device to the top of the package, which significantly reduces the thermal resistance of the device; this structure can ensure the excellent electrical and heat dissipation performance of the device, while greatly improving Reliability in harsh environments such as high temperature and high humidity; and the corresponding packaging process steps are simple, reducing the time for chip bonding and curing, and greatly improving the packaging process efficiency.
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present invention without departing from the spirit and scope of the present invention. The technical solutions are subject to possible changes and modifications. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention belong to the technical solutions of the present invention. protected range.
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