CN114189160B - Light-load conduction control method and circuit for clamping tube in active clamping flyback topology - Google Patents
Light-load conduction control method and circuit for clamping tube in active clamping flyback topology Download PDFInfo
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- CN114189160B CN114189160B CN202111485700.0A CN202111485700A CN114189160B CN 114189160 B CN114189160 B CN 114189160B CN 202111485700 A CN202111485700 A CN 202111485700A CN 114189160 B CN114189160 B CN 114189160B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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Abstract
The invention relates to the technical field of active clamp flyback control, and discloses a light-load conduction control method of a clamp tube in an active clamp flyback topology. According to the invention, the clamping tube is controlled to conduct twice in one period, negative current with a certain degree is generated in the two times, and proper conduction time is searched for the first time, so that the conduction duration of the second time is determined to be relatively accurate, the problem that the conduction time of the clamping tube is too short or too long is effectively avoided, zero-voltage conduction under light load is accurately realized, and the turn-on loss is effectively reduced.
Description
Technical Field
The invention relates to the technical field of active clamp flyback control, in particular to a light load conduction control method and circuit for a clamp tube in an active clamp flyback topology.
Background
The Active Clamp Flyback (ACF) can realize the recovery of leakage inductance energy and zero voltage conduction (ZVS) of the primary side power device, thereby effectively improving the system efficiency and reducing the conduction loss. The active clamp flyback topology is shown in fig. 1, wherein LM and Lk respectively represent the equivalent excitation inductance and leakage inductance of the transformer, C01 is the clamp capacitance, QP0 and QA0 are the control signals of the main power tube and the clamp tube, sp0 and Sa0 are the control signals of the main power tube and the clamp tube, and zero voltage turn-on of the primary side main power tube can be realized through alternate conduction of QP0 and QA 0.
Referring to fig. 2, an ideal operating waveform of the active clamp flyback topology is shown, vds represents the drain voltage of the main power transistor QP0 in fig. 1, sa represents the conduction control signal of the clamp, sp represents the conduction control signal of the main power transistor, ILM represents the current waveform flowing through the excitation inductor LM in fig. 1. the main power tube is turned off at the moment tc0, the voltage on the clamping capacitor at the moment tc1 reaches the maximum value after a certain dead time, the current on the exciting inductance at the moment tc2 is reduced to 0, then the drain-source voltage of the main power tube starts to resonate until the moment tc3, the clamping tube QA0 is turned on again for a period of time until the moment tc4, the duration time is Ta0, and the current directions of the exciting inductances are opposite. At the time tc4, the clamping tube is turned off, then the Vds is discharged to 0 by negative current after a certain time, and the main power tube is conducted at the time tc5, so that zero-voltage conduction of the main power tube is realized.
In the prior art, the clamp is only turned on for a short period of time at the time tc3 shown in fig. 2, and the on time is often fixed, which has two possibilities: one is that the on-time is too short, and the negative current generated in this case is insufficient, and Vds is often not discharged to 0. Referring to fig. 3, at the time te3, the clamp tube is turned on for a short time, that is, ta0 is shorter than the ideal case shown in fig. 2, vds is not completely discharged to 0, and at the time te5, the main tube is turned on, and at the moment, vds at the moment is turned on and is completely discharged to 0 potential; another situation is that the set on-time is too long, as shown in fig. 4, ta0 is too long, resulting in that Vds decreases rapidly, and then leaks to 0 in td4 and td5, and the generated negative current in this case is too large, which may cause problems such as potential instability of power transmission.
Disclosure of Invention
The invention aims to provide a light load conduction control method and circuit for a clamping tube in an active clamping flyback topology, and solves the problems in the background technology.
In order to achieve the above purpose, the present invention provides the following technical solutions: the utility model provides a clamping tube light load conduction control method in active clamp flyback topology, includes active clamp flyback circuit, still includes light load conduction control circuit, light load conduction control circuit includes detection circuitry, first on time control module, second on time control module and drive unit, and detection circuitry and drive unit all are connected with active clamp flyback circuit, control method specifically includes the following steps:
the first step: the detection circuit detects the follow current time of the active clamp flyback circuit in a light load steady state, and sets the follow current time as an initial conduction time and a first conduction time;
and a second step of: the first conduction time control module outputs an initial conduction control signal to the clamping tube through the driving unit according to the first conduction time set by the detection circuit, the clamping tube is conducted, the detection circuit detects whether the drain-source voltage of the main power tube drops to 0 within a certain time, and the first conduction time is reset or the second conduction time is set according to the result;
and a third step of: the second conduction time control module outputs a twice conduction control signal to the clamping tube through the driving unit according to the first conduction time and the second conduction time fed back by the first conduction time control module and the detection circuit, and simultaneously, the main power tube is started next time, and the next period starts;
fourth step: the third step is performed periodically.
As a preferred embodiment of the present invention, in the second step, the detection circuit detects whether the drain-source voltage of the main power tube drops to 0 within a certain period of time, and resets the first conduction time according to the result, or sets the specific process of the second conduction time as follows: after the detection circuit detects that the clamp tube is conducted for the first time, whether the drain-source voltage of the main power tube is reduced to 0 or not in a shorter set time, if not, conducting in the next period is carried out, the first conduction duration of the clamp tube in the next period is increased by a certain delay, and the time is set to be the first conduction time of the next period; if the exciting current falls to 0, the difference between the first conduction time and the initial conduction time in the period, namely the time difference between the moment when the exciting current falls to 0 in the first conduction in the period and the initial value of the first conduction time is latched, and the time difference is set to be the second conduction time.
In the third step, the driving unit outputs a two-time conduction control signal to the clamp tube, so that the clamp tube is conducted after the main power tube is turned off and before the next main power tube is turned on, and the two conduction time periods are respectively a first conduction time and a second conduction time.
In a preferred embodiment of the present invention, in the third step, negative currents generated by the first conduction and the second conduction of the clamp tube are equal in magnitude and the negative currents are identical in duration.
A light load conduction control circuit of a clamping tube in an active clamping flyback topology is applied to a light load conduction control method of the clamping tube in the active clamping flyback topology, and comprises a detection circuit, a first conduction time control module, a second conduction time control module and a driving unit.
As a preferred embodiment of the present invention, the output end of the detection circuit is connected to the input end of the first conduction time control module, the output ends of the first conduction time control module and the detection circuit are both connected to the input end of the second conduction time control module, and the output ends of the first conduction time control module and the second conduction time control module are both connected to the input end of the driving unit.
Compared with the prior art, the invention provides a light load conduction control method and circuit for a clamping tube in an active clamping flyback topology, and the method has the following beneficial effects:
according to the light-load conduction control method and circuit for the clamping tube in the active clamping flyback topology, the clamping tube is controlled to conduct twice in one period, negative current with a certain degree is generated twice, proper conduction time is searched for the first time, so that the conduction duration of the second time is determined to be relatively accurate, the problem that the conduction time of the clamping tube is too short or too long is effectively avoided, zero-voltage conduction under light load is accurately realized, and the turn-on loss is effectively reduced.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of the structure of an active clamp flyback topology;
FIG. 2 is a waveform diagram of an active clamp flyback operation;
FIG. 3 is a graph of an operational waveform of an active clamp flyback clamp with too short an on-time;
FIG. 4 is a diagram of an operational waveform when the on-time of the active clamp flyback clamp is too long;
FIG. 5 is a waveform diagram illustrating operation of the present invention during a period of stable operation;
FIG. 6 is a diagram showing the waveforms of the operation of the clamp according to the present invention corresponding to different turn-off times after the first turn-on;
FIG. 7 is a graph showing the operational waveforms of the Ta adjustment stage according to the invention;
FIG. 8 is a system block diagram of a clamp light load turn-on control circuit according to the present invention;
FIG. 9 is a schematic circuit diagram of the detection circuit of the present invention;
FIG. 10 is a circuit diagram of a first on-time control module according to the present invention
FIG. 11 is a circuit diagram of a second on-time control module according to the present invention
FIG. 12 is a schematic waveform diagram of the related signals of the detection circuit of the present invention
Fig. 13 is a circuit diagram of a driving circuit according to the present invention.
Detailed Description
The invention is further described in connection with the following detailed description, in order to make the technical means, the creation characteristics, the achievement of the purpose and the effect of the invention easy to understand.
Referring to fig. 1-13, the present invention provides a technical solution: the utility model provides a clamping tube light load conduction control method in active clamp flyback topology, includes active clamp flyback circuit, still includes light load conduction control circuit, and light load conduction control circuit is connected with active clamp flyback circuit, light load conduction control circuit includes detection circuitry, first on time control module, second on time control module and drive unit, and detection circuitry and drive unit all are connected with active clamp flyback circuit, the control method specifically includes the following steps:
the first step: the detection circuit detects the follow current time Tdis of the active clamp flyback circuit in a light load steady state, the time is set to be initial conduction time Tdis and first conduction time, the first conduction time is the same as the initial conduction time Tdis, the initial conduction time Tdis is used in the second step, and Ta is set;
the freewheel time Tdis, as shown in fig. 5, starts from an extremely short dead time after the main power tube is turned off to the end of the moment when the primary exciting inductance current drops to 0;
and a second step of: the first conduction time control module outputs an initial conduction control signal to the clamping tube through the driving unit according to a first conduction time set by the detection circuit (the first conduction time is a follow current time Tdis of the detection circuit in the light load steady state of the active clamping flyback circuit), the clamping tube is conducted, the detection circuit detects whether the drain-source voltage of the main power tube is reduced to 0 in a certain time or not, and the first conduction time is reset or the second conduction time Ta is set according to the result;
and a third step of: the second conduction time control module outputs twice conduction control signals to the clamping tube through the driving unit according to the first conduction time and the second conduction time fed back by the first conduction time control module and the detection circuit, so that the clamping tube is conducted after the main power tube is turned off and before the main power tube is turned on next time, the two conduction time periods are respectively the first conduction time (sum of the second conduction time Ta and the initial conduction time Tdis) and the second conduction time Ta, and meanwhile, the main power tube is turned on next time and the next period starts;
as shown in fig. 5, according to Ta information obtained by first conduction of the clamp tube, the clamp tube is controlled to be turned on for the second time at time t5 and turned off at time t6 after the duration Ta time reaches t6, vds drops to 0 after the same Td time as that of the previous conduction, at this time, the main power tube is turned on, and since Vds has been released to 0, the main power tube realizes zero voltage turn-on;
fourth step: the third step is carried out periodically;
as shown in fig. 7, fig. 7 shows an operating waveform of the Ta adjustment stage of the present invention, where the waveform shown in fig. 7 includes three adjustment periods and a stabilization period, the waveform is the same as the waveform of the stabilization period, the first period is that the clamp is turned on at time t01, and there is no negative current when turned off, so that the lowest point voltage of Vds resonance is not different from that of a normal flyback converter, after Tdis detected, the second period is that the clamp is turned on at time t04, the conduction duration is increased by a short period of time on the basis of Tdis, and then turned off at time t07, and the generated negative current discharges the voltage of Vds to a potential lower than the lowest point of the first period, but because the negative current is not negative enough, the lowest point of Vds is still greater than 0; the third period, the conduction time of the clamping tube is continuously increased, the clamping tube is conducted until the time t13 at the time t11, and negative current generated in the third period is enough to discharge the charge on the drain-source parasitic capacitance of the main power tube, so that at the time t14, vds is discharged to 0, the time difference from t12 to t13 is counted and locked to Ta, the clamping tube is controlled to be conducted at the time t15 of the current period, the time of Ta is continued until the time t16, and the clamping tube is conducted twice in each period: the first conduction time is tdis+ta, the second conduction time is Ta, and the time of Ta characterizes proper negative current, so as to discharge the charge on the drain-source parasitic capacitance of the main power tube.
In this embodiment, in the second step, the detection circuit detects whether the drain-source voltage of the main power tube drops to 0 within a certain time, and resets the first conduction time according to the result, or sets the specific process of the second conduction time as follows: after the detection circuit detects that the clamp tube is conducted for the first time, whether the drain-source voltage of the main power tube is reduced to 0 or not in a shorter set time, if not, conducting in the next period is carried out, the first conduction duration of the clamp tube in the next period is increased by a certain delay, and the time is set to be the first conduction time of the next period; if the current drops to 0, the difference between the first conduction time and the initial conduction time in the period, namely, the time difference between the moment when the exciting current drops to 0 in the first conduction in the period and the initial value of the first conduction time is latched, the time difference is set as the second conduction time Ta,
in practical application, when the secondary side output voltage of the transformer is fixed, the first time Ta is positively correlated with the primary side input voltage, and when the input voltage rises, ta increases; when the input voltage is reduced, ta is reduced, when the primary side input voltage of the transformer is fixed, the first time Ta and the secondary side output voltage are in positive correlation, and when the output voltage is increased, ta is increased; when the output voltage is reduced, ta is reduced, and at the same time, it should be noted that the opening interval of the main power tube is approximately kept unchanged during steady-state operation, so that the second conduction time of the clamp tube in each period can be approximately considered to be kept unchanged after Ta is determined, and the initial time of the second conduction is approximately kept unchanged.
As shown in fig. 5, if the time of Ta control is enough, the current ILM on the exciting inductor will become negative, i.e. be maintained reversely for a period of time, after the clamp is turned on for the first time, the drain voltage Vds of the main power tube is discharged to 0 potential by negative current in a set shorter time Td, meanwhile, at time t4, the exciting inductor current is 0, then Vds starts to resonate again, and the difference between the first conduction time and the initial conduction time Tdis of the clamp in the current period, i.e. Ta is locked, which means that the negative current generated by the clamp in the Ta time is enough to discharge the charge on the drain-source parasitic capacitance of the main power tube.
The waveforms shown in fig. 6 show the variation waveforms of the negative current at different turn-off moments and the voltage at the drain end of the main power tube after the turn-off, wherein Vds represents the drain-source voltage of the main power tube, ILM represents the current of the exciting inductor, sa represents the control signal of the clamp tube, the clamp tube is turned on at ts0, if the clamp tube is turned off at ts1, the inductor current just reaches 0, the generated negative current i_neg1 is also 0, the resonance waveform of the drain end voltage of the main power tube is not different from the resonance waveform of the common flyback converter after the turn-off, and the lowest resonance point voltage is Vds1; if the clamping tube is turned off at the ts2 moment, a certain degree of negative current I_neg2 is generated at the moment, the drain terminal voltage of the main power tube is discharged to a potential Vds2 lower than Vds1 under the action of the negative current, but Vds2 is still higher than 0 potential; if the clamp is turned off at ts3, and the negative current i_neg3 generated at this time is larger than i_neg2, after ts3 is turned off, the drain voltage of the main power transistor is discharged to a lower potential Vds3, and Vds3 is just 0. It is approximately considered that controlling the turn-off time of the clamp after the first turn-on can be used to find a suitable negative current to provide a relatively accurate turn-on time parameter for the second turn-on.
In this embodiment, in the third step, the magnitudes of negative currents generated by the first conduction and the second conduction of the clamp tube on the exciting inductor are equal, the durations are the same, and the processes of the first conduction and the second conduction exist in each period of the steady state and do not overlap each other.
The utility model provides a clamp tube light load switches on control circuit in active clamp flyback topology, is applied in the control method of clamp tube light load switches on in active clamp flyback topology, including detection circuitry, first on-time control module, second on-time control module and drive unit, detection circuitry, the drain-source voltage of accepting the main power tube is used for judging whether the negative current that produces after the first clamp tube switches on is enough, produces enable signal EN control adjustment first on-time to produce initial on-time according to the drain-source voltage of main power tube.
As shown in fig. 9, the detection circuit detects SW, i.e. the drain voltage of the main power tube, generates Tdis and detects whether the SW voltage drops to about 0 potential in Td time after the first turn-on, and generates the enable control signal EN if the SW voltage does not drop to 0, so as to control the first turn-on unit to control the next period clamp tube to be turned off later for a period of time; if it falls to 0, the current first on-time is latched. On the other hand, the detection circuit also detects the initial on-time Tdis;
the detection circuit comprises a voltage signal SW, wherein the voltage signal SW is connected with a drain end of a JFET tube QD0, a source end of the QD0 is connected with a forward input end of a comparator CMP2, an inverse input end of the comparator CMP2 is connected with a +100mV voltage signal, an output end of the comparator CMP2 is connected with a data input end D end of a D trigger DFF1, a clock input end CLK of the DFF1 is connected with a sampling signal Td, and an output generation control signal EN of the trigger DFF1 is connected with an input end of a first conduction control module; the voltage signal SW is further connected to an upper polar plate of the capacitor CS, a lower polar plate of the capacitor CS is connected to one end of a resistor Rs, the other end of the resistor Rs is grounded, the lower polar plate of the capacitor CS is further connected to an inverting input end of a comparator CMP1, a positive input end of the comparator CMP1 is connected to a +10mv voltage signal, an output of the comparator CMP1 is connected to a drain end of an NMOS tube MN0, a gate of the NMOS tube NM0 is connected to a control signal off_leb, a source of the NMOS tube NM0 is connected to ground, an output of the comparator CMP1 is further connected to one input end of a Nor gate nor1, the other input end of the Nor gate nor1 is connected to an output of a Nor gate nor2, a Tdis signal generated by the output of the Nor gate nor1 is connected to an input end of a second ON control module, the control signal sp_on and the control signal off_leb are further connected to one input end of the Nor gate nor3, and the other input ends of the Nor gate Nor2 are connected to the other input end of the Nor gate 2;
in fig. 9, CS and Rs constitute a simple differentiating circuit, the output of which is input to the inverting input terminal of the comparator CMP1 to be compared with the +10mv reference voltage, the output of the comparator being pulled down during the off_leb time, masking the output of the comparator; after the OFF_LEB time, the comparator normally outputs a comparison signal. The output of the comparator CMP1 is connected with the input end of the Nor gate Nor1, nor1 and Nor2 form an SR trigger, the output of Nor1 is Tdis, SP_ON is a control signal of the main power tube, and OFF_LEB represents a shorter dead time after the main power tube is turned OFF. The time point when the freewheeling to 0, namely the moment when the inductive current reaches 0, is determined by detecting the change rate of SW, and the Tdis signal is obtained after latching. SW is also connected with the Drain end of JFET QD0, the source end of QD0 is connected with the reverse input end of a comparator CMP2, the positive input end of CMP2 is connected with +100mV voltage, the output of the comparator CMP2 is connected with the Data end of a D trigger DFF1, the CLK input end of DFF1 is connected with a Td control signal, and the output of the comparator CMP2 is sampled at the falling edge of Td to obtain an EN signal. That is, in Td time, if the SW voltage drops below the reference threshold value of 100mV, the on time is considered to generate enough negative current, EN is low, otherwise EN is high, and the first on control module in the next period is controlled to continuously adjust the first on time;
FIG. 12 shows the working waveform of the key signal in a period in FIG. 9, SW represents the drain voltage of the main power tube, SP_ON is the ON signal of the main power tube, OFF_LEB is the dead zone control signal after the main power tube is turned OFF, tdis is the output control signal of the detection unit, td is the set detection time signal, and EN is the output of the detection module; in this period shown in fig. 12, tdis starts at time t_de3 and ends at time t_de4, after a delay of Td, the SW voltage does not drop to 0, and the output of the falling edge sampling comparator CMP2 of Td is high, i.e., EN is high, so that the first on time of the next period continues to increase.
As shown in fig. 10, the first on-time control module outputs a first on-control signal, and adjusts the first on-time according to feedback from the detection circuit until a second on-time Ta is generated, so as to control the clamp tube to conduct for the second time;
the first-time on-time control signal Tdis is connected with a grid electrode of a PMOS tube MP1, the Tdis signal is also connected with a grid electrode of an NMOS tube NM1, the Tdis signal is also connected with one input end of a NOR gate Nor5, a source electrode of the PMOS tube MP1 is connected with a current source Ic, a drain electrode of the MP1 is connected with a drain electrode of the NMOS tube NM1, the drain electrode of the MP1 is also connected with an upper polar plate of a capacitor CH1, the drain electrode of the MP1 is also connected with one input end of a NOR gate Nor4, the other input end of the NOR gate Nor4 is connected with an output end of the NOR gate Nor5, the other input end of the NOR gate Nor5 is connected with an output end of the NOR gate Nor4, a lower polar plate of the capacitor CH1 is connected with ground, the control signal Tdis is connected with an input end of a bidirectional counting unit 1, the output of the current Nor gate Nor1 is increased or the output of the NOR gate Nor4 is decreased in a cycle of the current on-time;
the gates of MP1 and MP2 are connected with the control signal Tdis, the current Ic charges and discharges the capacitor CH1, the EN controls the up-down counting unit CNT1 to control the charging current Ic to increase or decrease, and when the charging current Ic increases, the first on control signal T1 becomes shorter; when decreasing, the first turn-on control signal T1 becomes longer;
as shown in fig. 11, the second on-time control module obtains a second on-time control signal Ta according to the first on-control signal T1 and the initial on-time Tdis fed back by the first on-time control module, controls the clamp tube to generate a second on-control signal, and generates second clamp tube on-off signals according to Ta and the period of the main power tube in the previous period;
the inverse signal of T1 and Tdis NOT logic generate a second conduction control signal Ta;
the driving unit controls the clamping tube to sequentially complete first conduction and second conduction according to control signals generated by the first conduction time control module and the second conduction time control module;
as shown in fig. 9 and 13, the clamp is controlled to complete the first conduction and the second conduction in sequence according to the control signals generated by the first conduction time control module and the second conduction time control module;
the control signal T1 of the first conduction control module and the control signal Ta of the second conduction control module are input to the grids of LDMOS LD1 and LD2 through OR gate OR1 and inverter Inv3, level conversion signals are generated through RD1 and RD2 and sent to the input end of RS trigger RS1, RD3, PD1 and Cd1 are used for suppressing common mode noise, PD2, RD4 and Cd2 are also used for suppressing common mode noise, the output of RS1 drives the grid of the active clamp through driving buffer DR1, the reference ground potential of RS1 and DR1 is connected with SW, the reference power supply potential is connected with VB, and bootstrap capacitor CB is also connected between VB and SW in series.
In this embodiment, the output end of the detection circuit is connected to the input end of the first conduction time control module, the output ends of the first conduction time control module and the detection circuit are connected to the input end of the second conduction time control module, the output ends of the first conduction time control module and the second conduction time control module are connected to the input end of the driving unit, and the output end of the driving unit is connected to the gate electrode of the active clamp tube.
While the fundamental and principal features of the invention and advantages of the invention have been shown and described, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (6)
1. The utility model provides a control method is switched on to clamp tube light load in active clamp flyback topology, includes active clamp flyback circuit, its characterized in that: the control method comprises the following steps of:
the first step: the detection circuit detects the follow current time of the active clamp flyback circuit in a light load steady state, and sets the follow current time as an initial conduction time and a first conduction time;
and a second step of: the first conduction time control module outputs an initial conduction control signal to the clamping tube through the driving unit according to the first conduction time set by the detection circuit, the clamping tube is conducted, the detection circuit detects whether the drain-source voltage of the main power tube drops to 0 within a certain time, and the first conduction time is reset or the second conduction time is set according to the result;
and a third step of: the second conduction time control module outputs a twice conduction control signal to the clamping tube through the driving unit according to the first conduction time and the second conduction time fed back by the first conduction time control module and the detection circuit, and simultaneously, the main power tube is started next time, and the next period starts;
fourth step: the third step is performed periodically.
2. The method for controlling light load conduction of a clamping tube in an active clamping flyback topology according to claim 1, wherein the method comprises the following steps: in the second step, the detection circuit detects whether the drain-source voltage of the main power tube drops to 0 within a certain time, and resets the first conduction time according to the result, or sets the specific process of the second conduction time as follows: after the detection circuit detects that the clamp tube is conducted for the first time, whether the drain-source voltage of the main power tube is reduced to 0 or not in a shorter set time, if not, conducting in the next period is carried out, the first conduction duration of the clamp tube in the next period is increased by a certain delay, and the time is set to be the first conduction time of the next period; if the exciting current falls to 0, the difference between the first conduction time and the initial conduction time in the period, namely the time difference between the moment when the exciting current falls to 0 in the first conduction in the period and the initial value of the first conduction time is latched, and the time difference is set to be the second conduction time.
3. The method for controlling light load conduction of a clamping tube in an active clamping flyback topology according to claim 1, wherein the method comprises the following steps: in the third step, the driving unit outputs a two-time conduction control signal to the clamping tube, so that the clamping tube is conducted after the main power tube is turned off and before the next main power tube is turned on, and the two conduction time periods are respectively a first conduction time and a second conduction time.
4. The method for controlling light load conduction of a clamping tube in an active clamping flyback topology according to claim 1, wherein the method comprises the following steps: in the third step, the magnitudes of negative currents generated by the first conduction and the second conduction of the clamping tube are equal, and the durations of the negative currents are the same.
5. A light load conduction control circuit of a clamping tube in an active clamping flyback topology, which is applied to the light load conduction control method of the clamping tube in the active clamping flyback topology as set forth in any one of claims 1 to 4, and is characterized in that: the circuit comprises a detection circuit, a first conduction time control module, a second conduction time control module and a driving unit.
6. The light load turn-on control circuit of a clamp tube in an active clamp flyback topology according to claim 5, wherein: the output end of the detection circuit is connected with the input end of the first conduction time control module, the output ends of the first conduction time control module and the detection circuit are connected with the input end of the second conduction time control module, and the output ends of the first conduction time control module and the second conduction time control module are connected with the input end of the driving unit.
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