CN114189148B

CN114189148B - Power converter and control method thereof

Info

Publication number: CN114189148B
Application number: CN202210071119.2A
Authority: CN
Inventors: 林友实
Original assignee: Yutai Semiconductor Co ltd
Current assignee: Yutai Semiconductor Co ltd
Priority date: 2022-01-21
Filing date: 2022-01-21
Publication date: 2022-10-21
Anticipated expiration: 2042-01-21
Also published as: CN114189148A

Abstract

The invention discloses a power converter and a control method thereof. The power converter includes complementary transistors and a mode switching circuit. The mode switching circuit turns on a first transistor of the complementary transistors in a first mode so that the first transistor converts the input voltage into a first output voltage, and turns on a second transistor of the complementary transistors in a second mode so that the second transistor converts the input voltage into a second output voltage. The power converter combines the input voltage ranges of complementary transistors, thus having an extended input voltage range of the power converter.

Description

Power converter and control method thereof

Technical Field

The present invention relates to the field of circuit technologies, and in particular, to a power converter and a control method thereof.

Background

At present, with the development of integrated circuits, the integration level of chips is continuously improved, and higher operating voltages also put higher and higher requirements on the high-voltage technology of the chips. However, because the high voltage devices inside the chip occupy a large area, it is necessary to design as many modules as possible to operate at a low voltage. For this reason, it is necessary to convert the high voltage input to the chip into a low voltage to supply power to the low voltage devices inside the chip.

The traditional design scheme for converting high pressure into low pressure mainly comprises three types: 1. the conventional high-voltage circuit adopts an LDO (low dropout regulator) circuit to drive a bandgap reference circuit and an external bias current circuit to generate a fixed low voltage. This solution can produce a constant low level, but the loop is too complex and wastes chip area. 2. The circuit design of the scheme is simple, but the size parameters of the related devices are overlarge, so that the optimization of the chip area is not facilitated, and the device cost is high. 3. A number of MOS diodes are connected to the source of the NMOS source follower to generate a low voltage. The disadvantage of this scheme is that when the input voltage is low, the NMOS source follower cannot work normally, which affects the stability of the whole chip during operation.

It is therefore desirable to provide a power converter in a chip that can convert a high voltage to a low voltage over an extended input voltage range.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a power converter and a control method thereof, thereby enabling the power converter to normally operate in an extended input voltage range.

According to an aspect of the present invention, there is provided a power converter including: a first transistor having a first doping type and a second transistor having a second doping type opposite to the first doping type, each transistor having a control terminal, a first terminal coupled to the input terminal, and a second terminal coupled to the output terminal; and a mode switching circuit coupled to control terminals of the first transistor and the second transistor, wherein the mode switching circuit is configured to turn on the first transistor and turn off the second transistor in a first mode so that the first transistor converts an input voltage into a first output voltage, and turn off the first transistor and turn on the second transistor in a second mode so that the second transistor converts the input voltage into a second output voltage, and both the first output voltage and the second output voltage are lower than the input voltage.

Optionally, the mode switching circuit includes: and a bias current generation circuit for generating a bias current varying with the input voltage, wherein the first transistor and the second transistor are turned on or off according to the bias current.

Optionally, the mode switching circuit further includes: a pull-up circuit and a pull-down circuit coupled between the input terminal and a ground terminal, the pull-up circuit and the pull-down circuit having a first node coupled to the control terminal of the first transistor; and a first current source coupled between the input terminal and the ground terminal with the bias current generating circuit and having a second node coupled with a control terminal of the second transistor, wherein the pull-up circuit and the pull-down circuit are configured to generate a first current and a second current according to a bias current related to the input voltage, respectively, and the first transistor is turned on or off according to a difference between the first current and the second current, and the second transistor is turned on or off according to a current value of the bias current.

Optionally, the mode switching circuit further includes: a first clamp circuit coupled between a first terminal and a control terminal of the first transistor and configured to generate a first clamp voltage at the control terminal of the first transistor; and a second clamp circuit coupled between the control terminal and the ground terminal of the second transistor and configured to generate a second clamp voltage at the control terminal of the second transistor.

Optionally, the first clamping circuit and the second clamping circuit each include: a plurality of transistors coupled in series, each transistor connected as a diode.

Optionally, the plurality of transistors in the second clamp circuit further includes a third transistor, the third transistor has a control terminal, a first terminal coupled to one of the plurality of transistors, and a second terminal coupled to a ground terminal, and the bias current generating circuit shares the third transistor to generate the bias current.

Optionally, the power converter further includes: a first current source coupled between the input terminal and the second clamp circuit, the first current source for generating a first reference current.

Optionally, the pull-up circuit and the pull-down circuit are both coupled to the third transistor to generate a mirror current of the bias current.

Optionally, the pull-up circuit includes: a fourth transistor having a control terminal, a first terminal coupled to the input terminal, and a second terminal coupled to the control terminal of the first transistor; a fifth transistor having a control terminal coupled to the control terminal of the fourth transistor, a first terminal coupled to the input terminal, and a second terminal coupled to the control terminal of the fifth transistor; and a sixth transistor having a control terminal coupled to the control terminal of the third transistor, a first terminal coupled to the second terminal of the fifth transistor, and a second terminal coupled to ground, wherein the fourth transistor is configured to generate the first current.

Optionally, the pull-down circuit includes: a second current source for generating a second reference current; a seventh transistor having a control terminal, a first terminal coupled to the control terminal of the first transistor, and a second terminal coupled to a ground terminal; an eighth transistor having a control terminal coupled to the control terminal of the seventh transistor, a first terminal coupled to the second current source and the control terminal of the eighth transistor, and a second terminal coupled to a ground terminal; and a ninth transistor having a control terminal coupled to the control terminal of the third transistor, a first terminal coupled to the control terminal of the seventh transistor, and a second terminal coupled to a ground terminal, wherein the seventh transistor is configured to generate the second current.

Optionally, the mode switching circuit further includes: a hysteresis circuit coupled to the pull-up circuit and configured to provide a hysteresis current to the pull-up circuit.

Optionally, the hysteresis circuit includes: a tenth transistor having a control terminal coupled to the control terminal of the first transistor, a first terminal coupled to the input terminal, and a second terminal; and an eleventh transistor having a control terminal coupled to the control terminal of the fifth transistor, a first terminal coupled to the second terminal of the tenth transistor, and a second terminal coupled to the control terminal of the eleventh transistor, wherein the tenth transistor is configured to generate the hysteresis current.

Optionally, the power converter further includes: an auxiliary transistor having a first doping type has a control terminal coupled to the control terminal of the second transistor, a first terminal coupled to an output terminal, and a second terminal coupled to a ground terminal.

Optionally, the first doping type is P-type, and the second doping type is N-type.

Optionally, the power converter further includes: an auxiliary resistor coupled between the input terminal and the control terminal of the first transistor.

According to another aspect of the present invention, there is provided a control method of a power converter including a first transistor having a first doping type and a second transistor having a second doping type opposite to the first doping type, each transistor having a control terminal, a first terminal coupled to an input terminal, and a second terminal coupled to an output terminal, wherein the control method includes: turning on the first transistor and turning off the second transistor in a first mode so that the first transistor converts an input voltage into a first output voltage; and turning off the first transistor and turning on the second transistor in a second mode so that the second transistor converts the input voltage into a second output voltage, wherein the first mode and the second mode are changed according to a bias current varying with the input voltage, and the first output voltage and the second output voltage are both lower than the input voltage.

Optionally, the changing the first mode and the second mode according to the bias current varying with the input voltage includes: generating a first current and a second current according to the bias current, wherein the first current flows from the input end to the control end of the first transistor, and the second current flows from the control end of the first transistor to the ground end; and turning on or off the first transistor according to a difference between the first current and the second current, and turning on or off the second transistor according to a current value of the bias current.

Optionally, the control method further includes: providing a first clamp circuit coupled between the input terminal and a control terminal of the first transistor and providing a first clamp voltage; and providing a second clamp circuit coupled between the control terminal of the second transistor and a ground terminal and providing a second clamp voltage.

Optionally, the control method further includes: a first reference current is provided between the input terminal and a control terminal of the second transistor, and a current value of the bias current is adjusted by the second clamp circuit according to the input voltage.

Optionally, the control method further includes: providing a hysteresis current for adjusting the first current to provide hysteresis in the changing of the first and second modes.

Optionally, the control method further includes: an auxiliary transistor having a first doping type is provided, the auxiliary transistor having a control terminal coupled to the control terminal of the second transistor, a first terminal coupled to an output terminal, and a second terminal coupled to a ground terminal.

In order to solve the above technical problem, the present invention provides a power converter including complementary transistors and a mode switching circuit. The mode switching circuit turns on a first transistor of the complementary transistors in a first mode so that the first transistor converts the input voltage to a first output voltage, and turns on a second transistor of the complementary transistors in a second mode so that the second transistor converts the input voltage to a second output voltage. The power converter combines the input voltage ranges of the complementary transistors, thus having an extended input voltage range of the power converter.

In a preferred embodiment, the first transistor is a PMOS transistor and is turned on in a low input voltage range, and the second transistor is an NMOS transistor and is turned on in a high input voltage range. PMOS transistors have much lower Vgs losses than NMOS transistors and therefore lower the lower limit of the low input voltage range. Thus, the power converter has an extended input voltage range, but uses PMOS transistors in the low input voltage range.

In a preferred embodiment, the first transistor is used as a switch in the first mode to provide the input voltage directly from the input terminal to the output terminal in the low input voltage range, and the second transistor is used as a source follower in the second mode to provide the clamp voltage from the input terminal to the output terminal. The mode switching circuit automatically switches the complementary transistors according to a bias current varying with the input voltage. The mode switching circuit is a simple design to ensure that the power converter has an extended input voltage with minimal increase in chip size. In addition, the mode switching circuit has an open loop, thereby improving the stability of the power converter. The power converter is suitable for supplying power to a low-voltage circuit with low performance requirement and can also be used for supplying power to a starting circuit.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a block diagram of a power converter according to an embodiment of the invention.

Fig. 2 shows a circuit schematic of a power converter according to an embodiment of the invention.

Fig. 3 shows waveforms of an input voltage and an output voltage of a power converter according to an embodiment of the invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, identical elements or modules are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

The invention will be further described with reference to the following figures and examples.

Fig. 1 shows a block diagram of a power converter according to an embodiment of the invention. As shown in fig. 1, the power converter 100 includes a PMOS (P-channel metal-oxide-semiconductor) transistor M1 and an NMOS (N-channel metal-oxide-semiconductor) transistor M2, a first clamp circuit 111, a second clamp circuit 112, and a mode switching circuit 120.

The PMOS transistor M1 has a source coupled to the input terminal, a drain coupled to the output terminal, and a gate, and the NMOS transistor M2 has a drain coupled to the input terminal, a source coupled to the output terminal, and a gate. Wherein the input terminal is configured to receive a high voltage input voltage Vin _ HV and the output terminal is configured to provide a low voltage output voltage VCLP _ L.

The first clamp circuit 111 is coupled between the input terminal and the gate of the PMOS transistor M1. Further, the first clamp circuit 111 is configured to generate a first clamp voltage at the gate of the PMOS transistor M1, the first clamp voltage protecting the PMOS transistor M1 from being damaged when the source is directly coupled to the high voltage input terminal. The second clamp circuit 112 is coupled between the gate of the NMOS transistor M2 and ground. The second clamp circuit 112 is configured to generate a second clamp voltage at the gate of the NMOS transistor M2. When the gate of the NMOS transistor M2 receives a large bias voltage, the second clamp circuit 112 clamps the bias voltage to a predetermined value to protect the NMOS transistor M2 from damage by an excessive current through the NMOS transistor M2.

The mode switching circuit 120 includes a pull-up circuit 121, a pull-down circuit 122, a first current source 123, and a bias current generating circuit 124. The pull-up circuit 121 and the pull-down circuit 122 are coupled between the input terminal and the ground terminal, and the intermediate node is coupled to the gate of the PMOS transistor M1. The first current source 123 is coupled to the bias current generating circuit 124 between the input terminal and the ground terminal, wherein the middle node is coupled to the gate of the NMOS transistor M2.

The pull-up circuit 121 generates a pull-up current I21, and the pull-down circuit 122 generates a pull-down current I22. The first current source 123 generates a first reference current I1 having a fixed value. The first reference current I1 is large enough to support the pull-up current I21 higher than the pull-down current I22 when the high-voltage input voltage VIN _ HV is in the high-voltage range, and the first reference current I1 also needs to be large enough to be able to quickly charge the gate of the NMOS transistor M2 when the high-voltage input voltage VIN _ HV suddenly jumps from 0 to a high voltage. The bias current generating circuit 124 generates a bias current Ibias associated with the high voltage input voltage VIN _ HV. Both the pull-up current I21 and the pull-down current I22 vary with the bias current, and the PMOS transistor M1 is turned on or off according to the difference between the pull-up current I21 and the pull-down current I22. The NMOS transistor M2 is turned on or off according to the value of the bias current Ibias.

The first reference current I1 is the maximum current flowing through the second clamp circuit 112, when the high-voltage input voltage VIN _ HV is in a low voltage range, the second clamp circuit 112 will limit the current flowing through it, and the first reference current I1 is greater than the bias current Ibias, and the pull-up current I21 is less than the pull-down current I22. Thus, the power converter 100 operates in the first mode in which the PMOS transistor M1 is turned on and the NMOS transistor M2 is turned off. When the high-voltage input voltage VIN — HV is in the high-voltage range, the bias current Ibias increases to Ibias1 (Ibias 1< I1), and the pull-up current I21 is greater than the pull-down current I22. Thus, the power converter 100 operates in the second mode, in which the PMOS transistor M1 is turned off and the NMOS transistor M2 is turned on.

According to the above embodiment, the power converter 100 includes the PMOS transistor M1 and the NMOS transistor M2. In response to a change in the high-voltage input voltage VIN _ HV, the power converter 100 switches between the first mode and the second mode. In the first mode, the high-voltage input voltage VIN _ HV is converted into the low-voltage output voltage VCLP _ L by the PMOS transistor M1. In the second mode, the high voltage input voltage VIN _ HV is converted to the low voltage output voltage VCLP _ L by the NMOS transistor M2. The power converter 100 combines the input voltage ranges of the PMOS transistor M1 and the NMOS transistor M2, and thus has an extended input voltage range of the power converter.

The first clamp circuit 111 includes PMOS transistors M12-M15 coupled in series between the input terminal and the gate of the PMOS transistor M1, and each connected as a diode. For example, the PMOS transistor M12 has a gate and a drain coupled to each other. The other PMOS transistors are connected in a similar manner to the PMOS transistor M12. The first clamp circuit 111 generates a first clamp voltage of 4 VTP, where VTP is the threshold voltage of the PMOS transistor.

The second clamp circuit 112 includes NMOS transistors M16-M19 that are coupled in series between the gate of the PMOS transistor M1 and ground and are each connected as a diode. For example, the NMOS transistor M16 has a gate and a source coupled to each other. The other NMOS transistors are connected in a similar manner to NMOS transistor M16. The second clamp circuit 112 generates a second clamp voltage of 4 VTN, where VTN is the threshold voltage of the NMOS transistor.

The first reference current source 123 is coupled between the input terminal and the gate of the PMOS transistor M1. In a preferred embodiment, the bias current generating circuit 124 shares the last NMOS transistor M19 in the second clamp circuit 112.

The pull-up circuit 121 includes PMOS transistors M4 and M5, and an NMOS transistor M6. The PMOS transistor M5 and the NMOS transistor M6 are coupled in series between the input terminal and the ground terminal. Further, the gate of the NMOS transistor M19 in the second clamp circuit 112 is coupled to the gate of the NMOS transistor M6 to form a current mirror with a ratio of 1. Therefore, the value of the pull-up current I21 is equal to n3 × n5 × Ibias.

The pull-down unit 122 includes a second current source 125 and NMOS transistors M7-M9. The second current source 125 generates a second reference current I2 having a fixed value. The second current source 125 is coupled to the drain of the NMOS transistor M8. Further, the gate of the NMOS transistor M8 is coupled to the drain of the NMOS transistor M8 and to the gate of the NMOS M7 to form a current mirror with a ratio of 1. The gate of the NMOS transistor M19 in the second clamp circuit 112 is coupled to the gate of the NMOS M9 to form a current mirror with a ratio of 1. The NMOS M9 has a source coupled to ground and a drain coupled to the gate of the NMOS transistor M8. Therefore, the current value of the pull-down current I22 will be (I2-n 2 Ibias) n1.

The current mirror has a ratio between the input current and the output current. The ratio is determined by the width-to-length ratio (W/L) of the transistors in the current mirror, or by the number of transistors in the current mirror if the current mirror comprises a different number of transistors in the input branch and the output branch. For example, the current mirror of the NMOS transistor M8 and the NMOS transistor M7 has 1:8 in the sample. In one case, each of the NMOS transistors M8 and M7 may include the same number of transistors, but the NMOS transistor M7 has a width-to-length ratio 8 times that of the NMOS transistor M8. In another case, the NMOS transistors M8 and M7 may include different numbers of transistors, each having the same aspect ratio, but the number of transistors in the NMOS transistor M7 may be 8 times the number of transistors in the NMOS transistor M8.

In a preferred embodiment, the power converter 100 further comprises a hysteresis circuit 131. The hysteresis circuit 131 includes PMOS transistors M10 and M11. The source of the PMOS transistor M10 is coupled to the input terminal, the drain is coupled to the source of the PMOS transistor M11, and the gate is coupled to the gate of the PMOS transistor M1. The gate of PMOS transistor M5 in pull-up circuit 121 is coupled to the gate and source of PMOS transistor M11 to form mirror diodes of FETs (field Effect transistors) equal in number to (1 + n4).

In the case of using the hysteresis circuit 131 in the power converter, when the PMOS transistor M1 is turned on and the PMOS transistor M10 is also turned on, the pull-up current I21 will be n3 × n 5/(1 + n 4) × Ibias. When the pull-up current I21 is higher than the pull-down current I22, the PMOS transistor M1 tends to turn off, and the PMOS transistor M10 will also turn off following the PMOS transistor M1. When the PMOS transistor M10 is turned off, it will turn off the current through the PMOS transistor M11 and the pull-up current I21 will gradually change to the final value n3 n5 Ibias.

In a preferred embodiment, the power converter 100 further includes an auxiliary PMOS transistor M3, wherein a gate of the auxiliary PMOS transistor M3 is coupled to the gate of the NMOS transistor M2, a source thereof is coupled to the output terminal, and a drain thereof is coupled to the ground terminal. The auxiliary PMOS transistor M3 provides an additional way to protect the circuit from overshoot of the output voltage VCLP _ L caused by the PMOS transistor M1 not turning off quickly when VIN _ HV suddenly increases. Generally, by careful simulation, we can select a first reference current I1 that is high enough to avoid overshoot. Under abnormal conditions, however, VIN _ HV will increase rapidly, and the auxiliary PMOS transistor M3 will provide a secondary protection method, which will help clamp the output voltage VCLP _ L not to exceed 4 vtn + VTP, where VTP is the threshold voltage of the PMOS transistor M3.

In a preferred embodiment, the power converter 100 further includes an auxiliary resistor R1 coupled between the input and the gate of the PMOS transistor M1. In one or more examples, auxiliary resistor R1 is a large pull-up resistor adapted to provide a voltage to the gate of PMOS transistor M1.

Referring to fig. 3, the power converter 100 operates in an input voltage range with a lower limit of (VTP + VOV), where VTP represents the threshold voltage of the PMOS transistor M1 and VOV represents the overdrive voltage of the NMOS transistor M19.

During the time period T1, the high voltage input voltage VIN _ HV still has a small value. Therefore, the bias current Ibias through the NMOS transistor M19 has a very small value. The pull-up current I22 through the PMOS transistor M4 is smaller than the pull-down current I21 through the NMOS transistor M7. At this time, the gate of the PMOS transistor M1 is coupled to the ground terminal through the NMOS transistor M7, so the PMOS transistor M1 is turned on, and at the same time, the NMOS transistor M2 is turned off because the gate of the NMOS transistor M2 is coupled to the input terminal through the first current source 123. Then the power converter 100 operates in the first mode in which the high-voltage input voltage VIN _ HV is converted into the low-voltage output voltage VCLP _ L by the PMOS transistor M1, because the PMOS transistor M1 functions as a switch in the first mode, the low-voltage output voltage VCLP _ L rises with the rise of the high-voltage input voltage VIN _ HV.

In the time period T2, the high-voltage input voltage VIN _ HV rises to a value where the bias current Ibias through the NMOS transistor M19 increases to the first current threshold Ibias 1. The pull-up current I22 through the PMOS transistor M4 is greater than the pull-down current I21 through the NMOS transistor M7. As described above, both pull-up current I21 and pull-down current I22 are proportional to the bias current Ibias. When the bias current increases to a value greater than the first current threshold Ibias1, the difference between the pull-up current I21 and the pull-down current I22 changes from a negative value to a positive value, which is represented by the following equation:

IBIAS1＝(n1*I2-Ia1)/[n1*n2+n3*n5/(1+n4)] (1)

in equation (1), ia1 represents a current through the auxiliary resistor R1, I2 represents a second reference current in the pull-down circuit, and n1, n2, n3, n4, and n5 represent ratios of current mirrors in the power converter shown in the diagram.

At this time, the gate of the PMOS transistor M1 is pulled up to the first clamping voltage by the first clamping circuit 111, so the PMOS transistor M1 is turned off, while the gate of the NMOS transistor M2 is pulled up to the second clamping voltage by the second clamping circuit 112, so the NMOS transistor M2 is turned on. The power converter 100 then operates in a second mode in which the high voltage input voltage VIN _ HV is converted by the NMOS transistor M2 to a low voltage output voltage VCLP _ L, which will not follow the high voltage input voltage VIN _ HV because the NMOS transistor M2 acts as a source follower and is clamped at its gate.

In the time period T3, the high-voltage input voltage VIN _ HV falls to a value where the bias current Ibias through the NMOS transistor M19 decreases to the second current threshold Ibias 2. The pull-up current I21 through the PMOS transistor M4 is smaller than the pull-down current I22 through the NMOS transistor M7. As described above, both pull-up current I21 and pull-down current I22 are proportional to the bias current Ibias. When the bias current decreases to a value less than the second current threshold IBIAS2, the difference between the pull-up current I21 and the pull-down current I22 changes from a positive value to a negative value, which is represented by the following equation:

IBIAS2＝(n1*I2-Ia2)/(n1*n2+n3*n5) (2)

in equation (2), ia2 represents the current through the auxiliary resistor R1, I2 represents the second reference current in the pull-down circuit, and n1, n2, n3, n4, and n5 represent the ratios of the current mirrors in the power converter shown in fig. 1. The second current threshold IBIAS2 has a value smaller than the first current threshold IBIAS1 due to the current through the auxiliary resistor.

At this time, the gate of the PMOS transistor M1 is coupled to the ground terminal through the NMOS transistor M7, so the PMOS transistor M1 is turned on again, and at the same time, the NMOS transistor M2 is turned off again because the gate of the NMOS transistor M2 is coupled to the input terminal through the first current source 123. The power converter 100 operates again in the first mode, and the high-voltage input voltage VIN _ HV is converted into the low-voltage output voltage VCLP _ L by the PMOS transistor M1, because the PMOS transistor M1 functions as a switch in the first mode, the low-voltage output voltage VCLP _ L decreases as the high-voltage input voltage VIN _ HV decreases.

Further, the power converter 100 has an output voltage range of (VTP + VOV 1) to 4 × (VTN + VOV 2), where VTP denotes a threshold voltage of the PMOS transistor M1, VTN denotes a threshold voltage of the NMOS transistor M2, and VOV1 and VOV2 denote overdrive voltages of the NMOS transistor M19 at the first and second current thresholds, respectively.

In summary, the power converter of the embodiment of the present disclosure includes a source follower constituted by a PMOS transistor and an NMOS transistor. When the high-voltage input voltage of the voltage input port is not high enough, the high-voltage input voltage is converted into low-voltage output through the PMOS transistor. When the high-voltage input voltage is increased to a certain degree, the high-voltage input voltage is converted into stable low-voltage output voltage through the NMOS source electrode follower for output. The voltage input range of the circuit is increased through simple circuit design. The stable low-voltage power supply which can be used for other circuit modules in the chip is generated in a full-voltage range and can be used as a low-voltage power supply circuit or a starting circuit of the chip. In addition, the whole circuit of the power converter of the embodiment is of an open-loop structure, so that the stability problem does not exist, and the stability of the circuit is improved.

It should be noted that the words "during", "when" and "when 8230; \8230when" as used herein in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a start action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the start action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

In accordance with embodiments of the present invention, the foregoing examples are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined with reference to the appended claims and their equivalents.

Claims

1. A power converter, comprising:

a first transistor having a first doping type and a second transistor having a second doping type opposite to the first doping type, each transistor having a control terminal, a first terminal coupled to the input terminal, and a second terminal coupled to the output terminal; and

a mode switching circuit for turning on the first transistor and turning off the second transistor in a first mode so that the first transistor converts an input voltage into a first output voltage, and turning off the first transistor and turning on the second transistor in a second mode so that the second transistor converts the input voltage into a second output voltage, and the first output voltage and the second output voltage are both lower than the input voltage,

wherein the mode switching circuit comprises:

a bias current generating circuit including a third transistor for generating a bias current varying with the input voltage;

a pull-up circuit including a fourth transistor coupled between the input terminal and the control terminal of the first transistor, and a fifth transistor and a sixth transistor, a first terminal of the fifth transistor being coupled to the input terminal, a second terminal of the fifth transistor being coupled to a first terminal of the sixth transistor, a second terminal of the sixth transistor being grounded, a control terminal of the fourth transistor being coupled to the control terminal and the second terminal of the fifth transistor, a control terminal of the sixth transistor being coupled to a control terminal of the third transistor, the fourth transistor being configured to generate a first current; and

a pull-down circuit comprising a seventh transistor, a second current source, an eighth transistor, and a ninth transistor, wherein a first terminal of the second current source is coupled to a power voltage, a second terminal of the second current source is coupled to a first terminal and a control terminal of the eighth transistor, a second terminal of the eighth transistor is coupled to ground, the ninth transistor is coupled between a control terminal of the seventh transistor and ground, a control terminal of the seventh transistor is coupled to a control terminal of the eighth transistor, a control terminal of the ninth transistor is coupled to a control terminal of the third transistor, and the seventh transistor is configured to generate a second current,

wherein the first transistor is turned on or off according to a difference between the first current and the second current, and the second transistor is turned on or off according to a current value of the bias current.

2. The power converter of claim 1, wherein the mode switching circuit further comprises:

a first clamp circuit coupled between a first terminal and a control terminal of the first transistor and configured to generate a first clamp voltage at the control terminal of the first transistor; and

a second clamping circuit coupled between the control terminal of the second transistor and a ground terminal and configured to generate a second clamping voltage at the control terminal of the second transistor.

3. The power converter of claim 2, wherein the first clamp circuit and the second clamp circuit each comprise:

a plurality of transistors coupled in series, each transistor connected as a diode.

4. The power converter of claim 3, wherein the third transistor is further included in a plurality of transistors in the second clamp circuit,

the third transistor has a control terminal, a first terminal coupled to one of the plurality of transistors, and a second terminal coupled to a ground terminal, and the bias current generating circuit generates the bias current in common with the third transistor.

5. The power converter of claim 4, further comprising:

a first current source coupled between the input terminal and the second clamp circuit, the first current source for generating a first reference current.

6. The power converter of claim 1, wherein the mode switching circuit further comprises:

a hysteresis circuit coupled to the pull-up circuit and configured to provide a hysteresis current to the pull-up circuit.

7. The power converter of claim 6, wherein the hysteresis circuit comprises:

a tenth transistor having a control terminal coupled to the control terminal of the first transistor, a first terminal coupled to the input terminal, and a second terminal; and

an eleventh transistor having a control terminal coupled to the control terminal of the fifth transistor, a first terminal coupled to the second terminal of the tenth transistor, and a second terminal coupled to the control terminal of the eleventh transistor,

wherein the tenth transistor is used for generating the hysteresis current.

8. The power converter of claim 1, further comprising:

an auxiliary transistor having a first doping type has a control terminal coupled to the control terminal of the second transistor, a first terminal coupled to an output terminal, and a second terminal coupled to a ground terminal.

9. The power converter of claim 8, wherein the first doping type is P-type and the second doping type is N-type.

10. The power converter of claim 1, further comprising:

an auxiliary resistor coupled between the input terminal and the control terminal of the first transistor.

11. A control method for a power converter as claimed in any of claims 1 to 10, the power converter comprising a first transistor having a first doping type and a second transistor having a second doping type opposite to the first doping type, each transistor having a control terminal, a first terminal coupled to an input terminal, and a second terminal coupled to an output terminal,

wherein, the control method comprises the following steps:

turning on the first transistor and turning off the second transistor in a first mode so that the first transistor converts an input voltage into a first output voltage; and

turning off the first transistor and turning on the second transistor in a second mode so that the second transistor converts the input voltage to a second output voltage,

wherein the first mode and the second mode are changed according to a bias current varying with the input voltage, and the first output voltage and the second output voltage are both lower than the input voltage.

12. The control method of claim 11, wherein the first mode and the second mode changing according to a bias current varying with the input voltage comprises:

generating a first current and a second current according to the bias current, wherein the first current flows from the input end to the control end of the first transistor, and the second current flows from the control end of the first transistor to the ground end; and

turning on or off the first transistor according to a difference between the first current and the second current, and turning on or off the second transistor according to a current value of the bias current.

13. The control method according to claim 12, further comprising:

providing a first clamp circuit coupled between the input terminal and the control terminal of the first transistor and providing a first clamp voltage; and

and providing a second clamping circuit, wherein the second clamping circuit is coupled between the control end and the grounding end of the second transistor and provides a second clamping voltage.

14. The control method according to claim 13, further comprising:

a first reference current is provided between the input terminal and the control terminal of the second transistor, and a current value of the bias current is adjusted by the second clamp circuit according to the input voltage.

15. The control method according to claim 11, further comprising:

providing a hysteresis current for adjusting the first current to provide hysteresis in the changing of the first and second modes.

16. The control method according to claim 11, further comprising:

an auxiliary transistor having a first doping type is provided, the auxiliary transistor having a control terminal coupled to the control terminal of the second transistor, a first terminal coupled to an output terminal, and a second terminal coupled to a ground terminal.

17. The method of claim 16, wherein the first doping type is P-type and the second doping type is N-type.