CN114185837A

CN114185837A - System-on-Chip and Method of Regulating Voltage and Frequency

Info

Publication number: CN114185837A
Application number: CN202010967176.XA
Authority: CN
Inventors: 江鹏
Original assignee: Alibaba Group Holding Ltd
Current assignee: Alibaba Group Holding Ltd
Priority date: 2020-09-15
Filing date: 2020-09-15
Publication date: 2022-03-15
Anticipated expiration: 2040-09-15
Also published as: CN114185837B

Abstract

A system-on-chip and method of regulating voltage and frequency are provided. The processing unit is used to generate a frequency configuration instruction and a frequency modulation and voltage regulation instruction; the DVFS controller is used to generate at least one frequency-voltage pair according to the frequency configuration instruction, and the target frequency of the frequency modulation and voltage regulation instruction and the at least one frequency-voltage pair are selected. In a case where the frequencies match, the frequency modulation signal is generated based on the first frequency, the voltage modulation signal is generated based on the voltage corresponding to the first frequency, the frequency modulation signal is used to adjust the clock frequency of the system-on-chip, and the voltage-regulated signal is used to adjust the power supply voltage of the system-on-chip; On-chip bus, coupled to the processing unit and the DVFS controller. This application configures the allowable value range for the clock frequency and power supply voltage of the system. The frequency modulation and voltage regulation operation within the allowable value range can be carried out normally, and the frequency modulation and voltage regulation operation outside the allowable value range is rejected. In this way, the safety of frequency modulation and voltage regulation operation is improved.

Description

System on chip and method for adjusting voltage and frequency

Technical Field

The present disclosure relates to the field of chips, and more particularly, to a system on a chip and a method of adjusting voltage and frequency.

Background

The trend toward miniaturization of integrated circuits has empowered processor manufacturers on how to reduce power consumption. Dynamic Voltage and Frequency Scaling (DVFS) is one of the methods for processor power reduction. The dynamic voltage and frequency adjustment dynamically adjusts the clock frequency and the power supply voltage of the system according to different requirements of an application program operated by the processor on computing capacity, thereby achieving the purpose of energy conservation.

In the DVFS system, an application program can initiate a frequency modulation and voltage regulation request through a system interface, and a DVFS controller regulates the clock frequency and the power supply voltage of the system according to the frequency modulation and voltage regulation request. And the attack software can bring potential safety hazard to the system by utilizing the point. For example, attack software may initiate a fm-regulator request that contains a larger frequency and voltage that may cause a system crash if the clock frequency of the system is set to.

Disclosure of Invention

In view of the above, an object of the present disclosure is to provide a system on chip and a method for adjusting voltage and frequency, so as to solve the safety hazard of the frequency modulation and voltage adjustment operation of the system on chip.

In a first aspect, an embodiment of the present disclosure provides a system on a chip, including:

the processing unit is used for generating a frequency configuration instruction and a frequency and voltage adjusting instruction;

the DVFS controller is used for configuring at least one frequency-voltage pair according to a frequency configuration instruction, generating a frequency modulation signal based on a first frequency under the condition that the target frequency of the frequency modulation and voltage regulation instruction is consistent with the first frequency in the at least one frequency-voltage pair, and generating a voltage regulation signal based on the voltage corresponding to the first frequency, wherein the frequency modulation signal is used for regulating the clock frequency of the system on chip, and the voltage regulation signal is used for regulating the power supply voltage of the system on chip;

an on-chip bus coupling the processing unit and the DVFS controller.

Optionally, the DVFS controller generates an alert signal if the target frequency does not coincide with any of the at least one frequency voltage pair.

Optionally, the alarm signal is one of an interrupt signal, a reset signal or a bus error signal.

Optionally, the processing unit includes a secure environment and an insecure environment that are divided on hardware, and the processing unit generates the frequency configuration instruction in the secure environment and generates the frequency and voltage modulation instruction in the insecure environment.

Optionally, the processing unit switches between a user mode and a kernel mode, generates the frequency configuration instruction in the kernel mode, and generates the frequency and voltage modulation instruction in the user mode.

Optionally, the frequency configuration instruction includes an indication bit, where the indication bit is used to indicate state information when the processing unit generates the frequency configuration instruction, and the DVFS controller is further configured to: and determining whether to generate an alarm signal according to an indication bit in the frequency configuration instruction.

Optionally, the DVFS controller includes:

a plurality of register sets for storing at least one frequency-voltage pair;

the frequency conversion register is used for storing the target frequency;

a comparator for comparing the target frequency with the at least one frequency-voltage pair, respectively, and outputting a resultant signal;

the frequency conversion generating unit is used for generating the frequency modulation signal according to the result signal;

and the voltage generating unit is used for generating the voltage regulating signal according to the result signal.

Optionally, the DVFS controller includes:

an interrupt generating unit for generating an interrupt signal;

a reset generating unit for generating a reset signal;

a bus response unit for generating a bus error signal;

and the error detection unit is used for sampling the result signal and indicating one of the interrupt generation unit, the reset generation unit and the bus response unit to start according to the result signal.

Optionally, any one of the voltages in the at least one frequency voltage pair is a minimum voltage for the processing unit to operate at the corresponding frequency.

Optionally, the system on chip further includes a static storage unit configured to store a plurality of frequency-voltage pairs, and the processing unit generates the at least one frequency-voltage pair according to the plurality of frequency-voltage pairs.

In a second aspect, embodiments of the present disclosure provide a method for adjusting voltage and frequency, including:

generating a frequency configuration instruction and a frequency and pressure regulating instruction;

generating at least one frequency voltage pair according to the frequency configuration instruction;

comparing the target frequency in the frequency and voltage modulation instruction with the at least one frequency voltage pair;

and under the condition that the target frequency is consistent with a first frequency, adjusting the clock frequency of the system according to the first frequency, and adjusting the power supply voltage of the system according to the voltage corresponding to the first frequency.

Optionally, the method further comprises: and generating an alarm signal and carrying out alarm processing under the condition that the target frequency is not consistent with any frequency in the at least one frequency voltage pair.

Optionally, the frequency configuration instruction includes an indication bit, where the indication bit is used to indicate state information when the processing unit generates the frequency configuration instruction, and the method further includes: and determining whether to generate an alarm signal according to an indication bit in the frequency configuration instruction.

In a third aspect, an embodiment of the present disclosure provides a computing apparatus, including:

the system-on-chip of any of the above;

a bus;

a memory device coupled to the system on chip through the bus;

a power management circuit coupled to a DVFS controller in the system-on-chip.

According to the system on chip provided by the embodiment of the disclosure, the allowable value range is configured for the clock frequency and the power supply voltage of the system, the frequency and voltage regulation operation within the allowable value range can be normally performed, and the frequency and voltage regulation operation outside the allowable value range is refused to be performed, so that the safety of the frequency and voltage regulation operation is improved.

Drawings

The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following description of embodiments of the disclosure, which refers to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a system on a chip according to an embodiment of the present disclosure;

FIG. 2 is a graph of frequency and voltage;

fig. 3 is a schematic diagram of an exemplary structure of the DVFS controller of fig. 1;

FIG. 4 is a flow chart of a method of regulating voltage and frequency provided by an embodiment of the present disclosure;

FIG. 5 is a block diagram of a general-purpose computer system to which embodiments of the present disclosure are applied;

fig. 6 is a schematic structural diagram of an embedded system to which the embodiment of the present disclosure is applied.

Detailed Description

The present disclosure is described below based on examples, but the present disclosure is not limited to only these examples. In the following detailed description of the present disclosure, some specific details are set forth in detail. It will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the present disclosure. The figures are not necessarily drawn to scale.

System on chip of the disclosed embodiments

Fig. 1 is a schematic structural diagram of a system on chip 100 to which an embodiment of the present disclosure is applied.

Referring to the figures, an on-chip bus 102 couples various components together with the processing unit 101. An on-chip bus 102, such as an AXI bus. The AXI Bus is the most important part of the amba (advanced Microcontroller Bus architecture)3.0 and above protocol proposed by ARM corporation, and is an on-chip Bus oriented to high performance, high bandwidth, and low latency. The AIX bus separates address/control and data phases, supports unaligned data transmission, and simultaneously supports burst transmission and out-of-order transmission, thereby meeting the requirements of ultrahigh performance and complex system-on-chip design.

As shown, DVFS controller 103, high speed memory 104 are coupled to processing unit 101 via bus 102. The DVFS controller 103 is coupled to the clock management unit 105, the off-chip power management circuit 211, and in some embodiments, the power management circuit 211 may also be located in the system-on-chip 100. The system-on-chip 100 may further comprise interface circuitry, not shown, through which it is coupled to an off-chip external device. The external devices may be, for example, text, audio and video input/output devices and various other memories. The system-on-chip 100 may access off-chip external devices through the interface circuit. Unlike the high speed memory 104 provided on a system-on-chip, off-chip storage may be larger in capacity but slower and less costly. In some implementations, the high speed memory 104 may be Static Random Access Memory (SRAM) while the off-chip memory is DRAM (dynamic random access memory) and flash (flash) memory. Designers may also configure the SoC architecture so that communications between various elements in the system-on-chip are secure.

As shown, the system-on-chip 100 has embedded therein basic software (e.g., embedded control system 121) and applications (e.g., applications A-N). Still other applications, not shown, may be stored in memory external to system-on-chip 100, copied into high-speed memory 104 in system-on-chip 100 by interface circuitry for execution by processing unit 101, or to access resources on system-on-chip 100 by interface circuitry.

The DVFS controller 103 is operative to receive frequency configuration commands and fm regulator commands from the on-chip bus 102. The frequency configuration instructions include at least one frequency voltage pair. The fm regulator instructions include a target frequency. The DVFS controller 103 reads at least one frequency-voltage pair from the frequency configuration instructions and stores it as a frequency-voltage table 106 on the graph, each frequency-voltage pair characterizing a clock frequency and a corresponding supply voltage that the system can set. Meanwhile, the DVFS controller 103 obtains a target frequency from the fm/voltage regulation command, the DVFS controller 103 compares the target frequency with each frequency-voltage pair in the frequency-voltage meter 106, and when the frequency in a certain frequency-voltage pair matches the target frequency, the corresponding voltage is taken out to generate a voltage regulation signal REGV, which is sent to the power management circuit 211, the power management circuit 211 adjusts the supply voltage VCPU provided to the system accordingly, and at the same time, the DVFS controller 103 generates a fm signal REGF, which is sent to the clock management unit 105, and the clock management unit 105 generates a clock signal FCPU of the system. The DVFS controller 103 also refuses to perform the fm voltage adjustment operation and generates an ALARM signal ALARM when the target frequency does not coincide with any of the frequencies in the frequency voltmeter 106, and an ALARM processing unit (not shown) performs ALARM processing based on the ALARM signal ALARM.

The processing unit 101 is configured to generate frequency configuration instructions and fm and voltage regulation instructions, and more specifically, the processing unit 101 generates frequency configuration instructions and fm and voltage regulation instructions when executing executable code from the embedded control system 121 or the applications a-N. For example, the embedded control system 121 may include computer code for the following processes: firstly, collecting signals related to system load, and calculating the current system load; predicting the performance required by the system in the next time period according to the current load of the system; the predicted performance is then translated to a desired frequency and the system interface is then invoked to modify the clock frequency of the system to the desired frequency. The system interface is an interface provided by the embedded control system for calling the underlying hardware unit. When decoding and executing the computer code, the processing unit 101 generates the fm/fm instruction sent to the hardware DVFS controller by calling the system interface. . As another example, the processing unit 101 generates FM voltage regulation instructions in executing executable code in the applications A-N. The frequency allocation command is generated when the boot program is executed. The boot program is used to load the embedded operating system 121 after the computer is powered on. That is, the boot program is executed and generates the frequency configuration instruction during the period from when the computer is powered on to when the embedded operating system 121 is operating normally. This has the advantage that since the various interface circuits may not yet function properly when the boot program is running, it is not easy for external attack software to attack the frequency configuration instructions.

It should be noted that the frequency voltages specified in the frequency configuration command correspond to verified frequency voltage pairs that enable the system to operate properly.

In one implementation, SoC 100 includes a static memory cell that contains a number of frequency-voltage pairs, and the frequency-voltage pairs specified in the frequency configuration instructions are contained within the number of frequency-voltage pairs.

In another implementation, fig. 2 is taken as an example. Fig. 2 shows a plot Curve1 of frequency and voltage. Each point of Curve1 represents a minimum voltage for a frequency corresponding to that frequency. The frequency configuration command may configure the frequency voltage pairs in the DVFS controller 103 using operating points (f0, v0) - (f4, v4) on Curve 1. The frequency configuration instructions may also select, for example, (f0, V11) and (f2, V12) on the graph to configure the frequency voltage pairs in the DVFS controller 103, where V11 is greater than V0 and V12 is greater than V2, in which case the supply voltage provided to the system will retain margin. Of course, the range of voltages that the power management circuit can provide needs to be considered.

In further implementations, the execution environment of computer instructions by the processing unit 101 may be divided on a hardware basis into a secure environment 1011 and a non-secure environment 1012. The secure environment 1011 is a more trusted instruction execution environment than the non-secure environment 1012, e.g., the secure environment 1011 is not externally accessible, the non-secure environment 1012 is externally accessible, the secure environment includes hardware protection mechanisms at the input and output interfaces, such as registers for filtering authenticated or unauthenticated data, and communication with the secure environment may be based on cryptographic algorithms, etc. Alternatively, the processing unit 101 generates a frequency configuration command in the secure environment 1011 and a frequency and voltage modulation command in the non-secure environment 1012.

In further implementations, the execution environment of the processing unit 101 for computer instructions may be partitioned into a user state and a kernel state based on software. The user mode and the kernel mode come from a multi-user management mode. The multi-user management mode at least comprises two user types: a general-authority user and a highest-authority user. Based on the multi-user management mode, the addressing space of the memory is logically divided into kernel space and user space in software, for example, in the case of a Linux operating system, the highest 1 gigabyte (from virtual address 0xC0000000 to 0 xffffffffff) is used as the kernel space, and the lower 3 gigabyte (from virtual address 0x00000000 to 0xFFFFFFFF) is used as the user space. If an application program is executed by an ordinary user, the code and data of the application program are loaded into a user space to be executed, and if the application program is executed by a highest authority user, the code and data of the application program are loaded into a kernel space to be executed. Thus, when a processor processes code in kernel space, its mode of operation is referred to as kernel mode, and when a processor processes code in user space, its mode of operation is referred to as user mode. Optionally, the processing unit 101 generates a frequency configuration instruction in a kernel mode, and generates a frequency and voltage modulation instruction in a user mode.

Under normal conditions, the processing unit 101 generates the frequency configuration instruction only in the secure environment or the kernel mode, and generates the frequency and voltage modulation instruction only in the non-secure environment or the user mode, thereby ensuring the safety of the frequency and voltage modulation operation. The attack program can still destroy the generation process of the frequency configuration instruction, for example, by causing the processing unit 101 to generate the frequency configuration instruction in an insecure environment through an illegal computer instruction, and tamper with the frequency voltage pair in the frequency configuration instruction.

To this end, in a further implementation, the frequency configuration instruction includes an indication bit for indicating status information of the processing unit 101 when the frequency configuration instruction is generated. For example, a value of 0 indicates that the processing unit 101 is in a secure environment, and a value of 1 indicates that the processing unit 101 is in an unsecure environment, or a value of 0 indicates that the processing unit 101 is in a kernel state, and a value of 1 indicates that the processing unit 101 is in a user state. Thus, the DVFS controller 103 may determine whether the processing unit 101 generates the frequency configuration instruction in a correct state (i.e., a secure environment or a kernel state) by detecting the indication bit. If the AVFS controller 103 determines that the processing unit 101 generates the frequency configuration instruction in the correct state according to the indication bit, frequency configuration is performed. If the AVFS controller 103 determines that the processing unit 101 generates the frequency configuration instruction in an error state according to the indication bit, the frequency configuration is refused to be executed and an alarm signal is given, and then the alarm processing unit performs alarm processing according to the alarm signal. Thus, even if an attack program can disrupt the generation process of the frequency configuration instruction, the AVFS controller 103 cannot complete the frequency configuration.

Fig. 3 is a schematic diagram of an exemplary DVFS controller 300. As shown, register F is used to store the target frequency. Register sets F-V are used to store a plurality of frequency voltage pairs. The plurality of comparators 303 are configured to compare the target frequency in the register F with the frequency-voltage pairs in the register sets F-V, and if they match, the voltage generating unit 302 generates the voltage regulating signal REGV, and the frequency conversion generating unit 301 generates the frequency modulation signal FCPU, and if the error detecting unit 304 detects that the target frequency does not match any of the frequencies in any of the frequency-voltage pairs, the interrupt generating unit 305, the RESET generating unit 306, or the bus response unit 307 may generate the interrupt signal SINT, the RESET signal RESET, or the bus error signal SBUS. The error detection unit 304 is also used for detecting an indication bit in the frequency allocation instruction. An interrupt signal SINT, a RESET signal RESET or a bus error signal SBUS is given according to the indication bit.

The interrupt signal SINT is processed by an interrupt controller (not shown). An interrupt controller, which may be provided inside or outside the processing unit 301, defines various processing routines for various interrupt signals, and when a corresponding interrupt signal occurs, the corresponding processing routine is initiated to perform corresponding processing. The RESET signal RESET is sent to a RESET circuit (not shown) which RESETs the system-on-chip 300 and then restarts the system-on-chip. The bus error signal SBUS is sent to the bus 302 for processing.

In one implementation, the error detection unit 304 is further configured to detect an indication bit of the frequency configuration instruction to determine whether the state of the processing unit is normal when the frequency configuration instruction is generated, and if not, enable the interrupt generation unit 305, the RESET generation unit 306, or the bus response unit 307 to generate the interrupt signal SINT, the RESET signal RESET, or the bus error signal SBUS.

According to the system on chip of the embodiment of the disclosure, an allowed value range is configured for the clock frequency and the power supply voltage of the system, the frequency modulation and voltage regulation operation of the clock frequency and the power supply voltage can be normally performed within the allowed value range, and the frequency modulation and voltage regulation operation outside the allowed value range is refused to be performed and an alarm signal is generated.

Method for adjusting voltage and frequency of disclosed embodiment

FIG. 4 shows a flow chart of a method of regulating voltage and frequency of an embodiment of the present disclosure. The method can be implemented by a software program or by a software program and a hardware module together. As shown on the figure, the method comprises the following steps.

In step S400, a frequency configuration instruction is generated in the secure environment. The step is completed by the processing unit, and a frequency configuration instruction is generated by acquiring a plurality of pre-stored frequency voltage pairs, wherein the frequency configuration instruction comprises at least one frequency voltage pair.

In step S401, at least one frequency voltage pair is generated according to the frequency configuration command. This step may be performed by the DVFS controller, i.e., the DVFS controller receives the frequency configuration command, reads at least one frequency voltage pair therefrom, and stores the frequency voltage pair in the DVFS controller.

In step S402, a fm regulator command is generated in an unsafe environment. The step is completed by the processing unit, for example, by predicting the load condition of the next cycle of the system, determining the clock frequency required by the processing unit, generating the frequency and voltage modulation instruction according to the required clock frequency, and using the required clock frequency as the target frequency in the frequency and voltage modulation instruction.

In step S403, the target frequency in the fm regulator command is compared with at least one frequency voltage pair. This step may be performed by the DVFS controller. The target frequency is compared with the frequency in the frequency-voltage pair obtained via step S401 by the comparator.

In step S404, whether the target frequency coincides with the first frequency. The first frequency is any one of the at least one frequency voltage pair. If the target frequency coincides with the first frequency, step S405 is performed, otherwise step S406 is performed.

In step S405, the clock frequency is adjusted according to the first frequency, and the power supply voltage is adjusted according to the voltage corresponding to the first frequency.

In step S406, an alarm signal is generated and alarm processing is performed.

In this embodiment, at least one frequency-voltage pair is configured to limit the clock frequency of the system and the allowable value range of the supply voltage provided to the system, if the frequency regulation instruction is adjusted within the allowable value range for the clock frequency of the system, the frequency and voltage can be normally adjusted, and if the frequency regulation instruction is outside the allowable value range, the frequency and voltage are rejected to be executed and alarm processing is performed, so that the safety of the system is improved.

Further, the alarm signal generated in step S406 may be one of an interrupt signal, a reset signal or a bus error signal. Different processing is performed for different alarm signals. For example, interrupt handling routines in the embedded control system may be employed to handle interrupt signals and reset signals.

As another implementation, the frequency configuration instruction and the frequency voltage regulation instruction are generated in different modes of a processor (including a central processing unit, a microprocessor, and a digital signal processing unit), for example, an operation of generating the frequency configuration instruction in a core mode, and an operation of generating the frequency voltage regulation instruction in a user mode.

Specific application of system on chip

FIG. 5 illustrates a general computer architecture to which embodiments of the disclosure may be applied. As shown, computer system 500 may include one or more processors 12, and memory 14. The system on chip provided in the above embodiments may be used as the processor 12.

The memory 14 in the computer system 500 may be a main memory (referred to simply as main memory or memory). For storing instruction information and/or data information represented by data signals, such as data provided by the processor 12 (e.g., operation results), and for implementing data exchange between the processor 12 and an external storage device 16 (or referred to as an auxiliary memory or an external memory).

In some cases, processor 12 may need to access memory 14 to retrieve data in memory 14 or to make modifications to data in memory 14. To alleviate the speed gap between processor 12 and memory 14 due to the slow access speed of memory 14, computer system 500 further includes a cache memory 18 coupled to bus 11, cache memory 18 being used to cache some data in memory 14, such as program data or message data, that may be repeatedly called. The cache Memory 18 is implemented by a storage device such as a Static Random Access Memory (SRAM). The Cache memory 18 may have a multi-level structure, such as a three-level Cache structure having a first-level Cache (L1 Cache), a second-level Cache (L2 Cache), and a third-level Cache (L3 Cache), or may have a Cache structure with more than three levels or other types of Cache structures. In some embodiments, a portion of the cache memory 18 (e.g., a level one cache, or a level one cache and a level two cache) may be integrated within the processor 12 or in the same system on a chip as the processor 12.

In this regard, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and so on. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory, where the write access request specifies write data and a corresponding physical address that need to be written into the memory; the memory management unit 122 is configured to translate the virtual addresses specified by the instructions into the physical addresses mapped by the virtual addresses, and the physical addresses specified by the write access request may be consistent with the physical addresses specified by the corresponding instructions.

The information exchange between the memory 14 and the cache 18 is typically organized in blocks. In some embodiments, the cache 18 and the memory 14 may be divided into data blocks by the same spatial size, and a data block may be the smallest unit of data exchange (including one or more data of a preset length) between the cache 18 and the memory 14. For the sake of brevity and clarity, each data block in the cache memory 18 will be referred to below simply as a cache block (which may be referred to as a cacheline or cache line), and different cache blocks have different cache block addresses; each data block in the memory 14 is referred to as a memory block, and different memory blocks have different memory block addresses. The cache block address comprises, for example, a physical address tag for locating the data block.

Due to space and resource constraints, the cache memory 18 cannot cache the entire contents of the memory 14, i.e., the storage capacity of the cache memory 18 is generally smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to the entire memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, firstly, the cache memory 18 is accessed through the bus 11 to judge whether the content to be accessed is stored in the cache memory 18, if so, the cache memory 18 hits, and at the moment, the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to look up the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, the efficiency of the processor 12 can be significantly improved when the cache memory 18 hits, thereby also improving the performance and efficiency of the overall computer system 500.

In addition, computer system 500 may also include input/output devices such as storage device 16, display device 13, audio device 19, mouse/keyboard 15, and the like. The storage device 16 is a device for information access such as a hard disk, an optical disk, and a flash memory coupled to the bus 11 via corresponding interfaces. The display device 13 is coupled to the bus 11, for example via a corresponding graphics card, for displaying in accordance with display signals provided by the bus 11.

The computer system 500 also typically includes a communication device 17 and thus may communicate with a network or other devices in a variety of ways. The communication device 17 may comprise, for example, one or more communication modules, by way of example, the communication device 17 may comprise a wireless communication module adapted for a particular wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication in compliance with the 802.11 standard established by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication conforming to a cellular or other wireless wide area protocol; the communication device 17 may also include a communication module using other protocols, such as a bluetooth module, or other custom type communication modules; the communication device 17 may also be a port for serial transmission of data.

Of course, the structure of different computer systems may vary depending on the motherboard, operating system, and instruction set architecture. For example, many computer systems today have an input/output control hub coupled between the bus 11 and various input/output devices, and the input/output control hub may be integrated within the processor 12 or separate from the processor 12.

Fig. 6 is a block diagram of an embedded system to which an embodiment of the present disclosure is applied. The above embodiments provide a system on a chip as the processor 601.

Although the embedded system has a high similarity to a computer system in terms of hardware structure, the application characteristics of the embedded system cause the embedded system to be greatly different from a general computer system in terms of the composition and implementation form of hardware.

First, in order to meet the requirements of the embedded system 600 on speed, volume and power consumption, data that needs to be stored for a long time, such as an operating system, application software, and special data, is usually not used in a storage medium with a large capacity and a low speed, such as a magnetic disk, but a random access Memory 602 or a Flash Memory (Flash Memory)603 is mostly used.

In addition, in the embedded system 600, an a/D (analog/digital conversion) interface 605 and a serial interface 606 are required for the need of measurement and control, which is rarely used in general-purpose computers. The a/D interface 605 mainly performs conversion of an analog signal to a digital signal and conversion of a digital signal to an analog signal required in the test. The embedded system 600 often requires testing when applied to industrial production. Since the single chip generates a digital signal and needs to be converted into an analog signal for testing during testing, unlike a general-purpose computer, an a/D (analog/digital conversion) interface 605 is required to complete the related conversion. In addition, the industry often requires multiple embedded systems to be connected in series to perform related functions, and therefore a serial interface 606 for connecting multiple embedded systems in series is required, which is not required in general purpose computers.

In addition, the embedded system 600 is a basic processing unit, and it is often necessary to connect a plurality of embedded systems 600 into a network in industrial design, so that a network interface 607 for connecting the embedded system 600 into the network is required. This is also mostly not required in general purpose computers. In addition, some embedded systems 600 employ an external bus 604, depending on the application and size. With the rapid expansion of the application field of the embedded system 600, the embedded system 600 tends to be personalized more and more, and the types of buses adopted according to the characteristics of the embedded system 600 are more and more. In addition, in order to test the internal circuit of the embedded processor 601, the boundary scan test technology is commonly used in the processor chip. To accommodate this testing, a debug interface 608 is employed.

With the rapid development of Very Large Scale integrated circuits (Very Large Scale Integration) and semiconductor processes, part or all of the embedded system can be implemented on a silicon chip, i.e., an embedded system on a chip (SoC).

Commercial value of the disclosed embodiments

The system on chip provided by the embodiment of the disclosure reduces the system power consumption on the basis of ensuring the safety of frequency modulation and voltage regulation operations, and can form a computing device used in various scenes, such as a cloud server with a huge number of data centers, and in this scene, the power consumption of each cloud server is reduced by reducing the power consumption of a processor, so that the operation cost of each cloud server and the whole data center is reduced; as another example, in the case of a very small electronic product used in daily life, the capacity of a battery that can be carried is limited due to size limitation, and therefore, it is necessary to reduce power consumption of the electronic product to contribute to the prolongation of the usage time of the electronic product. Therefore, the system on chip and the computing device constructed by the system on chip have commercial value and economic value on the basis of practical value.

As will be appreciated by one skilled in the art, the present disclosure may be embodied as systems, methods and computer program products. Accordingly, the present disclosure may be embodied in the form of entirely hardware, entirely software (including firmware, resident software, micro-code), or in the form of a combination of software and hardware. Furthermore, in some embodiments, the present disclosure may also be embodied in the form of a computer program product in one or more computer-readable media having computer-readable program code embodied therein.

Any combination of one or more computer-readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium is, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer-readable storage medium include: an electrical connection for the particular wire or wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical memory, a magnetic memory, or any suitable combination of the foregoing. In this context, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with a processing unit, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a chopper. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any other suitable combination. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

Computer program code for carrying out embodiments of the present disclosure may be written in one or more programming languages or combinations. The programming language includes an object-oriented programming language such as JAVA, C + +, and may also include a conventional procedural programming language such as C. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A system on a chip, comprising:

an on-chip bus coupling the processing unit and the DVFS controller.

2. The system on a chip of claim 1, wherein the DVFS controller generates an alert signal if the target frequency does not coincide with any of the at least one frequency voltage pair.

3. The system on a chip of claim 2, wherein the alarm signal is one of an interrupt signal, a reset signal, or a bus error signal.

4. The system on a chip of claim 1, wherein the processing unit comprises a secure environment and an insecure environment divided in hardware, the processing unit generating the frequency configuration instructions in the secure environment and the frequency and voltage modulation instructions in the insecure environment.

5. The system on a chip of claim 1, wherein the processing unit switches between a user mode and a kernel mode, and generates the frequency configuration instructions in the kernel mode and the fm regulator instructions in the user mode.

6. The system on a chip of claim 1, the frequency configuration instruction comprising an indication bit to indicate state information when the processing unit generates the frequency configuration instruction, the DVFS controller further to: and determining whether to generate an alarm signal according to an indication bit in the frequency configuration instruction.

7. The system on a chip of claim 1, the DVFS controller comprising:

a plurality of register sets for storing at least one frequency-voltage pair;

the frequency conversion register is used for storing the target frequency;

8. The system on a chip of claim 3, the DVFS controller comprising:

an interrupt generating unit for generating an interrupt signal;

a reset generating unit for generating a reset signal;

a bus response unit for generating a bus error signal;

9. The system on a chip of claim 1, any one of the at least one frequency-voltage pair being a minimum voltage for the processing unit to operate at a corresponding frequency.

10. The system-on-chip of claim 1, further comprising a static storage unit to store a plurality of frequency voltage pairs, the processing unit to generate the at least one frequency voltage pair from the plurality of frequency voltage pairs.

11. A method of regulating voltage and frequency, comprising:

12. The method of claim 11, further comprising: and generating an alarm signal and carrying out alarm processing under the condition that the target frequency is not consistent with any frequency in the at least one frequency voltage pair.

13. The method of claim 11, wherein the frequency configuration instruction includes an indication bit to indicate status information when the processing unit generates the frequency configuration instruction, the method further comprising: and determining whether to generate an alarm signal according to an indication bit in the frequency configuration instruction.

14. A computing device, comprising:

the system on chip of any of claims 1 to 10;

a bus;

a memory device coupled to the system on chip through the bus;

a power management circuit coupled to the DVFS controller.