CN114175507A

CN114175507A - Unbalanced fault detection circuit

Info

Publication number: CN114175507A
Application number: CN201980098580.3A
Authority: CN
Inventors: 田内宏宪; 伊藤勇辉; 兵头贵志
Original assignee: Omron Corp
Current assignee: Omron Corp
Priority date: 2019-08-07
Filing date: 2019-08-07
Publication date: 2022-03-11
Also published as: US11984880B2; JPWO2021024432A1; WO2021024432A1; EP4012925A4; US20220294440A1; JP7405143B2; EP4012925A1

Abstract

An unbalanced fault detection circuit according to one aspect of the present disclosure is used to detect unbalanced faults in electronic equipment including a plurality of current paths each including electronic equipment and connected in parallel, and the unbalanced fault detection circuit includes: a detection unit; a plurality of coils arranged so as to surround the plurality of current paths and connected in series, the detection unit outputs a sum of induced voltages of the plurality of coils based on currents flowing in the plurality of current paths, that is, a coil sum voltage; and a control unit , when the coil and the voltage from the detection unit exceed the range of the predetermined value, the unbalanced failure of the electronic equipment is detected.

Description

Unbalanced fault detection circuit

Technical Field

The present disclosure relates to an unbalance fault detection circuit that detects an unbalance fault of an electronic apparatus including an electronic apparatus as a semiconductor switching element, for example, and an electronic apparatus including the unbalance fault detection circuit.

Background

The problem of patent document 1 is that, in an apparatus having a configuration in which a plurality of semiconductor switching elements connected in parallel are simultaneously operated by an operation signal from a common drive circuit, the occurrence of an overcurrent in any one of the semiconductor switching elements can be reliably detected by a simple circuit.

In patent document 1, when a plurality of (e.g., two) IGBTs are connected in parallel and a common drive signal is given thereto by a gate drive circuit, a gate current detector is inserted in each wiring between the gate drive circuit and each IGBT. When an overcurrent flows through any of the IGBTs, the polarity of the detection current detected by the polarity detector and the exclusive-or element differs between the gate current detection units, and the occurrence of an arm short-circuit current is detected. Alternatively, a circuit is added which detects that either of the detection currents between the two gate current detectors exceeds a predetermined value by the overcurrent detector and the logical sum element, and the occurrence of the arm short-circuit current is detected by calculating the logical product of the output of the logical sum element and the output of the exclusive or element by the logical product element.

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication No. 10-042546

Disclosure of Invention

Technical problem to be solved by the invention

The circuit of patent document 1 has a large number of components, and is difficult to be miniaturized.

The invention discloses an unbalance fault detection circuit of an electronic equipment device, which can detect unbalance faults of the electronic equipment with less components compared with the prior art.

Means for solving the problems

An unbalanced fault detection circuit according to an aspect of the present disclosure is an unbalanced fault detection circuit for detecting an unbalanced fault in an electronic device apparatus including a plurality of current paths, each of the plurality of current paths including an electronic device and being connected in parallel, the unbalanced fault detection circuit including: a detection unit having a plurality of coils arranged so as to surround the plurality of current paths, respectively, and connected in series, the detection unit outputting a coil sum voltage that is a sum of induced voltages of the plurality of coils based on currents flowing through the plurality of current paths; and a control unit for detecting an imbalance failure of the electronic device when the coil voltage from the detection unit exceeds a predetermined value range.

Effects of the invention

According to the unbalance fault detection circuit of the present disclosure, an unbalance fault can be detected with a smaller number of components compared to the related art.

Drawings

Fig. 1 is a block diagram showing a configuration example of a failure detection system 10 according to embodiment 1.

Fig. 2 is a timing chart showing an example of waveforms of signals and the like in each part of the failure detection system 10 in fig. 1.

Fig. 3 is a timing chart showing another example of waveforms of signals and the like in each part of the failure detection system 10 in fig. 1.

Fig. 4 is a timing chart showing another example of waveforms of signals and the like in each part of the failure detection system 10 in fig. 1.

Fig. 5 is a plan view showing an example of mounting the failure detection system 10 of fig. 1 on a printed circuit board 500.

Fig. 6 is a cross-sectional view of the printed circuit board 500 of fig. 5 cut by a broken line VI-VI'.

Fig. 7 is a cross-sectional view of the green sheet 500 of fig. 5 cut by a broken line VII-VII'.

Fig. 8 is a block diagram showing a configuration example of the failure detection system 10A according to embodiment 2.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described below are merely illustrative of the present invention in all respects. Of course, various modifications and alterations can be made without departing from the scope of the present invention. That is, when the present invention is implemented, the specific configuration according to the embodiment can be appropriately adopted. In the appended drawings, the same or similar structures are denoted by the same reference numerals.

(embodiment mode 1)

Fig. 1 is a block diagram showing a configuration example of a failure detection system 10 according to embodiment 1. In fig. 1, the fault finding system 10 is a fault finding system 10 for an electronic equipment device including two current paths into which switching elements Q1, Q2 are respectively inserted, and the fault finding system 10 includes a direct current source 20, a drive signal oscillator 30, switching elements Q1, Q2 connected in parallel, and a fault finding circuit 100. The failure detection circuit 100 includes a detection unit 110 having two

coils

111 and 112 connected in series, and a control unit 120.

In fig. 1, a dc current source 20 is a power source that outputs a dc input current Iin and supplies power. The drive signal oscillator 30 controls the switching of the switching elements Q1 and Q2 with the same drive signal Sdrv. The switching elements Q1 and Q2 are semiconductor switching elements such as MOSFETs, for example, and are controlled by the switching element drive signal Sdrv to switch the on state. That is, the currents I1 and I2 flowing through the current paths including the switching elements Q1 and Q2 are 0 when the drive signal Sdrv is at a low level and are maximized when the drive signal Sdrv is at a high level.

Coils

111 and 112 of detection unit 110 are disposed so as to surround the vicinities of the two current paths, respectively, and induced voltages are generated by currents I1 and I2. The control unit 120 detects that an unbalanced fault occurs in the electronic device when the sum of the induced voltages of the

coils

111 and 112, that is, the coil sum voltage Vc, is greater than a predetermined threshold Vth or less than-Vth. Here, the unbalanced fault is a current having a current ratio deviated from a normal predetermined current ratio flowing through a group of a plurality of current paths of the electronic equipment device, and includes the following three types.

(1) A first imbalance fault in which the resistance value of one of the switching elements Q1 and Q2 is different from that of the other, and the currents I1 and I2 are not equal to each other.

(2) A short-circuit fault occurs in any one of the switching elements Q1, Q2, and a second unbalance fault in which the currents I1, I2 flowing in the current paths of the short-circuit-failed switching elements Q1, Q2, of the currents I1, I2, increase.

(3) An open fault occurs in any of the switching elements Q1, Q2, and a third imbalance fault occurs in which, of the currents I1, I2, the currents I1, I2 flowing in the current paths of the switching elements Q1, Q2 in which an open fault has not occurred sharply increase.

When the control unit 120 detects an imbalance fault, the stop signals Sc20 and Sc30 are output to the dc current source 20 and the drive signal oscillator 30, and the operations of the dc current source 20 and the drive signal oscillator 30 are stopped.

The operation of the failure detection system 10 configured as described above will be described below.

In the failure detection system 10 of fig. 1, the

coils

111 and 112 have the same number of turns and are wound in opposite directions, and are disposed in the vicinity of current paths of currents flowing through the switching elements Q1 and Q2, respectively.

The induced voltages generated in the

coils

111, 112 by the currents I1, I2 are proportional to the slope of the change in the magnetic flux passing inside the windings of the

coils

111, 112, and the magnetic flux generated by the currents I1, I2 is proportional to the currents I1, I2. Therefore, when the switching elements Q1 and Q2 normally operate, the values of the currents I1 and I2 are always equal, and therefore the induced voltages in the

coils

111 and 112 are equal and opposite in direction. Thereby, the two induced voltages cancel each other, and the value of the coil and the voltage Vc becomes 0.

Fig. 2 is a timing chart showing an example of waveforms of signals and the like in each part of the failure detection system 10 in fig. 1. In fig. 2, time t10 to t29 represent the time of the switching operation of the failure detection system 10. The time T10 to T17 are a period T1 of steady operation in which the currents I1 and I2 are equal, the time T20 to T28 are a period T2 of steady operation in which the currents I1 and I2 are unequal, and the time T29 and thereafter are a stop period T3 in which the operation of the switching elements Q1 and Q2 is stopped in order to detect the "first imbalance fault".

In fig. 2, at time t10 to t11, the switching element drive signal Sdrv from the drive signal oscillator 30 rises, and the currents I1 and I2 start to flow through the switching elements Q1 and Q2. Since the switching elements Q1 and Q2 are controlled by the same switching element drive signal Sdrv and the currents I1 and I2 increase at the same slope, the induced voltages generated by the

coils

111 and 112 cancel each other out, and the value of the coil and the voltage Vc becomes 0. At time t11, the switching element driving signal Sdrv becomes high, and the increase of the currents I1 and I2 stops.

At time t11 to t12, since the currents I1 and I2 flowing through the switching elements Q1 and Q2 do not change, induced voltages are not generated in the

coils

111 and 112, and the value of the coil sum voltage Vc becomes 0. At time t12 to t13, switching element drive signal Sdrv falls and currents I1 and I2 decrease. Induced voltages are generated in the

coils

111 and 112 in the opposite direction from the time t10 to t11, but these induced voltages cancel each other out, and the value of the coil and the voltage Vc becomes 0. At time t13 to t14, the switching element drive signal Sdrv is low, and the switching elements Q1 and Q2 are in an insulated state, so that the currents I1 and I2 are 0, and the coil sum voltage Vc is 0. The times t14 to t17 are repetitions of the times t10 to t 13. In this manner, the coil and the voltage Vc are always at the zero level in the period T1.

At time t20, the same control as at times t10 to t13 is started, but the above-described "first imbalance fault" occurs, and the current I1 is larger than the current I2. Due to the difference between the currents I1 and I2, the slopes of the changes in the currents I1 and I2 from time t20 to t21 also differ, and the slope of the current I1 is larger than the slope of the current I2. Therefore, the induced voltage generated in the coil 111 is larger than the induced voltage of the coil 112, and the coil sum voltage Vc is a positive value. However, the difference between the slopes of the currents I1 and I2 is smaller as the coil and the voltage Vc exceed the threshold Vth, and thus the controller 120 does not detect an unbalanced fault.

At times t21 to t22, the values of currents I1 and I2 are kept constant, and the values of the coil and voltage Vc are 0, as in times t11 to t 12. At times t22 to t23, currents I1 and I2 decrease, and induced voltages are generated in

coils

111 and 112, as in the case of times t12 to t 13. Since the induced voltage of the coil 111 is larger than the induced voltage of the coil 112, the coil sum voltage Vc has a negative value (opposite to the values from time t20 to t 21). However, this value is not lower than the threshold voltage-Vth, and the control unit 120 does not detect the imbalance failure. The times t24 to t27 are repetitions of the times t20 to t 23. As described above, the "first imbalance fault" occurs in the period T2, and thus the coil and the voltage Vc become non-zero levels at the timing of the rise and fall of the switching element drive signal Sdrv. However, since the values of the coil and the voltage Vc always satisfy the expression-Vth < Vc < Vth, the control unit 120 does not detect the first unbalance failure.

At time t28, the degree of the "first imbalance fault" described above deteriorates, and the difference between the slopes of the changes in the currents I1, I2 becomes larger than the value at time t 20. At time t28 to t29, the coil sum voltage Vc becomes larger than the values at times t20 to t21, and exceeds the threshold Vth at time t 29. The control portion 120 ascertains "the first unbalance failure" in response to the coil and the voltage Vc exceeding the threshold Vth, and transmits the transmission stop signal Sc30 to the drive signal oscillator 30. At time t30, the drive signal oscillator 30 stops the output of the switching element drive signal Sdrv in response to the stop signal Sc30, whereby the switching elements Q1 and Q2 are turned off, and the operation of the failure detection system 10 is stopped. In this manner, during the period T3, the degree of "first imbalance fault" is deteriorated, and the coil and the voltage Vc become smaller than-Vth or larger than Vth. In response to this, the control section 120 stops the output of the switching element drive signal Sdrv in the drive signal generation section.

As described above, a difference occurs between the currents I1 and I2 due to the failure of the switching elements Q1 and Q2, and the failure detection system 10 detects an unbalanced failure in response to the coil and the voltage Vc exceeding the voltage value range-Vth to Vth, and stops the operation of the switching elements Q1 and Q2.

Fig. 3 is a timing chart showing another example of waveforms of signals and the like in each part of the failure detection system 10 in fig. 1. In the example of fig. 3, the deterioration of the "first imbalance fault" in the period T2 is different in the aspect of being generated during the on period of the switching element driving signal Sdrv, compared to the example of fig. 2. In fig. 3, the operations from time t10 to time t27 are the same as those in fig. 2, and therefore, the description thereof is omitted. The operations from time T31 to T32 are the same as those from time T20 to T21, and a "first imbalance fault" occurs in period T2.

In fig. 3, at time t33, the degree of "first unbalance fault" deteriorates, and the current I2 that has flowed starts to decrease simultaneously with the current I1 starting to increase sharply. Therefore, a very large induced voltage is generated in the coil 111, while an induced voltage in the opposite direction to the direction from time t10 to t11 is generated in the coil 112. Since the direction of the current I2 is opposite to the period T1, the induced voltages of the two

coils

111 and 112 are in the same direction and do not cancel each other out. Accordingly, at time t34, the coil sum voltage Vc of the two

coils

111 and 112 exceeds the threshold Vth, and the controller 120 detects the "second imbalance fault" and stops the driving signal oscillator 30 and the switching elements Q1 and Q2 (the same as time t29 in fig. 2). Thus, at time t35, the operation of the failure detection system 10 is stopped (the same as at time t30 in fig. 2).

In this manner, even in the period in which the switching element drive signal Sdrv is at the high level, the fault detection system 10 detects an unbalanced fault in response to the coil and the voltage Vc exceeding the voltage value range-Vth to Vth, and stops the switching element drive signal Sdrv input to the switching elements Q1, Q2, thereby stopping the operations of the switching elements Q1, Q2. The "third imbalance fault" can be detected and stopped in the same manner.

Fig. 4 is a timing chart showing another example of waveforms of signals and the like in each part of the failure detection system 10 in fig. 1. The example of fig. 4 differs from the example of fig. 3 in that the short-circuit state is maintained even when the switching element driving signal Sdrv is stopped due to the short-circuit failure of the switching element Q1. In fig. 4, the operations from time t10 to time t32 are the same as those in fig. 3, and therefore, the description thereof is omitted.

In fig. 4, at time t40, the controller 120 detects that the values of the coil and the voltage Vc exceed the voltage values ranging from-Vth to-Vth, and outputs the stop signals Sc20 and Sc30 to the dc current source 20 and the drive signal oscillator 30. Thereby, the switching element Q2 is stopped, but the switching element Q1 maintains a short-circuited state. Therefore, the switching element Q1 remains in a state where the current I1 flows, without being stopped, as at time t34 in fig. 3. Then, at time t42, the dc current source 20 receives the stop signal Sc20 to set the input current Iin to 0, and stops the current flowing through the short-circuit-failure switching element Q1.

As described above, the failure detection circuit 100 according to embodiment 1 is, for example, an unbalanced failure detection circuit used in an electronic device including a plurality of current paths into which electronic devices such as the switching elements Q1 and Q2 are inserted, and the failure detection circuit 100 includes: a detector 110 configured such that, when the switching elements Q1, Q2 are operating normally, the sum voltage Vc of the voltages induced in the

coils

111, 112 is substantially 0; and a control unit 120 for detecting an unbalanced failure of the electronic device when the sum voltage Vc of the induced voltages of the

coils

111 and 112 exceeds a range of values deviated to positive and negative by a predetermined width (threshold value Vth) from 0. When an imbalance fault of the electronic equipment is detected, such as an open fault or a short fault of the switching elements Q1 and Q2, the control unit 120 stops the dc current source 20 and the drive signal oscillator 30, thereby stopping the currents I1 and I2 flowing through the switching elements Q1 and Q2. The detection unit 110 is configured by only two

coils

111 and 112, and the value detected by the control unit 120 is only the coil and the voltage Vc, so that the failure detection system 10 can detect the imbalance failure with a configuration having a small number of components.

Fig. 5 is a plan view showing an example of mounting the failure detection system 10 of fig. 1 on a printed circuit board 500. Fig. 6 is a cross-sectional view of the printed circuit board 500 of fig. 5 cut along a plane passing through VI-VI ', and fig. 7 is a cross-sectional view of the printed circuit board 500 of fig. 5 cut along a plane passing through VII-VII'. In fig. 5 to 7, the configuration of the failure detection system 10 is the same as that of the failure detection system 10 of fig. 1, but the dc current source 20, the drive signal oscillator 30, and a part of the wiring are omitted to simplify the drawing.

In the wiring of the circuit including the

coils

111, 112 and the control section 120 of fig. 5, solid lines indicate wires in the upper surface (front surface) of the printed circuit substrate 500, and broken lines indicate wires in the lower surface (back surface) of the printed circuit substrate 500. The small circles included in the

coils

111 and 112 represent lead wires that penetrate the printed circuit board 500 and are electrically connected to both the upper and lower surfaces. The paper-in currents I1 and I2 flow in the source terminals (S in fig. 5) of the switching elements Q1 and Q2, respectively.

By wiring the upper and lower surfaces of the printed circuit board 500 in this manner, the conductive wires on the printed circuit board 500 form the spiral coils 111 and 112.

Coils

111 and 112 connected in series in opposite directions generate induced voltages by currents I1 and I2 flowing through source terminals of switching elements Q1 and Q2, respectively, and controller 120 detects the coil and voltage Vc.

(embodiment mode 2)

Fig. 8 is a block diagram showing a configuration example of the failure detection system 10A according to embodiment 2. In fig. 8, the failure detection system 10A is different from the failure detection system 10 of fig. 1 in the following points.

(1) The switch device further includes switching elements Q3 and Q4 connected in parallel to the switching element Q1.

(2) The failure detection circuit 100A includes a detection unit 110A instead of the detection unit 110, and the detection unit 110A further includes

coils

113 and 114 connected in series to the

coils

111 and 112. The

coils

113 and 114 are disposed in the vicinity of current paths passing through the switching elements Q3 and Q4, respectively, and have the same number of turns and opposite winding directions.

In fig. 8, for example, when the current I4 becomes 0 only when the open failure occurs in the switching element Q4, the currents I1 to I3 flowing through the other switching elements Q1 to Q3 increase in a balanced manner. As a result, the induced voltages generated by the coils 111 to 113 increase, and the induced voltage generated by the coil 114 decreases. Thus, the coil sum voltage Vc increases greatly to exceed the threshold Vth, similarly to time t30 in fig. 3. If the coil sum voltage exceeds the threshold Vth, the control unit 120 detects an imbalance fault.

The current paths for detecting a fault in the fault detection system 10A of fig. 8 are not limited to two or four, and may be any number expressed by 2 × n relative to the natural number n. At this time, the detection unit 110A includes n sets of two coils connected in series, having the same number of turns, and having winding directions opposite to each other.

(other embodiments)

Embodiments 1 and 2 disclose

fault detection systems

10 and 10A for determining whether or not currents flowing through even-numbered current paths are all equal. However, the number of current paths of the fault detection system may be odd, and the currents flowing through the current paths during the steady operation period T1 may have different values from each other. For example, it is considered that the current I flows through the period T1 in N current paths including a plurality of (N) switching elements Q1 to QN₁～I_NThe case (1). In this case, by applying a voltage to the coilVc vs. Current I₁～I_NN coils (e.g., 111 and 112 in fig. 1; 111 to 114 in fig. 8) as 0 are arranged so as to surround the vicinities of the N current paths, respectively, thereby enabling detection of an imbalance fault. Specifically, when the number of turns of the coil having the winding direction opposite to the reference direction is regarded as a negative value with reference to the winding direction of the first coil of the detection current I1, the product of the current value flowing through each current path and the number of turns of the coil surrounding the current path, and the total value for all current paths may be set to 0. That is, if the following equation is satisfied, the coil sum voltage Vc becomes 0.

[ formula 1]

Here, n is_i(I is 1, 2, …, N) to surround the flowing current I_iThe number of turns of the coil arranged in the ith current path of (1), as described above, is a negative value when the winding direction is opposite to that of the first coil. However, when the number of turns of the plurality of coils is different from each other, the amount of change in the coil and the voltage Vc is different depending on which of the switching elements Q1 to QN has failed, and therefore, the setting of the threshold Vth should be noted.

Further, in embodiment 1 and embodiment 2, it is assumed that the coil and the voltage Vc are 0 in the period T1 of the steady operation in which all the switching elements normally operate. Therefore, the control unit 120 detects the unbalance failure when the coil and the voltage Vc exceed the voltage value range-Vth to Vth. However, for example, when the switching elements Q1 to Q4 are individually controlled, or the number of turns n of the coil₁～n₄And current I₁～I₄When the ratio of (c) is not inversely proportional, the coil and the voltage Vc can be set to be different from 0 even in the period T1. In this case, the controller 120 may detect the imbalance fault if the upper limit value and the lower limit value of the coil and the voltage Vc in the measurement period T1 exceed a predetermined value range including a range from the upper limit value to the lower limit value.

In embodiment 1, an example of surface mounting of the printed circuit board on the upper and lower surfaces as shown in fig. 5 is described. However, it is also possible to mount a discrete semiconductor element (a semiconductor element that achieves only a predetermined function) that performs the same operation as the above-described surface mounting, based on a plurality of switching elements and a plurality of coils that are embedded in a substrate during manufacturing. The imbalance fault detection circuits according to embodiments 1 and 2 are intended to detect an imbalance fault in a dc circuit using the dc current source 20. However, the unbalance fault detection circuit of the present disclosure is also capable of detecting an unbalance fault of a current in an alternating current circuit.

Industrial applicability of the invention

The unbalance fault detection circuit of the present disclosure can be applied to an electronic apparatus device including a plurality of current paths connected in parallel and respectively inserted with electronic apparatuses.

Description of the reference numerals

10. 10A: a fault detection system; 20: a direct current source; 30: a drive signal oscillator; 100. 100A: a fault detection circuit; 110. 110A: a detection unit; 111. 112, 113, 114: a coil; 120: a control unit; q1, Q2, Q3, Q4: a switching element; vc: a coil and a voltage.

Claims

1. An unbalanced fault detection circuit for detecting unbalanced faults of an electronic equipment device including a plurality of current paths, the multiple current paths respectively including electronic equipment and connected in parallel, the unbalanced fault detection circuit comprising:

A detection unit includes a plurality of coils connected in series, the plurality of coils are arranged so as to surround the plurality of current paths, respectively, and the detection unit outputs the plurality of coils based on the currents flowing in the plurality of current paths The sum of the induced voltages of the coils is the coil sum voltage; and

The control unit detects an unbalanced failure of the electronic equipment device when the coil and the voltage from the detection unit exceed the ranges of predetermined values.

2. The unbalanced fault detection circuit of claim 1, wherein,

The plurality of coils have the number of turns and the winding direction such that the coil and the voltage are actually zero,

The range of the predetermined value is a range between a positive threshold voltage and a negative threshold voltage.

3. The unbalanced fault detection circuit of claim 2, wherein,

Let the current flowing in each of the current paths be I _i , the number of turns of each coil corresponding to each of the current paths is _ni , and the winding direction of one of the plurality of coils is As the reference winding direction, the number of turns of the coil having the same winding direction as the reference winding direction is represented by the number of positive turns, and the number of turns of the coil having the winding direction opposite to the reference winding direction is expressed as the number of turns. When the number of turns is represented by the number of turns with a negative value, the number of turns of the plurality of coils is set to satisfy the following formula:

[Formula 1]

4. The unbalanced fault detection circuit of any one of claims 1 to 3, wherein,

The electronic equipment device is powered by a power source,

The control unit stops the power supply when the unbalanced failure is detected.

5. The unbalanced fault detection circuit of any one of claims 1 to 4, wherein,

A plurality of the electronic devices are respectively semiconductor switching elements,

A plurality of the semiconductor switching elements are controlled by the same driving signal to selectively switch the conduction and non-conduction of the current,

The unbalanced fault is caused by a short-circuit fault or an open-circuit fault of at least one semiconductor switching element among the plurality of semiconductor switching elements.

6. An electronic device comprising:

a plurality of current paths connected in parallel and each including a semiconductor switching element; and

The unbalanced fault detection circuit of any one of claims 1 to 5.