CN1141738C - Method for manufacturing on-chip inductor assembly - Google Patents

Abstract

The invention relates to a method for manufacturing a chip inductance component on a semiconductor substrate, which comprises the steps of firstly, defining the semiconductor substrate into a groove, and then forming an insulating layer filled in the groove, wherein the insulating layer has a dielectric constant lower than that of a silicon oxide substance or has a magnetic permeability higher than that of the silicon oxide substance. Then, a convoluted conductive coil is formed on the insulating layer. According to the invention, the inductance component is manufactured above the insulating material with low dielectric constant or high magnetic permeability, so that the parasitic capacitance effect and mutual inductance effect between the conductive coil and the substrate can be reduced.

Description

Manufacturing method of on-chip inductor component

The present invention relates to the manufacturing technology of semiconductor components, in particular to a method for manufacturing an on-chip inductance component that can reduce parasitic capacitance. The inductance component is formed above an insulating material with low dielectric constant or high magnetic permeability, so as to reduce the effect of parasitic capacitance and mutual inductance effect.

Integrated circuit technology enables miniaturization of electronic circuits. The miniaturization of circuits not only means that more components can be integrated on a single wafer, but also means that the cost of manufacturing circuits can be reduced. Today, many digital (such as memory or high-end processors, etc.) and analog circuits (such as operational amplifiers, etc.), contain active components such as bipolar junction transistors, field effect transistors, and diodes, or such as resistors and Passive components such as capacitors have been successfully implemented in integrated circuits.

However, radio frequency circuits of various communication devices such as mobile phones, wireless circuits, wireless modems, etc. cannot be fully realized in the form of integrated circuits. The difficulty lies in how to manufacture inductance components suitable for radio frequency applications. The known inductance components either have too low quality factor (hereinafter referred to as Q value) or too much loss, or need to use precious metals such as gold (Au) as materials.

U.S. Patent No. 5,446,311 proposes a technology for obtaining high-Q inductance components without using precious metals. It is to stack multiple layers of metal wires with the same convoluted shape on an insulating layer covering the surface of a semiconductor substrate to construct an inductance. components. The stacked multi-layer metal can reduce the series resistance, so as to improve the Q value, and its lumped equivalent circuit is shown in Figure 1. In Figure 1, C _d represents the parasitic capacitance between the metal wires, L ₁ is the inductance, R _s represents the series resistance of the convoluted metal wire, C ₁ and C ₂ represent the parasitic capacitance between the substrate and the metal wire, if the adopted The semiconductor substrate is a lossy material such as silicon, then R ₁ and R ₂ represent the parasitic resistances connected in parallel with C ₁ and C ₂ respectively, and since the semiconductor substrate is usually grounded, R ₁ , One end of R ₂ , C ₁ , and C ₂ is grounded. In addition, L ₂ represents the inductance existing in the substrate due to the mirror current mutual inductance effect, and R _SUB is the parasitic resistance existing in the substrate.

Since semiconductor technology usually uses silicon oxide (SiO _x ) as an insulating material, its dielectric constant (dielectric constant or relative permeability relative to vacuum) is approximately in the range of 3.9-4.5. Therefore, although the No. 5,446,311 case uses multi-layer metals to increase the Q value, it limits the self-resonant frequency (self-resonant frequency) of the inductance component due to the dielectric constant of the silicon oxide, thus limiting the high frequency of the inductance component. Applications.

Therefore, US Patent No. 5,539,241 proposes to etch the substrate portion below the convoluted metal line to form a hole (pit), so that the convoluted metal line is suspended above the hole only supported by the oxide layer. Since air is filled in the hole at this time, its dielectric constant is close to 1, so the parasitic capacitance of the inductance component can be reduced, and a self-resonant frequency above 2 GHz can be obtained. However, No. 5,539,241 applies partial etching to the substrate, which will make the manufacturing process quite complicated, and it is difficult to implement in BiCMOS and CMOS standard manufacturing processes.

In order to overcome the deficiencies in the prior art, the object of the present invention is to provide a method for manufacturing an on-chip inductance component, wherein the inductance component is made above a low dielectric constant or high magnetic permeability insulating material, and the method can reduce the on-chip inductance component. Parasitic capacitive effects and mutual inductance effects,

Another object of the present invention is to provide a method for manufacturing an on-chip inductor component, which is compatible with BiCMOS and CMOS standard processes. The parasitic capacitance effect and mutual inductance effect of the inductance components on the chip are reduced by steps such as deposition, etching, and planarization.

The present invention can be accomplished by providing a manufacturing method of an on-chip inductance device that can reduce parasitic capacitance. The manufacturing method of the inductor component provided by the present invention is implemented on a semiconductor substrate. Firstly, after the semiconductor substrate is defined into a trench, an insulating layer is formed to fill the trench. The insulating layer has a lower dielectric constant than silicon oxide or a higher magnetic permeability than silicon oxide. Then, a convoluted conductive coil is formed on the insulating layer.

The invention makes the inductance component above the insulating material with low dielectric constant or high magnetic permeability, so the parasitic capacitance effect and mutual inductance effect between the conductive coil and the substrate can be reduced.

In order to make the above and other purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, combined with the accompanying drawings, and described in detail as follows:

A brief description of the accompanying drawings:

Fig. 1 shows the lumped equivalent circuit diagram of the inductance component on the known chip;

Figures 2A-2D show a flow sectional view according to a preferred embodiment of the present invention;

Figure 3 shows a top view of Figure 2C; and

FIG. 4 shows a cross-sectional view of the process according to another preferred embodiment of the present invention. Symbol Description:

20～semiconductor substrate; 21～photoresist; 22～groove; 23, 33～insulating layer; 24～lead wire; 25～first interlayer dielectric layer; 26～through hole; 27～metal plug; 28 ～convoluted conductive coil; 29～second interlayer dielectric layer; 30～via hole; 31～metal plug; and, 32～lead wire.

Example

From Figure 1, there are three main factors that degrade the inductance components on the chip: (1) The mirror current flowing through the substrate will increase the series resistance R _SUB due to the mutual inductance effect; (2) The influence of the skin effect or other magnetic effects; And (3) represents the loss caused by the parasitic capacitances _C1 and _C2 between the substrate and the convoluted metal lines. Therefore, according to the present invention, one is to use insulating materials with low dielectric constant or high magnetic permeability to reduce parasitic capacitances _C1 and _C2 ; the other is to increase the distance between the convoluted metal wire and the substrate to reduce the mutual inductance effect, surface effect, or other magnetic effects. Hereinafter, a flowchart of a preferred embodiment of the present invention will be described in detail with reference to FIGS. 2A-2D .

Please refer to FIGS. 2A-2D , which are cross-sectional views of the process according to a preferred embodiment of the present invention, depicting several critical steps in the manufacturing process.

First, as shown in FIG. 2A , a photoresist layer 21 with a predetermined pattern is formed on a semiconductor substrate 20 by photolithography, exposing the surface of the substrate 20 where the groove 22 is to be formed. Usually, the semiconductor substrate 20 is a silicon substrate, and semiconductor components such as bipolar junction transistors or field effect transistors can be formed on the substrate 20 (for the sake of simplicity, they are not shown in 2A-2D) . Subsequently, the photoresist layer 21 is used as a mask to perform dry or wet etching to define a groove 22 on the substrate 20 . This etching step can be performed by using reactive ion etching (RIE) or high-density plasma etching (HDP) in combination with etching mixed gases such as SF ₆ and O ₂ , forming a trench 22 with a depth of about 2-100 μm, which is relatively The preferred depth of the trench 22 is about 2-50 μm.

Then, as shown in FIG. 2B , an insulating layer 23 with low dielectric constant or high permeability is deposited to cover the entire surface of the substrate 20 and also fill in the trench 22 . According to the invention, the insulating layer 23 has a lower dielectric constant than silicon oxide, or a higher magnetic permeability than silicon oxide. For example, the insulating layer 23 can be made of silicon and carbon-based organic polymers (such as AF ₄ polymers (parylene-F polyparaethylene toluene) with a dielectric constant of about 1.7), or ferrite ceramics with high magnetic permeability. (ferrite ceramic) material (such as ZnO), etc. Subsequent processes such as etching back (etch back) or chemical mechanical polishing (CMP) can be applied to obtain a flat surface, and then the insulating layer 23 is subjected to curing (curing )deal with.

Next, a conductive layer is deposited and patterned to form a lead 24 . The lead 24 is preferably made of aluminum-copper alloy, and a barrier layer (barrier layer) such as titanium or titanium nitride can be optionally added below it to prevent the aluminum from penetrating into the silicon substrate 20, but FIG. 2C is not divided into another independent level for display. The method for forming the lead 24, for example, can first obtain an aluminum-copper alloy layer by physical vapor deposition (PVD), and then determine the pattern of the lead 24 by photoetching and anisotropic etching. This anisotropic etching method For example, it may be performed in a reactive ion etcher (RIE) or a high density plasma (HDP) etcher containing a reactant gas mixture containing chlorine.

Thereafter, a first interlayer dielectric layer 25 is deposited to cover the entire surface, and after etching to define a via hole (via hole) 26, a conductive layer is deposited and patterned to form a convoluted conductive coil 28, as shown in the figure 2C shows the cross-sectional structure, and the top view of FIG. 2C is shown in FIG. 3 . The convoluted conductive coil 28 can be an aluminum-copper alloy obtained by physical vapor deposition, which can be directly filled in the through hole 26, and then electrically contacted with the lead wire 27; in addition, as shown in FIG. 2C, The tungsten metal plug 27 is filled in the through hole 26 before the convoluted conductive coil 28 is formed.

The formation of the lead wires 24 and the interlayer dielectric layer 25 is an optional step, which can also be omitted according to the layout requirements.

Next, a second interlayer dielectric layer 29 (for example, formed of silicon oxide obtained by plasma-assisted chemical deposition) is deposited to cover the entire surface, and after etching to define the through hole 30, a conductive layer is deposited and determined. pattern to form the leads 32, that is, the cross-sectional structure shown in FIG. 2D is obtained. The lead wire 32 can be aluminum or aluminum-copper alloy obtained by physical vapor deposition, which can be directly filled in the through hole 30, and then electrically contact with the other end of the convoluted conductive coil 28; in addition, it can also be as shown in the figure As shown in 2D, a metal plug 31 made of tungsten is electrically connected to the other end of the convoluted conductive coil 28 .

Since the convoluted conductive coil 28 is located above the insulating layer 23 with a low dielectric constant or high permeability, it can reduce the parasitic capacitances C ₁ and C ₂ between the substrate and the metal layer, and improve the self-resonant frequency of the inductance component; moreover According to the method of the present invention, the substrate is etched to form a deep groove 22, which can increase the distance between the convoluted conductive coil 28 and the substrate 20, and reduce the influence of the mutual inductance effect.

Please refer to FIG. 4 , which shows a cross-sectional flow chart according to another preferred embodiment of the present invention. After completing the steps shown in FIG. 2C , at least another insulating layer 33 is formed in the gap of the convoluted conductive coil 28 . The insulating layer 33 is, for example, made of the same material as the insulating layer 23 , which has a lower dielectric constant than silicon oxide or a higher magnetic permeability than silicon oxide. For example, the insulating layer 33 can be made of silicon and carbon-based organic polymer (such as AF ₄ polymer (parylene-F) with a dielectric constant of about 1.7), so as to reduce the parasitic capacitance C _d of the convoluted conductive coil 28; or The insulating layer 33 can be made of a ferrite ceramic material (such as ZnO) with high magnetic permeability to increase the inductance L ₁ .

Then, a second interlayer dielectric layer 29 is deposited to cover the entire surface, and after the through holes 30 are etched to be determined, a conductive layer is deposited and patterned to form leads 32 , that is, the cross-sectional structure shown in FIG. 3 . The lead wire 32 can be aluminum or aluminum-copper alloy obtained by physical vapor deposition, which can be directly filled in the through hole 30, and then electrically contact with the other end of the convoluted conductive coil 28; in addition, it can also be as shown in the figure 3 , it is electrically connected to the other end of the convoluted conductive coil 28 via a corresponding metal plug 31 .

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. For example, the above-mentioned convoluted conductive coil 28 of the present invention can also be stacked in multiple layers (two layers, three layers, four layers, etc.) The implementation of the conductive layer can further reduce the series resistance R _s and improve the quality factor of the inductance component. Therefore, any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined as defined by the appended claims in conjunction with the specification and accompanying drawings. allow.

Claims (14)

1. A method for manufacturing an on-chip inductive component, comprising: Determining a semiconductor substrate into a groove; forming an insulating layer in the trench, the insulating layer has a lower dielectric constant than silicon oxide number; and forming a convoluted conductive coil on the insulating layer. 2 . The method for manufacturing an inductor on a chip as claimed in claim 1 , wherein the insulating layer is an organic polymer based on silicon and carbon. 3. The method for manufacturing an inductor on a chip as claimed in claim 2, wherein the insulating layer is polyparaethylene toluene. 4. The method for manufacturing an inductor on a chip as claimed in claim 1, wherein the trench has a depth of about 2-100 μm. 5 . The method for manufacturing an inductor on a chip as claimed in claim 1 , further comprising forming another insulating layer in the space between the convoluted conductive coils. 5 . 6. The method for manufacturing an inductor on a chip as claimed in claim 5, wherein the insulating layer is an organic polymer based on silicon and carbon. 7. The method for manufacturing an inductor on a chip as claimed in claim 6, wherein the insulating layer is polyparaethylene toluene. 8. A method of manufacturing an inductance component on a chip, comprising: Determining a semiconductor substrate into a groove; forming an insulating layer in the trench, the insulating layer having a higher magnetic permeability than silicon oxide; and A convoluted conductive coil is formed on the insulating layer. 9. The method for manufacturing an inductor on a chip as claimed in claim 8, wherein the insulating layer is ferrite ceramic. 10. The method for manufacturing an inductor on a chip as claimed in claim 9, wherein the insulating layer is ZnO. 11. The method for manufacturing an inductor on a chip as claimed in claim 8, wherein the trench has a depth of about 2˜50 μm. 12. The manufacturing method of the on-chip inductor device as claimed in claim 8, further comprising forming another insulating layer in the gap of the convoluted conductive coil. 13. The method for manufacturing an inductor on a chip as claimed in claim 12, wherein the another insulating layer is ferrite ceramic. 14. The manufacturing method of the on-chip inductor device as claimed in claim 13, wherein the insulating layer is ZnO.

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