CN114172511B - Frequency preset control method and device based on FPGA, medium and electronic equipment - Google Patents
Frequency preset control method and device based on FPGA, medium and electronic equipment Download PDFInfo
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- CN114172511B CN114172511B CN202111517282.9A CN202111517282A CN114172511B CN 114172511 B CN114172511 B CN 114172511B CN 202111517282 A CN202111517282 A CN 202111517282A CN 114172511 B CN114172511 B CN 114172511B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- Computer Networks & Wireless Communication (AREA)
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- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a frequency preset control method, a device, a medium and electronic equipment based on an FPGA, which comprises initializing a frequency source, configuring a frequency source output frequency to an initial frequency point, configuring a register corresponding to a target frequency point in a RAM1 to a frequency source phase-locked loop, judging whether the target frequency point is locked, collecting a tuning voltage of the target frequency point when the target frequency point is locked, storing in a RAM2, establishing a frequency point-tuning voltage lookup table, storing in a RAM3, configuring a register corresponding to a frequency hopping frequency point to the phase-locked loop when frequency hopping, configuring DA (digital to analog) according to the frequency point-tuning voltage lookup table, generating preset tuning voltage by DA, and completing frequency preset; after the frequency-tuning voltage lookup table is built, the corresponding value is searched for according to the target frequency and is sent to the DA to be converted into the tuning voltage, so that the frequency is quickly preset, and the purpose of quick locking is achieved.
Description
Technical Field
The invention relates to the field of radar communication, in particular to a frequency preset control method, device, medium and electronic equipment based on FPGA.
Background
In recent years, with the increase of data rate in the field of radar communication, the locking time of a phase-locked loop becomes a key index for designing a radar communication system.
In radar communication systems, the lock time of a phase locked loop constrains the time interval between the reception and transmission of a signal by a radio frequency transceiver. In addition, in the application of frequency hopping spread spectrum communication, the faster the frequency hopping speed of the phase-locked loop is, the more favorable the multipath fading resistance and the interference avoidance are, thereby improving the data communication quality;
In the field of military frequency hopping communication, the faster the frequency hopping speed is, the more difficult the communication frequency is to track, thereby improving the data communication security.
Currently, the industry generally adopts a frequency preset mode to reduce the phase-locked loop locking time. The traditional frequency preset control mode has the conditions of insufficient preset precision, unreasonable preset and the like. The preset precision is not enough, the purpose of reducing the frequency hopping time cannot be achieved often due to unreasonable preset, and even the frequency source cannot be locked.
Disclosure of Invention
The invention aims to solve the technical problems of insufficient preset precision, unreasonable preset and the like in the traditional frequency preset control mode, and provides a frequency preset control method, device, medium and electronic equipment based on an FPGA, which solve the problems of how to perform frequency preset and enable a circuit to be automatically, accurately and stably controlled.
The invention is realized by the following technical scheme:
a frequency preset control method based on FPGA includes:
Initializing a frequency source, and configuring the output frequency of the frequency source to an initial frequency point;
Configuring a register corresponding to a target frequency point pre-stored in the RAM1 to a frequency source phase-locked loop;
judging whether the target frequency point is locked or not;
When the target frequency point is locked, collecting the tuning voltage of the target frequency point and storing the tuning voltage into the RAM2;
Establishing a frequency point-tuning voltage lookup table and storing the frequency point-tuning voltage lookup table into a RAM3;
During frequency hopping, configuring a register corresponding to a frequency hopping point to a phase-locked loop, and configuring data of the frequency hopping point to a DA (digital A) according to a frequency point-tuning voltage lookup table;
the DA generates a preset tuning voltage to finish frequency presetting.
Specifically, the method for configuring the register corresponding to the target frequency point pre-stored in the RAM1 to the frequency source phase-locked loop specifically includes the following steps:
Storing register values corresponding to a plurality of target frequency points into the RAM1;
and configuring a corresponding register to the frequency source phase-locked loop according to the current target frequency point.
Specifically, the method for judging whether the target frequency point is locked comprises the following steps:
Detecting whether the frequency source lock indication signal is high;
If the signal is high, the target frequency point is locked;
If the signal is low, the target frequency point is not locked, and if the target frequency point is not locked, the frequency source is initialized again.
Preferably, the tuning voltage of the acquisition target frequency point is sampled by adopting the 16bit precision AD.
Specifically, the method for collecting the tuning voltage of the target frequency point specifically includes the following steps:
Setting the acquisition times N of the tuning voltage of the target frequency point;
Judging whether the tuning voltage of the target frequency point is acquired or not, if the acquisition is not completed, reconfiguring a register corresponding to the target frequency point in the RAM1 to a frequency source phase-locked loop;
If the acquisition is completed, the acquisition times are n+1;
judging n=n, if not, initializing the frequency source again;
If the tuning voltages are equal, the average value of the N tuning voltages is taken and is used as the tuning voltage of the target frequency point and stored in the RAM2.
Further, after completing frequency presetting, judging whether the frequency source is locked or not;
If the frequency source is locked, ending;
if the frequency source is not locked, the frequency source is reinitialized.
A frequency preset control device based on an FPGA, comprising:
the initial module is used for initializing the frequency source and configuring the output frequency of the frequency source to an initial frequency point;
the first configuration module is used for configuring a register corresponding to a target frequency point pre-stored in the RAM1 to the frequency source phase-locked loop;
the judging module is used for judging whether the target frequency point is locked or not;
the acquisition module is used for acquiring the tuning voltage of the target frequency point when the target frequency point is locked, and storing the tuning voltage into the RAM2;
The processing module is used for establishing a frequency point-tuning voltage lookup table and storing the frequency point-tuning voltage lookup table into the RAM3;
The second configuration module is used for configuring a register corresponding to the frequency hopping point to the phase-locked loop when frequency hopping is performed, and configuring DA for the data of the frequency hopping point according to the frequency point-tuning voltage lookup table;
And the output module is used for generating preset tuning voltage by the DA and completing frequency preset.
Specifically, the acquisition module specifically includes:
The setting module is used for setting the acquisition times N of the tuning voltage of the target frequency point;
the first judging module is used for judging whether the acquisition of the tuning voltage of the target frequency point is completed or not; if the acquisition is not completed, reconfiguring a register corresponding to a target frequency point in the RAM1 to a frequency source phase-locked loop;
the counting module is used for counting the acquisition times n+1 after the acquisition is completed;
the second judging module is used for judging that n=n, and if the n=n is not equal, initializing the frequency source again;
and the calculation module is used for calculating the average value of the N tuning voltages, taking the average value as the tuning voltage of the target frequency point and storing the tuning voltage into the RAM2.
A computer readable storage medium storing a computer program which when executed by a processor implements the steps of an FPGA-based frequency preset control method described above.
An electronic device, comprising: at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to: the method for controlling the frequency preset based on the FPGA is implemented.
Compared with the prior art, the invention has the following advantages and beneficial effects:
The method starts to initialize the frequency points of the phase-locked loop and preset the frequency, sends the frequency point register values to the phase-locked loop, checks whether the phase-locked loop is locked after time delay, starts to collect tuning voltage of the AD after locking, stores the AD into the FRAM after the collection is completed, finally completes the collection of tuning voltage of all the frequency points, and establishes a frequency-tuning voltage lookup table. After the lookup table is built, the corresponding value is searched for according to the target frequency, and is sent to the DA for conversion into tuning voltage, so that the frequency is rapidly preset, and the purpose of rapid locking is achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1 is a schematic flow chart of a frequency preset control method based on an FPGA according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and embodiments, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It is to be understood that the specific embodiments described herein are merely illustrative of the substances, and not restrictive of the invention.
It should be further noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
Embodiments of the present invention and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Currently, the industry generally adopts a frequency preset mode to reduce the phase-locked loop locking time. The traditional frequency preset control mode has the conditions of insufficient preset precision, unreasonable preset and the like. The preset precision is not enough, the purpose of reducing the frequency hopping time cannot be achieved often due to unreasonable preset, and even the frequency source cannot be locked.
The application mainly aims to solve the defects of inaccurate and unreasonable preset of the current frequency preset control method and realize the automatic, accurate and stable control of the frequency preset circuit.
An embodiment first provides a frequency preset control method based on an FPGA, where the method includes:
The first step, the device in the second embodiment is powered on as a whole, the frequency source is initialized, and the output frequency of the frequency source is configured to the initial frequency point;
Step two, configuring a register corresponding to a target frequency point pre-stored in the RAM1 to a frequency source phase-locked loop;
Storing register values corresponding to a plurality of target frequency points into the RAM1;
and configuring a corresponding register to the frequency source phase-locked loop according to the current target frequency point.
The configuration may take a certain time, so that in the second step, a certain waiting time is required for configuration, and the configuration is completely completed.
Thirdly, judging whether the target frequency point is locked or not;
Detecting whether the frequency source lock indication signal is high;
If the signal is high, the target frequency point is locked;
If the signal is low, the target frequency point is not locked, and if the target frequency point is not locked, the first step is skipped again.
Fourth, when the target frequency point is locked, collecting the tuning voltage of the target frequency point and storing the tuning voltage into the RAM2;
The tuning voltage of the acquisition target frequency point is sampled by adopting 16bit precision AD, and the advantage of adopting 16bit high precision AD is that: in the process of converting the tuning voltage into digital information, the error caused is minimized as much as possible.
Fifthly, establishing a frequency point-tuning voltage lookup table and storing the frequency point-tuning voltage lookup table into the RAM3; the target frequency points are in one-to-one correspondence with the tuning voltages, so that the purpose of searching the tuning voltages with the target frequency points can be realized, and in actual use, the corresponding tuning voltages can be quickly searched according to the input target frequency points.
Step six, during frequency hopping, configuring a register corresponding to a frequency hopping point to a phase-locked loop, and configuring data of the frequency hopping point to a DA according to a frequency point-tuning voltage lookup table;
seventh, DA generates preset tuning voltage to finish frequency preset.
After completing the frequency presetting, it needs to detect whether the completion is normal, so the eighth step is performed after waiting for the completion of the configuration, i.e. after delaying for a period of time.
Eighth, after completing the frequency presetting, judging whether the frequency source is locked or not;
If the frequency source is locked, ending;
if the frequency source is not locked, the first step is skipped again. .
Example two
In this embodiment, if the number of times of tuning voltage of the target frequency point is too small, an error may occur, so the present embodiment provides an optimization method.
S1, the number of times N of acquisition of the tuning voltage to the target frequency point is set, where n=10 in this embodiment.
S2, judging whether the tuning voltage of the target frequency point is acquired or not, if the acquisition is not completed, proving that the conditions such as error of the initial frequency point, abnormal locking of a frequency source, abnormal target frequency point and the like are possibly caused, so that the configuration is carried out again by jumping to the first step, and if the acquisition is still abnormal for a plurality of times, an alarm is sent;
S3, if the acquisition is completed, acquiring the number of times n+1;
S4, judging whether n is equal to 10, if not, re-jumping to a second step, collecting tuning voltage of the frequency point for the second time, and repeating the steps S2 and S3 in sequence;
And S5, if n=10, proving that the acquisition of the tuning voltage is completed for N times for the target frequency point, calculating the average value of the N tuning voltages, taking the average value as the tuning voltage of the target frequency point, and storing the tuning voltage into the RAM2.
The averaging has the advantages of reducing error caused by the sampling process, sampling errors of AD devices and the like, normalizing and reducing the randomness of the errors. The method is used for collecting for 10 times, the time required by the collection process and the feasibility of error reduction are comprehensively considered, and the collection result is accurate and reasonable as much as possible.
Example III
The embodiment provides a modularized structure for realizing the first embodiment, and a frequency preset control device based on an FPGA, which comprises an initial module, a first configuration module, a judging module, an acquisition module, a processing module, a second configuration module and an output module.
The initial module is used for initializing the frequency source and configuring the output frequency of the frequency source to an initial frequency point;
The first configuration module is used for configuring a register corresponding to a target frequency point pre-stored in the RAM1 to a frequency source phase-locked loop;
The judging module is used for judging whether the target frequency point is locked or not;
The acquisition module is used for acquiring the tuning voltage of the target frequency point when the target frequency point is locked, and storing the tuning voltage into the RAM2;
the processing module is used for establishing a frequency point-tuning voltage lookup table and storing the frequency point-tuning voltage lookup table into the RAM3;
the second configuration module is used for configuring a register corresponding to the frequency hopping point to the phase-locked loop when frequency hopping is performed, and configuring DA for the data of the frequency hopping point according to the frequency point-tuning voltage lookup table;
the output module is used for generating preset tuning voltage by DA and completing frequency preset.
The signal output end of the initial module is electrically connected with the signal input end of the first configuration module, the signal output end of the first configuration module is electrically connected with the signal input end of the judging module, the signal output end of the judging module is electrically connected with the signal input end of the initial module and the signal input end of the collecting module, the signal output end of the collecting module is electrically connected with the signal input end of the processing module, the signal output end of the processing module is electrically connected with the signal input end of the second configuration module, and the signal output end of the second configuration module is electrically connected with the signal input end of the output module.
In addition, in order to implement the related structure in the second embodiment, the acquisition module in this embodiment specifically includes a setting module, a first judgment module, a counting module, a second judgment module, and a calculation module.
The setting module is used for setting the acquisition times N of the tuning voltage of the target frequency point;
The first judging module is used for judging whether the acquisition of the tuning voltage of the target frequency point is completed or not; if the acquisition is not completed, reconfiguring a register corresponding to a target frequency point in the RAM1 to a frequency source phase-locked loop;
the counting module is used for counting the acquisition times n+1 after the acquisition is completed;
the second judging module is used for judging that n=n, and if the n=n is not equal, initializing the frequency source again;
The calculation module is used for calculating the average value of the N tuning voltages, taking the average value as the tuning voltage of the target frequency point and storing the tuning voltage into the RAM2.
The signal input end of the first judging module is electrically connected with the signal output end of the setting module and the signal output end of the judging module, the signal output end of the first judging module is electrically connected with the signal input end of the counting module and the signal input end of the first configuration module, the signal output end of the counting module is electrically connected with the signal input end of the second judging module, and the signal output end of the second judging module is electrically connected with the signal input end of the calculating module and the signal input end of the initial module.
Example IV
A computer readable storage medium storing a computer program which when executed by a processor implements the steps of a frequency preset control method based on FPGA described above.
An electronic device, comprising: at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to: the method for controlling the frequency preset based on the FPGA is implemented.
The memory may be used to store software programs and modules, and the processor executes various functional applications of the terminal and data processing by running the software programs and modules stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an execution program required for at least one function, and the like.
The storage data area may store data created according to the use of the terminal, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.
Computer readable media may include computer storage media and communication media without loss of generality. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instruction data structures, program modules or other data. Computer storage media includes RAM, ROM, EPROM, EEPROM, flash memory or other solid state memory technology, CD-ROM, DVD or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices. Of course, those skilled in the art will recognize that computer storage media are not limited to the ones described above. The above-described system memory and mass storage devices may be collectively referred to as memory.
In the description of the present specification, reference to the terms "one embodiment/manner," "some embodiments/manner," "example," "a particular example," "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/manner or example is included in at least one embodiment/manner or example of the application. In this specification, the schematic representations of the above terms are not necessarily for the same embodiment/manner or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples described in this specification and the features of the various embodiments/modes or examples can be combined and combined by persons skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
It will be appreciated by persons skilled in the art that the above embodiments are provided for clarity of illustration only and are not intended to limit the scope of the invention. Other variations or modifications of the above-described invention will be apparent to those of skill in the art, and are still within the scope of the invention.
Claims (9)
1. The frequency preset control method based on the FPGA is characterized by comprising the following steps of:
Initializing a frequency source, and configuring the output frequency of the frequency source to an initial frequency point;
Configuring a register corresponding to a target frequency point pre-stored in the RAM1 to a frequency source phase-locked loop;
judging whether the target frequency point is locked or not;
When the target frequency point is locked, collecting the tuning voltage of the target frequency point and storing the tuning voltage into the RAM2;
Establishing a frequency point-tuning voltage lookup table and storing the frequency point-tuning voltage lookup table into a RAM3;
During frequency hopping, configuring a register corresponding to a frequency hopping point to a phase-locked loop, and configuring data of the frequency hopping point to a DA (digital A) according to a frequency point-tuning voltage lookup table;
The DA generates a preset tuning voltage to finish frequency presetting;
The method for configuring the register corresponding to the target frequency point in the RAM1 to the frequency source phase-locked loop specifically comprises the following steps:
Storing register values corresponding to a plurality of target frequency points into the RAM1;
and configuring a corresponding register to the frequency source phase-locked loop according to the current target frequency point.
2. The method for controlling frequency preset based on FPGA according to claim 1, wherein the method for determining whether the target frequency point is locked comprises the steps of:
Detecting whether the frequency source lock indication signal is high;
If the signal is high, the target frequency point is locked;
If the signal is low, the target frequency point is not locked, and if the target frequency point is not locked, the frequency source is initialized again.
3. The method for controlling frequency preset based on FPGA according to claim 1, wherein the tuning voltage of the acquisition target frequency point is sampled by using a 16bit precision AD.
4. The method for controlling frequency preset based on the FPGA according to claim 1, wherein the step of collecting the tuning voltage of the target frequency point specifically includes the steps of:
Setting the acquisition times N of the tuning voltage of the target frequency point;
Judging whether the tuning voltage of the target frequency point is acquired or not, if the acquisition is not completed, reconfiguring a register corresponding to the target frequency point in the RAM1 to a frequency source phase-locked loop;
If the acquisition is completed, the acquisition times are n+1;
judging n=n, if not, initializing the frequency source again;
If the tuning voltages are equal, the average value of the N tuning voltages is taken and is used as the tuning voltage of the target frequency point and stored in the RAM2.
5. The FPGA-based frequency preset control method according to claim 1, wherein after completing frequency preset, it is determined whether frequency source locking is performed;
If the frequency source is locked, ending;
if the frequency source is not locked, the frequency source is reinitialized.
6. The utility model provides a frequency presets controlling means based on FPGA which characterized in that includes:
the initial module is used for initializing the frequency source and configuring the output frequency of the frequency source to an initial frequency point;
the first configuration module is used for configuring a register corresponding to a target frequency point pre-stored in the RAM1 to the frequency source phase-locked loop;
the judging module is used for judging whether the target frequency point is locked or not;
the acquisition module is used for acquiring the tuning voltage of the target frequency point when the target frequency point is locked, and storing the tuning voltage into the RAM2;
The processing module is used for establishing a frequency point-tuning voltage lookup table and storing the frequency point-tuning voltage lookup table into the RAM3;
The second configuration module is used for configuring a register corresponding to the frequency hopping point to the phase-locked loop when frequency hopping is performed, and configuring DA for the data of the frequency hopping point according to the frequency point-tuning voltage lookup table;
And the output module is used for generating preset tuning voltage by the DA and completing frequency preset.
7. The FPGA-based frequency preset control apparatus of claim 6, wherein the acquisition module specifically comprises:
The setting module is used for setting the acquisition times N of the tuning voltage of the target frequency point;
the first judging module is used for judging whether the acquisition of the tuning voltage of the target frequency point is completed or not; if the acquisition is not completed, reconfiguring a register corresponding to a target frequency point in the RAM1 to a frequency source phase-locked loop;
the counting module is used for counting the acquisition times n+1 after the acquisition is completed;
the second judging module is used for judging that n=n, and if the n=n is not equal, initializing the frequency source again;
and the calculation module is used for calculating the average value of the N tuning voltages, taking the average value as the tuning voltage of the target frequency point and storing the tuning voltage into the RAM2.
8. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the steps of an FPGA-based frequency preset control method according to any one of claims 1-5.
9. An electronic device, comprising: at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to: implementing a method for controlling frequency presettings based on FPGA according to any one of claims 1-5.
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| CN101741379A (en) * | 2009-12-09 | 2010-06-16 | 中国科学院半导体研究所 | A Frequency Synthesis Device for Fast Locked Phase Locked Loop |
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| US8578193B2 (en) * | 2007-11-28 | 2013-11-05 | International Business Machines Corporation | Apparatus, method and program product for adaptive real-time power and perfomance optimization of multi-core processors |
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| CN202998066U (en) * | 2012-12-25 | 2013-06-12 | 陕西烽火电子股份有限公司 | Low-noise and fast-switch frequency synthesizer |
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| US10505549B1 (en) * | 2018-05-15 | 2019-12-10 | Perceptia Ip Pty Ltd | Power-saving phase accumulator |
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