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CN114172469A - Load modulation balance power amplifier and self-matching implementation method - Google Patents

Load modulation balance power amplifier and self-matching implementation method Download PDF

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CN114172469A
CN114172469A CN202111461513.9A CN202111461513A CN114172469A CN 114172469 A CN114172469 A CN 114172469A CN 202111461513 A CN202111461513 A CN 202111461513A CN 114172469 A CN114172469 A CN 114172469A
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amplifier
output
input
balanced
circuit
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陈世昌
王惠婕
连雪海
刘太君
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Hangzhou Dianzi University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers

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Abstract

本发明公开一种负载调制平衡功率放大器及自匹配实现方法，其包括功分器、相位补偿网络、输入3‑dB正交耦合器、平衡放大器、控制放大器和输出3‑dB正交耦合器；所述平衡放大器包括上下两路平衡子放大器；本发明通过根据输入功率大小自适应改变平衡放大器栅极偏置大小，实现对控制功放和平衡功放输出电流大小和相对相位的控制，达到对饱和点和回退点的阻抗匹配的目的，相位补偿网络增加了电路的工作带宽，解决了传统操作复杂，结果不连续的问题。本发明在负载调制平衡放大器的应用背景下，采用自适应动态偏置和阻抗自匹配技术，具有结构简单，实用性强，便于推广的优点。

Figure 202111461513

The invention discloses a load modulation balanced power amplifier and a self-matching implementation method, comprising a power divider, a phase compensation network, an input 3-dB quadrature coupler, a balanced amplifier, a control amplifier and an output 3-dB quadrature coupler; The balanced amplifier includes upper and lower balanced sub-amplifiers; the present invention realizes the control of the output current and relative phase of the control power amplifier and the balanced power amplifier by adaptively changing the gate bias of the balanced amplifier according to the input power, so as to achieve the saturation point. For the purpose of impedance matching at the back-off point, the phase compensation network increases the operating bandwidth of the circuit and solves the problem of complex traditional operations and discontinuous results. In the application background of the load modulation balanced amplifier, the present invention adopts the adaptive dynamic bias and impedance self-matching technology, and has the advantages of simple structure, strong practicability and easy popularization.

Figure 202111461513

Description

Load modulation balance power amplifier and self-matching implementation method
Technical Field
The invention belongs to the field of radio frequency microwave communication, relates to a load modulation balanced power amplifier and a self-matching implementation method, and particularly relates to a load modulation balanced amplifier design for realizing automatic impedance matching by means of dynamic bias voltage control.
Background
In the field of mobile communications, in order to increase the spectrum utilization of a limited frequency band to transmit as much data as possible, radio frequency transceiving systems generally require complex modulation of data, which causes signals of modern communication systems to generally have high peak-to-average power ratios (PAPR). The traditional linear amplifier has undistorted amplification effect for constant envelope signals, but has low amplification efficiency for high peak-to-average ratio signals with sharply changed envelopes. Therefore, to ensure the overall efficiency of the transmitter, it is generally required that the power amplifier can operate in a wide dynamic range of power, i.e. in the saturation and back-off regions while maintaining high efficiency. In recent years, load modulation amplifiers for high peak-to-average ratio signals have been studied very much, and load modulation amplifiers represented by Doherty (Doherty) and Outphasing (Outphasing) structures have become the mainstream of applications in the industry. However, such amplifiers typically operate only in a narrow band.
Recently, a new Load Modulation Balanced Amplifier (LMBA) has been proposed in the industry. Similar to the two amplifiers, the load modulation balanced amplifier can realize high-efficiency modulation signal amplification during power back-off, and has a certain broadband effect, so that the load modulation balanced amplifier is strongly concerned by researchers of radio frequency microwave power amplifiers. The working principle of the load modulation type amplifier is that a modulation signal is decomposed into two orthogonal signals (the phase difference is 90 degrees) with equal amplitude by inputting a 3-dB orthogonal coupler, and an additionally added control signal is injected into an isolation port of the output 3-dB orthogonal coupler so as to realize load impedance modulation on a direct connection end and a coupling end of the output 3-dB orthogonal coupler, and the modulation signal has the same phase at an output port after passing through the 3-dB orthogonal coupler and is superposed on the output port together with the power of the control signal.
The conventional load modulation balanced amplifier requires a separate control signal to connect the isolated ports of the output 3-dB quadrature coupler while achieving modulation of the impedance by changing the amplitude and phase of the control signal, which increases the complexity of operation to some extent. Based on the above background, the present invention provides a novel load modulation balanced amplifier architecture, so that the original dual-input signal is changed into a single-input signal, and the control amplifier can still perform the load modulation function, and fit the optimal impedance trajectory curve as much as possible. By adjusting the circuit bias, the automatic matching of the impedance of the circuit in the saturation and backspacing states is realized, so that a complex output matching structure is not needed. The design scheme improves the linearity and the gain stability of the circuit at the same time, and has flexible operation and simple structure.
Disclosure of Invention
An object of the present invention is to provide a load modulation balanced power amplifier, which solves the problem of complicated operation of control signals in the conventional load modulation balanced amplifier. The theory innovates the dual-input structure of the traditional load modulation balanced amplifier, and realizes the amplitude and phase modulation effect of a control signal in load modulation by setting the power distribution ratio and the bias voltage of the power divider based on the change rule of an impedance track curve. The impedance matching under different states is realized through flexible adjustment of the bias, and the method has the advantages of simple operation and easy popularization.
A load modulation balanced power amplifier comprises a power divider, a phase compensation network, an input 3-dB quadrature coupler, a balanced amplifier, a control amplifier and an output 3-dB quadrature coupler; the balanced amplifier comprises an upper balanced sub-amplifier and a lower balanced sub-amplifier;
the power divider is used for distributing the power of the single input signal source to the balanced amplifier and the control amplifier; the input power provided for the control amplifier is larger than the power flowing into the input ends of the upper and lower paths of balanced sub-amplifiers, so that the control amplifier is saturated in advance;
the phase compensation network is used for adjusting the phase difference of output currents of the control amplifier and the balance amplifier through a phase value which changes along with frequency, so that the modulation impedance track always falls in an optimal value area of load traction, and the phase compensation network provides a changed phase compensation value under different frequencies to fit an optimal impedance track curve.
Preferably, the characteristic impedance of the phase compensation network is 50 ohms, the phase variation range in the working frequency band is higher than that of a single series transmission line, and the current relative phase requirements under different frequencies can be met. No reflection occurs when the terminating impedance is 50 ohms, and only different phase compensation effects are generated on signals input into the coupler under different frequencies.
The input end of the input 3-dB orthogonal coupler is connected with the output end of the phase compensation network, and the straight-through end and the coupling end are respectively connected with the input end of the upper balanced amplifier and the input end of the lower balanced amplifier; the isolation termination is a 50 ohm resistor R3;
the input end of the output 3-dB quadrature coupler is connected with a 50 ohm load R5, the straight-through end and the coupling end are respectively connected with the output end of the lower balanced amplifier and the output end of the upper balanced amplifier, and the isolation end is connected with the output end of the control amplifier;
the input 3-dB orthogonal coupler and the output 3-dB orthogonal coupler enable the phases of the two paths of balanced sub-amplifiers at the output ports of the load modulation balanced power amplifier to be consistent;
preferably, the input 3-dB orthogonal coupler and the output 3-dB orthogonal coupler both adopt a two-stage bridge structure, so that the connection of each path of power amplifier is facilitated, the crossover is avoided, and the bandwidth of the couplers is increased;
the upper and lower paths of balanced sub-amplifiers have the same structure and the same size, and respectively comprise a balanced amplifier input matching circuit, an RC (resistance-capacitance) stabilizing circuit, a self-adaptive bias control circuit, a transistor P2, a drain electrode bias circuit and a blocking capacitor C8; the input end of the balanced amplifier input matching circuit is used as the input end of each path of balanced sub-amplifier, the output end of the balanced amplifier input matching circuit is connected with the input end of the RC stable circuit, and the output end of the RC stable circuit is connected with the grid electrode of the transistor; the input end of the self-adaptive bias control circuit is connected with a direct-current power supply, and the output end of the self-adaptive bias control circuit is connected with a transistor grid; the input end of the drain electrode biasing circuit is connected with a direct current power supply, the output end of the drain electrode biasing circuit is connected with the drain electrode of the transistor and then is simultaneously connected with one end of a blocking capacitor C8, and the other end of the blocking capacitor C8 is used as the output end of each path of balanced sub-amplifier;
the control amplifier comprises a control amplifier input matching circuit, an RC (resistor-capacitor) stabilizing circuit, a grid biasing circuit, a transistor P1, a drain biasing circuit, a control amplifier output matching circuit and a blocking capacitor C3; the input end of the input matching circuit of the control amplifier is used as the input end of the control amplifier, the output end of the input matching circuit of the control amplifier is connected with the input end of the RC stable circuit, and the output end of the RC stable circuit is connected with the grid electrode of the transistor P1; the input end of the grid biasing circuit is connected with a direct current power supply, and the output end of the grid biasing circuit is connected with the output end of the RC stabilizing circuit; the input end of the control amplifier output matching circuit is connected with one end of the drain electrode biasing circuit and then is connected with the drain electrode of the transistor P1, the other end of the drain electrode biasing circuit is connected with a direct current power supply, the output end of the control amplifier output matching circuit is connected with one end of a blocking capacitor C3, and the other end of the blocking capacitor C3 serves as the output end of the control amplifier and is connected with the isolating end of the output 3-dB quadrature coupler;
the input matching circuit of the balanced amplifier and the input matching circuit of the control amplifier are designed by adopting a low-pass filter matching design method, and the design of a low Q value improves the circuit bandwidth;
the RC stabilizing circuit consists of parallel RC circuits and is used for improving the stability of the amplifier and avoiding self-excitation in the actual test process;
the adaptive bias control circuit is used for dynamically adjusting the grid bias voltage along with the input power.
Preferably, the adaptive bias control circuit comprises a resistor R6, a grounded capacitor C9, a series microstrip line L17, a diode, a grounded capacitor C10 and a grounded resistor R7; one end of the resistor R6 is connected with a DC power supply VGsThe other end of the series microstrip line L17 is connected with one end of a grounding capacitor C9 and one end of a series microstrip line L17, the other end of the series microstrip line L17 is connected with the output end of the RC stable circuit and the gate of the transistor after the cathode of the diode is connected, and the anode of the diode is connected with one end of a grounding capacitor C10 and one end of a grounding resistor R7; the other end of the ground capacitor C9, the other end of the ground capacitor C10, and the other end of the ground resistor R7 are grounded.
The gate bias circuit of the control amplifier biases the control transistor P1 to class AB;
the grid bias voltage of the balanced amplifier is dynamically adjusted along with the input power, and the automatic matching of the load impedance in a backspacing state and a saturation state is realized.
The through and coupling end impedances of the output 3-dB quadrature coupler are also balanced amplifier load impedances, which relate to the amplitude and phase of the control amplifier:
Figure BDA0003388847360000041
Figure BDA0003388847360000042
wherein IcThe current flowing into the isolation end of the output 3-dB quadrature coupler from the output end of the amplifier is controlled, IbThe current flowing into the straight-through end or the coupling end of the output 3-dB orthogonal coupler from the output end of the balanced amplifier is equal, phi is the relative phase of the current of the isolation end of the output 3-dB orthogonal coupler and the current of the straight-through end of the output 3-dB orthogonal coupler, and Z isbRepresenting the load impedance of the balanced amplifier, theta representing the phase of the reflection coefficient of the load impedance of the balanced amplifier, Z0Representing the characteristic impedance of the output 3-dB quadrature coupler, j representing a complex number;
it was found from the above equations (1) to (2) that the modulation of the load impedance of the balanced amplifier is mainly by the current ratio Ic/IbAnd the effect of the relative phase phi. Under the single-input structure provided by the invention, phi can be considered unchanged, so the research on load impedance modulation of the balanced amplifier is transferred to the main variable Ic/IbThe study of (1). As can be seen from the observation of the formulas (1) to (2), the current ratio Ic/IbReflects both the amplitude and phase modulation of the impedance. Therefore, the current ratio I can be realized by the adjustment of the power divider and the bias voltagec/IbThereby achieving the effect of impedance matching between the back-off point and the saturation point.
Another object of the present invention is to provide a method for implementing self-matching of a load modulation balanced power amplifier, which is characterized by comprising the following steps:
the method comprises the following steps: designing an RC (resistor-capacitor) stabilizing circuit, and continuously adjusting the values of resistors R4 and R2 and capacitors C2 and C7 to enable a stabilizing parameter to be larger than 1 in a full frequency band;
step two: determining input and output impedances of the control amplifier transistor and balancing the optimal input impedance of the amplifier transistor according to the set working frequency and the bias size so as to facilitate subsequent matching;
step three: designing an input matching circuit of a control amplifier, an output matching circuit of the control amplifier and an input matching circuit of a balanced amplifier according to the saturation impedance of the transistor;
step four: designing an input 3-dB orthogonal coupler and an output 3-dB orthogonal coupler, wherein the phases of a straight-through end and a coupling end of the input 3-dB orthogonal coupler and the output 3-dB orthogonal coupler are different by 90 degrees, and the amplitudes of two paths of signals are equal; the input 3-dB orthogonal coupler isolation port is connected with a 50 ohm resistor, and the input port of the output 3-dB orthogonal coupler is connected with a 50 ohm load;
step five: designing a power divider, wherein the impedances of three ports are 50 ohms, the power divider divides a single input signal into two paths of signals, the specific power division proportion is determined according to a debugging result, and the two paths of signals are respectively sent to an input port of a control amplifier and an input port of a phase compensation network connected with an input 3-dB quadrature coupler;
step six: designing a self-adaptive bias control circuit, rectifying input power flowing into a grid electrode of a transistor by a forward diode, and converting the input power into the change of grid voltage through a series resistor R6;
step seven: the debugged control amplifier input matching circuit, the control amplifier output matching circuit, the balanced amplifier input matching circuit, the RC stabilizing circuit, the self-adaptive bias control circuit, the transistors P1 and P2, the input 3-dB quadrature coupler, the output 3-dB quadrature coupler and the power divider are combined and debugged, and then the optimal impedance track dragged by the load is fitted by changing the impedance. The method comprises the following steps:
1) saturated load impedance of transistor P2
In the case of single input, P should be maintained in order to increase the impedance in the low power regioncontrol/PbalanceGreater than a threshold value a, a being an empirical setting by those skilled in the art, a > 1. Wherein P iscontrolIndicating the magnitude of the control amplifier output power, PbalanceIndicating the output power level of the balanced sub-amplifier, the control amplifier is required to saturate early and the balanced sub-amplifier is required to turn on late. Therefore, the control amplifier is firstly set to be biased in the AB class, and the two-way balanced sub-amplifier is biased in the C class. On the basis, the current I at the output end of the amplifier is analyzed and controlledcAnd balancing the output current I of the sub-amplifierbA change in (c).
Assuming the amplifier current is an ideal linear model, the current is normalized according to the drive level:
Figure BDA0003388847360000051
Figure BDA0003388847360000061
for the sake of simplifying the description, the setting ratio β ═ Ib,max/Ic,max，Ic,maxRepresenting the maximum value of the output current of the control amplifier, Ib,maxRepresenting the maximum value, k, of the output current of the balanced sub-amplifier1Denotes the drive level, k, at which P2 is open2Indicating the drive level at which P1 is saturated. In general, k is1≤k2。
When the control amplifier and the two paths of balanced sub-amplifiers are saturated, the output power of the whole circuit reaches the maximum value, and the corresponding saturated load impedance Z is obtainedb,satCan be expressed as:
Figure BDA0003388847360000062
where θ represents the phase of the reflection coefficient of the load impedance of the balanced amplifier, Z0To representOutputting the characteristic impedance of the 3-dB quadrature coupler, wherein j represents a complex number;
total output power PallThe sum of the output powers of the control amplifier and the two paths of balanced sub-amplifiers is represented by the general expression:
Figure BDA0003388847360000063
wherein IcRepresenting the control amplifier output current; i isbRepresenting the output current of the balanced sub-amplifier, Re (Z)b) Representing the load impedance ZbThe real part of (a).
Simplifying the above formula (6) to obtain the total saturated output power Psat：
Figure BDA0003388847360000064
The expression for the total saturated output power is only related to the parameter β, φ. According to the datasheet of the transistors, the power sum P of the transistors P1 and P2 can be obtainedsatAt this goal, the rationality and efficiency of the synthetic data is maximized, and the optimal values of β and φ are sought after in iterative comparisons with the results of load traction. When the values of beta and phi are determined, the saturated load impedance Z can be obtainedb,sat。
2) Back-off impedance of transistor P2
Defining that beta is constant throughout the modulation process, the value of phi can be considered unchanged, thereby further analyzing the low power phase of P2. At a driving level of k2At the moment in time, transistor P1 has just saturated, controlling the amplifier output current to reach a maximum value Ic,maxBalancing the output current of the sub-amplifier
Figure BDA0003388847360000071
The modulated back-off point load impedance Zb,backComprises the following steps:
Figure BDA0003388847360000072
the total output power of the control amplifier and the balance amplifier in the back-off state can be obtained as follows:
Figure BDA0003388847360000073
the backoff range may be determined by comparing PsatAnd PbackObtaining:
Figure BDA0003388847360000074
given an OBO, PbackIs determined in the formula
Figure BDA0003388847360000075
This monomial is unknown and Z can be solved by solving equation (10)b,backThe real and imaginary parts of (c) are determined. To ensure Z obtained in this wayb,backIs realized by analyzing the load impedance Z of the back-off pointb,backReal and imaginary part of (c):
Figure BDA0003388847360000076
the real part of the impedance must be a positive number to have practical physical significance, so the constraint implied by equation (11) is:
Figure BDA0003388847360000077
it is equivalent to a control power with the back-off power at minimum saturation, which also corresponds to IcAnd IbPhysical meaning of the current model.
3) The grid voltage is changed through the self-adaptive bias control circuit, the control on the output current magnitude and the relative phase of the control amplifier and the balance amplifier is realized, and the Z is ensuredb,satAnd Zb,backSo as to be in returnThe state of the switch can still keep high efficiency, and high output power and high efficiency are obtained when the switch is saturated.
Step eight: and designing a phase compensation network according to the relative phase difference of the two paths of currents of the control amplifier and the balance amplifier under different frequencies, and then further combining the phase compensation network with the seven networks to debug the complete circuit.
The working principle of the impedance self-matching load modulation balanced power amplifier provided by the invention is as follows: by controlling the power division ratio and the self-adaptive bias control circuit, the control amplifier is saturated in advance, the impedance reflection coefficient amplitude is increased at low power, and the purpose of increasing the load impedance and further increasing the efficiency at low power is achieved. With increasing output power of the balanced amplifier, Ic/IbThe value of (3) is decreased, so that the reflection coefficient amplitude of the load impedance is reduced, the phase is gradually increased, and the impedance trajectory rule obtained by load traction is met, which is also a common method of a single-input load modulation balanced amplifier. Because the matching of the impedance at low power and the matching of the impedance at saturation are related to the grid bias of the balanced amplifier, the matching of the impedance under the states is realized and the gain linearity of the circuit is improved through the control of the self-adaptive grid bias.
The invention has the beneficial effects that: the amplitude and the phase of the impedance are modulated by using the change ratio of power to current and adopting a self-adaptive bias control circuit, so that the traditional double-input structure is replaced. And the phase compensation network connected with the input end of the input 3-dB orthogonal coupler is used for compensating the dispersion effect of the microstrip line. In the case of broadband matching, the bandwidth of the circuit is only affected by the coupler. The design of the two-stage bridge further improves the bandwidth of the circuit. The modulation of the impedance of the balanced amplifier does not need the participation of an output matching network, thereby realizing the purpose of load modulation and simplifying the whole circuit structure.
Drawings
Fig. 1 is a schematic structural diagram of an impedance self-matching load modulation balanced power amplifier in the present invention.
Fig. 2 is a schematic diagram of the structure of the phase compensation network in the present invention and the simulation of the phase offset using simulation software.
FIG. 3 is a schematic diagram of the adaptive bias control circuit of the present invention and simulation of dynamic gate voltage adjustment with input power using simulation software.
FIG. 4 is a schematic diagram of an amplifier modulation impedance trace of the present invention simulated in simulation software over a wide frequency band (3.4GHz-3.9 GHz).
FIG. 5 is a graph showing the simulation results of the present invention in a wide frequency band (3.4GHz-3.9GHz) using simulation software.
Detailed Description
The following are specific embodiments of the present invention and are further described with reference to the drawings, but the present invention is not limited to these embodiments.
Fig. 1 is a schematic structural diagram of an impedance self-matching load modulation balanced power amplifier according to the present invention, where the power amplifier includes a power divider, a phase compensation network, two balanced sub-amplification circuits, one control amplifier circuit, and two 3-dB quadrature couplers. The balanced sub-amplifier circuit comprises a broadband input matching circuit, an RC (resistor-capacitor) stabilizing circuit, a self-adaptive bias control circuit, a drain electrode bias circuit and a blocking capacitor; the control amplifier circuit comprises a broadband input matching circuit, an RC stabilizing circuit, a grid biasing circuit, a broadband output matching circuit, a drain biasing circuit and a blocking capacitor.
The power divider is a Wilkinson power divider, and the structure is more compact. The microstrip line voltage regulator specifically comprises a microstrip line L1, a microstrip line L2 and a resistor R1; one end of a microstrip line L1 is connected with one end of a microstrip line L2 and then connected with a single input signal source, and the other end of the microstrip line L1 is connected with one end of a resistor R1 and then connected with a control amplifier; the other end of the microstrip line L2 is connected with the other end of the resistor R1 and then connected with the input end of the phase compensation network.
The phase compensation network adopts a structure of combining a microstrip line and a capacitor as shown in figure 2, and changes the relative phase phi of two paths of current; varying phase compensation values are provided at different frequencies to fit the optimal impedance trajectory curve. The microstrip line voltage regulator specifically comprises a series microstrip line L3, a series capacitor C4, a parallel short-circuit microstrip line L4, a series capacitor C5 and a series microstrip line L5; one end of the series microstrip line L3 is connected with a signal output by the power divider, the other end of the series microstrip line L3 is connected with one end of the series capacitor C4, the other end of the series capacitor C4 is connected with one end of the parallel short-circuit microstrip line L4 and one end of the series capacitor C5, the other end of the series capacitor C5 is connected with one end of the series microstrip line L5, the other end of the series microstrip line L5 is connected with the input end of the input 3-dB quadrature coupler, and the other end of the parallel short-circuit microstrip line L4 is grounded.
The 3-dB quadrature coupler is a two-stage 3-dB quadrature coupler, and the bandwidth range is further improved by a multi-stage structure. The input coupler is structurally composed of a microstrip line L6, a microstrip line L7, a microstrip line L8, a microstrip line L9, a microstrip line L10, a microstrip line L11 and a microstrip line L12 in sequence; the output 3-dB orthogonal coupler has the structural sequence of a microstrip line L28, a microstrip line L29, a microstrip line L30, a microstrip line L31, a microstrip line L32, a microstrip line L33 and a microstrip line L34;
one end of the microstrip line L6 is connected with one end of the microstrip line L7, and the connection part is connected with the output end of the phase compensation network, namely the output end of the series microstrip line L5; the other end of the microstrip line L7 is connected with one end of the microstrip line L8 and one end of the microstrip line L10, the other end of the microstrip line L10 is connected with the microstrip line L11, and the connection position is a coupling port of the coupler and is connected with the input end of the balanced amplifier; the other end of the microstrip line L11 is connected with the microstrip line L12, and the connection part is a coupler straight-through end which is connected with the input end of the other path of balance amplifier; the other end of the microstrip line L12 is connected with the other end of the microstrip line L8 and then connected with one end of the microstrip line L9, the other end of the microstrip line L9 is connected with the other end of the microstrip line L6, a 50-ohm resistor R3 is connected at the interface, and the other end of the R3 is grounded;
one end of the microstrip line L28 is connected with the microstrip line L29; the other end of the microstrip line L29 is connected with one end of the microstrip line L30 and one end of the microstrip line L32, and the other end of the microstrip line L32 is connected with the microstrip line L33 and is also connected with the output end of the control amplifier; the other end of the microstrip line L33 is connected with the microstrip line L34, the connection point is connected with a 50-ohm load R5, and the other end of the R5 is grounded; the other end of the microstrip line L34 is connected to the other end of the microstrip line L30 and then to one end of the microstrip line L32, and the other end of the microstrip line L31 is connected to the other end of the microstrip line L28.
The broadband input and output matching circuits are both constructed by adopting a low-Q-value Chebyshev step-type broadband matching method, in order to ensure that the structure has universality and solve the problem of frequency limitation of lumped elements, series low-impedance microstrip lines are used for replacing series inductors, and series high-impedance microstrip lines are used for replacing parallel capacitors, so that a microstrip line structure with high and low impedance alternation is finally formed. The matching circuit structure of all the series microstrip lines expands the bandwidth and simplifies the layout at the same time.
The structure sequence of the broadband input matching circuit of the control amplifier is series capacitor C1, series microstrip line L19, series microstrip line L20 and series microstrip line L21; the input end of the series DC-blocking capacitor C1 is connected with the connection point of the microstrip line L1 and the resistor R1. The output end of the series DC blocking capacitor C1 is connected with the input end of the series microstrip line L19, the output end of the series microstrip line L19 is connected with the series microstrip line L20, the other end of the series microstrip line L20 is connected with the input end of the series microstrip line L21, and the other end of the series microstrip line L21 is connected with the input end of the RC stabilizing circuit.
The RC stabilizing circuit of the control amplifier consists of a parallel resistor and a capacitor, and a consumption component is added at the input end of the transistor, so that the stability of the amplifier is improved.
The control amplifier grid bias circuit biases the transistor to AB type, and is composed of a parallel microstrip line with one end connected with a power supply and grounded and the other end connected with the input end of the RC stable circuit, and is used for providing grid bias voltage.
The structure sequence of the control amplifier broadband output matching circuit is a series microstrip line L24, a series microstrip line L25, a series microstrip line L26 and a series microstrip line L27; the drain of the control amplifier transistor P1 is connected with the input end of a series microstrip line L24, the output end of a series microstrip line L24 is connected with the input end of a series microstrip line L25, the other end of the series microstrip line L25 is connected with a series microstrip line L26, the output end of a series microstrip line L26 is connected with the input end of a series microstrip line L27, the output end of the series microstrip line L27 is connected with a series DC blocking capacitor C3, and the output end of the series DC blocking capacitor C3 is connected with an output 3-dB quadrature coupler microstrip line L32 and a microstrip line L33.
The drain electrode bias circuit of the control amplifier is composed of a parallel microstrip line with one end connected with a power supply and grounded and the other end connected with the drain electrode of the transistor P1 and is used for providing drain electrode direct current voltage.
The structure sequence of the balanced amplifier broadband input matching circuit is series capacitor C6, series microstrip line L13, series microstrip line L14, series microstrip line L15 and series microstrip line L16; the input end of the series DC blocking capacitor C6 is connected with the connection point of the microstrip line L10 and the microstrip line L11, and the input end of the balance amplifier DC blocking capacitor C6 in the other path is connected with the connection point of the microstrip line L11 and the microstrip line L12. The output end of the series DC blocking capacitor C6 is connected with the input end of a series microstrip line L13, the output end of a series microstrip line L13 is connected with a series microstrip line L14, the other end of the series microstrip line L14 is connected with the input end of a series microstrip line L15, the output end of a series microstrip line L15 is connected with a series microstrip line L16, and the other end of the series microstrip line L16 is connected with the input end of an RC stabilizing circuit.
The self-adaptive bias control circuit of the balanced amplifier has the structural sequence of a resistor R6, a grounded capacitor C9, a series microstrip line L17, a diode, a grounded capacitor C10 and a grounded resistor R7; one end of the resistor R6 is connected with a direct current power supply, the other end of the resistor R6 is connected with the other end of the grounding capacitor C9 and then connected with the series microstrip line L17, the other end of the L17 is connected with the cathode of the diode, and the anode of the diode is connected with the grounding capacitor C10 and the other end of the grounding resistor R7. The node of the microstrip line L7 connected with the cathode of the diode is connected with the output end of the stabilizing circuit and the gate of the transistor.
The drain of the balanced amplifier transistor P2 is connected to the input end of the DC blocking capacitor C8, the other end of C8 is connected to the joint of the microstrip line L28 and the microstrip line L29, and the output end of the other DC blocking capacitor C8 is connected to the microstrip line L28 and the microstrip line L31. The transistor type, the bias size and the matching structure of the two paths of balanced amplifiers are completely the same.
When the load modulation balanced amplifier is designed to work in a frequency band of 3.4GHz-3.9GHz, the grid bias is changed through the self-adaptive bias control circuit, the output current ratio of the control power amplifier and the balanced power amplifier can be controlled, the automatic matching of output impedance is realized, and high-efficiency output can be realized in a wider dynamic range.
The design method of the impedance self-matching load modulation balanced power amplifier is realized by the following steps:
the method comprises the following steps: and designing an RC (resistor-capacitor) stabilizing circuit, and continuously adjusting the values of the resistor and the capacitor to ensure that the stabilizing parameter is more than 1 in the full frequency band. Specifically, circuit simulation software can be used to analyze and compare the stability of the amplifier before and after the RC stabilizing circuit is added. In the example, the control amplifier selects a 50 ohm resistor and a 2.5pF capacitor to be connected in parallel as the final form of the stabilizing circuit, and the balance amplifier selects a 50 ohm resistor and a 4pF capacitor to be connected in parallel as the final form of the stabilizing circuit.
Step two: the input-output impedance of the transistor is determined for subsequent matching. The specific method comprises the following steps: the scalable transistor model in the GaN _ HEMT process provided by the foundry company and the previously designed stable circuit are brought into a template of load traction and source traction of specific circuit simulation software, and a compromise frequency point is selected in the whole working frequency band to obtain the optimal ranges of input impedance, output impedance and output impedance during power rollback. Meanwhile, it is observed that as the frequency increases, the phase of the output impedance reflection coefficient of the balanced amplifier becomes larger and larger, and the impedance locus is closer to the real axis, which is the theoretical basis for designing a phase compensation network later.
Step three: and D, using the optimal input impedance obtained in the step two to make a broadband input matching circuit. The input matching circuit adopts microstrip lines with high impedance and low impedance which are alternated, a step-type broadband matching path is presented on a Smith diagram to realize broadband matching, the specific method is to match capacitance and inductance by utilizing known matching technologies such as Chebyshev and the like, and then the impedance and the electrical length of the microstrip lines are solved by utilizing the change of the rational inquiry.
Step four: a two-stage 3-dB orthogonal coupler is designed, the coupling degree is required to be close to-3 dB in a working frequency band, the isolation degree is less than-20 dB in the working frequency band, and the phase of a coupling end signal leads a straight-through end signal by 90 degrees. And (3) solving the impedance value of each bridge arm by using an odd-even mode analysis method, and measuring the port characteristics by using simulation software.
Step five: the Wilkinson power divider is designed, and the impedances of the three ports are all 50 ohms. And generating a basic structure of the power divider by utilizing a model in simulation software according to the set working frequency and the set working bandwidth. The process of analyzing the load modulation may find that at low power the control amplifier should be saturated early, and therefore the proportion of power flowing all the way to the control amplifier should be increased.
Step six: the self-adaptive bias control circuit is designed, an input radio frequency signal is converted into direct current flowing from the anode to the cathode of the diode by utilizing the forward rectification function of the diode, the parallel capacitor C10 influences the radio frequency power flowing to the diode and further influences current increment, and the current is converted into the grid voltage of the transistor through the resistor R6.
Step seven: and combining and debugging the debugged broadband input/output matching circuit, the RC stabilizing circuit, the self-adaptive bias control circuit, the bias circuit, the transistor, the 3-dB quadrature coupler circuit and the power divider. During debugging, the adjusting capacitor C10, the resistor R6 and the resistor R7 realize gate bias control, so that the impedance change track is fitted to the optimal impedance track of load traction as much as possible. And designing a phase compensation network according to the relative phase difference of the two paths of current under different frequencies. And after the phase compensation network is combined with the network, debugging the complete circuit. The specific method comprises the following steps:
2) saturated optimal impedance of P2
First, the turn-on sequence of the control amplifier and the balance amplifier is analyzed for the single input case: to increase the impedance in the low power region, P should be maintainedcontrol/PbalanceAt a higher value, the power amplifier is required to be controlled to be saturated in advance, and the balanced power amplifier is started later. Therefore, the control amplifier is firstly set to be biased in the AB class, and the two-way balance amplifier is biased in the C class. On the basis, the current I at the output end of the amplifier is analyzed and controlledcAnd balancing the amplifier output current IbA change in (c).
Assuming that the power amplifier current is an ideal linear model, normalizing the current according to the driving level:
Figure BDA0003388847360000131
Figure BDA0003388847360000132
for the sake of simplifying the description, the setting ratio β ═ Ib,max/Ic,max，k1Denotes the drive level, k, at which P2 is open2Indicating the drive level at which P1 is saturated. In general, k is1≤k2。
When the three power amplifiers are saturated, the output power of the whole circuit reaches the maximum value, and the corresponding saturated impedance Z is obtainedb,satCan be expressed as:
Figure BDA0003388847360000133
the total output power is the sum of the output powers of the three power amplifiers, and the general expression is as follows:
Figure BDA0003388847360000134
simplifying the above formula to obtain the saturation power Psat：
Figure BDA0003388847360000135
The expression for the saturated output power is only related to the parameter β, φ. And according to the datasheet of the transistors, the power sum of the three transistors can be obtained, the rationality and the efficiency of the comprehensive data are maximized under the aim, and the optimal values of beta and phi are searched by repeatedly and iteratively comparing with the optimal values obtained in the second step. When the values of β and φ are determined, a saturated optimal impedance can be obtained.
2) Back-off impedance of P2
The parameters β and Φ obtained above are considered as the definition of β is not changed in the whole modulation process, and the value of Φ is considered as not changed, so that the low power stage of P2 can be further analyzed. At a driving level of k2At the moment when the control amplifier is saturated, IcHas reached a maximum value Ic,max，IbCan be expressed as
Figure BDA0003388847360000141
Modulated load impedance Zb,backComprises the following steps:
Figure BDA0003388847360000142
the output power at this time can be obtained as:
Figure BDA0003388847360000143
the backoff range may be determined by comparing PsatAnd PbackObtaining:
Figure BDA0003388847360000144
given an OBO, PbackIs determined in the formula
Figure BDA0003388847360000145
This monomial is unknown, and by solving it, Z can be expressedb,backThe real and imaginary parts of (c) are determined. To ensure Z obtained in this wayb,backIt can be realized that the real and imaginary parts of the back-off impedance are analyzed:
Figure BDA0003388847360000146
the real part of the impedance must be a positive number to have practical physical meaning, so the implicit constraint of the above equation is:
Figure BDA0003388847360000147
which is equivalent to the maximum back-off powerControl power at low saturation, which also corresponds to IcAnd IbPhysical meaning of the current model.
3) In the actual design, the backspacing range needs to be reasonably selected, and Z is obtainedb,satAnd Zb,backThen, by changing beta, phi, k1And k2Impedance matching can be performed, and particularly, the work ratio and the gate bias can be changed. Since the two impedance determinations are both made by analyzing the current relationship, both are bias dependent and are not independent of each other during the change. Bias conditions to achieve high impedance and improved efficiency at low power will result in gain compression, reduced output power and a shift in the saturation impedance point, thus allowing for the addition of an adaptive bias control circuit to vary the gate voltage while achieving Zb,satAnd Zb,backIs matched. And in low power, the balanced power amplifier is in deep C-type bias, so that the impedance reflection coefficient is improved. Along with the starting of the power amplifier, the grid bias voltage is improved, the conduction angle of the balanced power amplifier is increased, and the optimal matching during saturation is realized.
When the power amplifier is not at other frequency points of the central frequency, the matching condition of each path of power amplifier is changed due to the change of the electrical length of the microstrip line, so that the relative phase phi is changed, and the impedance point is shifted. For the correction of the impedance point, the most direct method is to compensate the phase change, and the change law of the phase required by the phase compensation network added before the control amplifier or the input 3-dB quadrature coupler is opposite. In this invention, the phase change before the input 3-dB quadrature coupler conforms to the general rule that microstrip line electrical length varies with frequency. The phase of a single series microstrip line can only realize about 20-degree change in the range of 3GHz-4GHz, and the phase compensation network shown in FIG. 2 can provide 45-degree change in the range of 3GHz-4GHz, so that the phase change requirement of the circuit can be met, and the frequency band can be further widened.
Fig. 3 is a block diagram of an adaptive bias control circuit and a bias variation range obtained using simulation software. The forward diode will be from RFinThe rf ac signal is rectified to a forward dc current, and the size of the capacitor C10 affects the current increment. The current increment is converted to a voltage increment through a series resistor R6. Lambda/4 microstrip line L17 implementationOpen circuit to radio frequency signal, capacitor C9 is bypass capacitor, VxIs a dynamically varying gate bias voltage. Software simulation proves that the structure can realize the dynamic adjustment of the gate bias voltage along with the input power.
FIG. 4 is a trace of the impedance change observed at different frequencies after the complete circuit is connected, and it can be observed that the impedance falls substantially within the area of load pulling, and the impedance level at low power is higher than that at saturation; under the action of the phase compensation network, the phase of the impedance gradually increases with the increase of the frequency.
Fig. 5 is a diagram showing simulation results obtained by the circuit simulation software according to the present invention, and it can be known from the simulation results that the saturated output power is greater than 47dBm, the saturated output efficiency is greater than 65%, and the 6dB back-off efficiency is greater than 55% in the frequency band range of 3.4GHz-3.9 GHz. The above results demonstrate the function of the load modulation balanced amplifier.
The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1.一种负载调制平衡功率放大器，其特征在于包括功分器、相位补偿网络、输入3-dB正交耦合器、平衡放大器、控制放大器和输出3-dB正交耦合器；所述平衡放大器包括上下两路平衡子放大器；1. a load modulation balanced power amplifier, it is characterized in that comprising power divider, phase compensation network, input 3-dB quadrature coupler, balanced amplifier, control amplifier and output 3-dB quadrature coupler; Described balanced amplifier Including upper and lower balanced sub-amplifiers; 所述功分器用于将单输入信号源功率分配至平衡放大器和控制放大器；提供给控制放大器的输入功率应大于流入上下两路平衡子放大器输入端的功率，使得控制放大器提早饱和；The power divider is used to distribute the power of the single input signal source to the balanced amplifier and the control amplifier; the input power provided to the control amplifier should be greater than the power flowing into the input ends of the upper and lower balanced sub-amplifiers, so that the control amplifier is saturated in advance; 所述相位补偿网络用于通过随频率变化的相位值，调节控制放大器和平衡放大器输出电流相位差，使得调制阻抗轨迹始终落在负载牵引的最优值区域，在不同频率下，提供变化的相位补偿值，来拟合最优阻抗轨迹曲线；The phase compensation network is used to adjust the phase difference between the output currents of the control amplifier and the balance amplifier through the phase value that changes with frequency, so that the modulated impedance track always falls in the optimal value region of the load pull, and provides a changing phase at different frequencies. compensation value to fit the optimal impedance trajectory curve; 所述输入3-dB正交耦合器的输入端接相位补偿网络的输出端，直通端和耦合端分别接上路平衡放大器的输入端、下路平衡放大器的输入端；隔离端接50欧姆电阻R3；The input end of the input 3-dB quadrature coupler is connected to the output end of the phase compensation network, the straight-through end and the coupling end are respectively connected to the input end of the upper circuit balanced amplifier and the input end of the lower circuit balanced amplifier; the isolation end is connected to a 50 ohm resistor R3 ; 所述输出3-dB正交耦合器的输入端接50欧姆负载R5，直通端和耦合端分别接下路平衡放大器的输出端、上路平衡放大器的输出端，隔离端接控制放大器的输出端；The input end of the output 3-dB quadrature coupler is connected to the 50 ohm load R5, the straight-through end and the coupling end are respectively connected to the output end of the lower circuit balanced amplifier, the output end of the upper circuit balanced amplifier, and the isolation end is connected to the output end of the control amplifier; 所述输入3-dB正交耦合器、输出3-dB正交耦合器使得两路平衡子放大器在负载调制平衡功率放大器的输出端口的相位一致；The input 3-dB quadrature coupler and the output 3-dB quadrature coupler make the phases of the two balanced sub-amplifiers consistent at the output ports of the load modulation balanced power amplifier; 所述自适应偏压控制电路用于随输入功率动态调整栅级偏置电压；所述自适应偏压控制电路包括电阻R6、接地电容C9、串联微带线L17、二极管、接地电容C10和接地电阻R7；电阻R6的一端接直流电源VGS，另一端与接地电容C9的一端、串联微带线L17的一端连接，串联微带线L17的另一端与二极管的负极相连后RC稳定电路输出端和晶体管栅极相连，二极管的正极与接地电容C10的一端、接地电阻R7的一端连接；接地电容C9的另一端的另一端、接地电容C10的另一端和接地电阻R7的另一端接地；The adaptive bias control circuit is used to dynamically adjust the gate bias voltage with the input power; the adaptive bias control circuit includes a resistor R6, a grounding capacitor C9, a series microstrip line L17, a diode, a grounding capacitor C10 and a grounding Resistor R7; one end of the resistor R6 is connected to the DC power supply V GS , the other end is connected to one end of the grounding capacitor C9 and one end of the series microstrip line L17, and the other end of the series microstrip line L17 is connected to the negative pole of the diode and the output end of the RC stabilization circuit It is connected to the gate of the transistor, and the anode of the diode is connected to one end of the grounding capacitor C10 and one end of the grounding resistor R7; the other end of the other end of the grounding capacitor C9, the other end of the grounding capacitor C10 and the other end of the grounding resistor R7 are grounded; 所述控制放大器的栅极偏置电路将控制晶体管P1偏置到AB类；The gate bias circuit of the control amplifier biases the control transistor P1 to class AB; 所述平衡放大器的栅极偏压随输入功率动态调整，实现负载阻抗在回退和饱和状态的自动匹配。The gate bias voltage of the balanced amplifier is dynamically adjusted with the input power, so as to realize the automatic matching of the load impedance in the fallback and saturation states. 2.如权利要求1所述的一种负载调制平衡功率放大器，其特征在于所述的相位补偿网络特征阻抗为50欧姆。2 . The load modulation balanced power amplifier according to claim 1 , wherein the characteristic impedance of the phase compensation network is 50 ohms. 3 . 3.如权利要求1所述的一种负载调制平衡功率放大器，其特征在于所述输入3-dB正交耦合器和输出3-dB正交耦合器均采用两级电桥结构。3 . The load modulation balanced power amplifier according to claim 1 , wherein the input 3-dB quadrature coupler and the output 3-dB quadrature coupler both adopt a two-stage electric bridge structure. 4 . 4.如权利要求1所述的一种负载调制平衡功率放大器，其特征在于所述上下两路平衡子放大器均包括平衡放大器输入匹配电路、RC稳定电路、自适应偏压控制电路、晶体管P2、漏极偏置电路、隔直电容C8；平衡放大器输入匹配电路的输入端作为每路平衡子放大器的输入端，输出端接RC稳定电路的输入端，RC稳定电路的输出端与晶体管栅极连接；自适应偏压控制电路的输入端接直流电源，输出端接晶体管栅极；漏极偏置电路的输入端接直流电源，输出端与晶体管的漏极连接后同时与隔直电容C8的一端连接，隔直电容C8的另一端作为每路平衡子放大器的输出端。4. a kind of load modulation balanced power amplifier as claimed in claim 1 is characterized in that described upper and lower two-way balanced sub-amplifiers all comprise balanced amplifier input matching circuit, RC stabilization circuit, adaptive bias control circuit, transistor P2, Drain bias circuit, DC blocking capacitor C8; the input end of the balanced amplifier input matching circuit is used as the input end of each balanced sub-amplifier, the output end is connected to the input end of the RC stabilization circuit, and the output end of the RC stabilization circuit is connected to the transistor gate ;The input terminal of the adaptive bias control circuit is connected to the DC power supply, and the output terminal is connected to the gate of the transistor; the input terminal of the drain bias circuit is connected to the DC power supply, and the output terminal is connected to the drain of the transistor and is connected to one end of the DC blocking capacitor C8. connected, the other end of the DC blocking capacitor C8 is used as the output end of each balanced sub-amplifier. 5.如权利要求1所述的一种负载调制平衡功率放大器，其特征在于所述控制放大器包括控制放大器输入匹配电路、RC稳定电路、栅极偏置电路、晶体管P1、漏极偏置电路、控制放大器输出匹配电路、隔直电容C3；控制放大器输入匹配电路的输入端作为控制放大器的输入端，控制放大器输入匹配电路的输出端与RC稳定电路的输入端连接，RC稳定电路的输出端与晶体管P1栅极连接；栅极偏置电路的输入端接直流电源，输出端接RC稳定电路的输出端；控制放大器输出匹配电路的输入端接漏极偏置电路的一端后与晶体管P1漏极连接，漏极偏置电路的另一端接直流电源，控制放大器输出匹配电路的输出端接隔直电容C3的一端，隔直电容C3的另一端作为控制放大器的输出端，接输出3-dB正交耦合器的隔离端。5. A load modulation balanced power amplifier according to claim 1, wherein the control amplifier comprises a control amplifier input matching circuit, an RC stabilization circuit, a gate bias circuit, a transistor P1, a drain bias circuit, The control amplifier output matching circuit and the DC blocking capacitor C3; the input end of the control amplifier input matching circuit is used as the input end of the control amplifier, the output end of the control amplifier input matching circuit is connected with the input end of the RC stabilization circuit, and the output end of the RC stabilization circuit is connected to the input end of the RC stabilization circuit. The gate of transistor P1 is connected; the input end of the gate bias circuit is connected to the DC power supply, and the output end is connected to the output end of the RC stabilization circuit; the input end of the output matching circuit of the control amplifier is connected to one end of the drain bias circuit and then connected to the drain of the transistor P1. Connect, the other end of the drain bias circuit is connected to the DC power supply, the output end of the control amplifier output matching circuit is connected to one end of the DC blocking capacitor C3, the other end of the DC blocking capacitor C3 is used as the output end of the control amplifier, and the output 3-dB positive The isolated side of the cross-coupler. 6.如权利要求1所述的一种负载调制平衡功率放大器，其特征在于所述输出3-dB正交耦合器的直通端和耦合端阻抗也是平衡放大器负载阻抗，其与控制放大器的幅度和相位的关系：6. a kind of load modulation balanced power amplifier as claimed in claim 1, it is characterized in that the straight-through end and coupling end impedance of described output 3-dB quadrature coupler are also balanced amplifier load impedance, it and the amplitude of control amplifier and Phase relationship:
Figure FDA0003388847350000021
Figure FDA0003388847350000021
Figure FDA0003388847350000022
Figure FDA0003388847350000022
 其中Ic是控制放大器输出端流入输出3-dB正交耦合器隔离端的电流大小，Ib是平衡放大器输出端流入输出3-dB正交耦合器直通端或耦合端的电流大小，φ是输出3-dB正交耦合器隔离端电流与输出3-dB正交耦合器直通端电流的相对相位，Zb表示平衡放大器负载阻抗，θ表示平衡放大器负载阻抗反射系数的相位，Z0表示输出3-dB正交耦合器的特征阻抗，j表示复数；where I c is the current flowing from the output end of the control amplifier into the isolated end of the output 3-dB quadrature coupler, I b is the current flowing from the output end of the balanced amplifier into the straight or coupled end of the output 3-dB quadrature coupler, and φ is the output 3 The relative phase of the -dB quadrature coupler isolation terminal current and the output 3-dB quadrature coupler through terminal current, Z b represents the balanced amplifier load impedance, θ represents the phase of the balanced amplifier load impedance reflection coefficient, Z 0 represents the output 3- The characteristic impedance of the quadrature coupler in dB, j is a complex number; 由上式(1)-(2)可知，平衡放大器负载阻抗的调制主要受电流比Ic/Ib和相对相位φ的影响；在单输入结构下φ认为是不发生改变的，因此通过功分器和偏置电压的调整实现对电流比Ic/Ib的控制，从而达到回退点和饱和点阻抗匹配的效果。From the above equations (1)-(2), it can be seen that the modulation of the load impedance of the balanced amplifier is mainly affected by the current ratio I c /I b and the relative phase φ; in the single-input structure, φ is considered to be unchanged, so through the power The adjustment of the divider and the bias voltage realizes the control of the current ratio I c /I b , so as to achieve the effect of impedance matching at the fallback point and the saturation point. 7.如权利要求1-6任一所述的一种负载调制平衡功率放大器自匹配实现方法，其特征在于该方法包括以下步骤：7. The method for realizing self-matching of a load modulation balanced power amplifier according to any one of claims 1-6, characterized in that the method comprises the following steps: 步骤一：设计RC稳定电路，不断调整电阻R4、R2和电容C2、C7的值使得稳定参数在全频带大于1；Step 1: Design an RC stabilization circuit, and constantly adjust the values of resistors R4, R2 and capacitors C2, C7 so that the stabilization parameter is greater than 1 in the full frequency band; 步骤二：根据设置的工作频率和偏置大小，确定控制放大器晶体管的输入、输出阻抗，以及平衡放大器晶体管的最优输入阻抗，以便后续匹配；Step 2: Determine the input and output impedances of the control amplifier transistor and the optimal input impedance of the balance amplifier transistor according to the set operating frequency and bias size for subsequent matching; 步骤三：根据晶体管饱和阻抗，设计控制放大器输入匹配电路、控制放大器输出匹配电路、平衡放大器输入匹配电路；Step 3: Design a control amplifier input matching circuit, a control amplifier output matching circuit, and a balanced amplifier input matching circuit according to the transistor saturation impedance; 步骤四：设计输入3-dB正交耦合器、输出3-dB正交耦合器，其中输入3-dB正交耦合器、输出3-dB正交耦合器的直通端和耦合端相位均满足相差90度，两路信号幅度大小相等；输入3-dB正交耦合器隔离端口接50欧姆电阻，输出3-dB正交耦合器输入端口接50欧姆负载；Step 4: Design the input 3-dB quadrature coupler and the output 3-dB quadrature coupler, in which the phases of the straight-through end and the coupling end of the input 3-dB quadrature coupler and the output 3-dB quadrature coupler meet the phase difference 90 degrees, the amplitudes of the two channels are equal; the isolation port of the input 3-dB quadrature coupler is connected to a 50-ohm resistor, and the input port of the output 3-dB quadrature coupler is connected to a 50-ohm load; 步骤五：设计功分器，三端口阻抗均为50欧姆，功分器将单输入信号不等分为两路信号，具体功分比例根据调试结果来确定，两路信号分别送给控制放大器输入端口和连接输入3-dB正交耦合器的相位补偿网络输入端口；Step 5: Design the power divider. The impedance of the three ports is 50 ohms. The power divider divides the single input signal into two signals unequally. The specific power division ratio is determined according to the debugging results. The two signals are respectively sent to the control amplifier input. port and the input port of the phase compensation network connected to the input 3-dB quadrature coupler; 步骤六：设计自适应偏压控制电路，正向二极管对流入晶体管栅极的输入功率进行整流，通过串联电阻R6转换为栅极电压的变化；Step 6: Design an adaptive bias control circuit, the forward diode rectifies the input power flowing into the gate of the transistor, and converts it into the change of the gate voltage through the series resistor R6; 步骤七：将调试好的控制放大器输入匹配电路、控制放大器输出匹配电路、平衡放大器输入匹配电路、RC稳定电路、自适应偏压控制电路、晶体管P1和P2、输入3-dB正交耦合器、输出3-dB正交耦合器和功分器组合并调试，进而通过改变阻抗的大小来拟合负载牵引的最优阻抗轨迹；具体是：Step 7: Input the debugged control amplifier input matching circuit, control amplifier output matching circuit, balanced amplifier input matching circuit, RC stabilization circuit, adaptive bias control circuit, transistors P1 and P2, input 3-dB quadrature coupler, The output 3-dB quadrature coupler and power divider are combined and debugged, and then the optimal impedance trajectory of load pull is fitted by changing the size of the impedance; specifically: 1)晶体管P2的饱和负载阻抗1) Saturation load impedance of transistor P2 单输入情况下，为了提高在低功率区的阻抗，应保持Pcontrol/Pbalance大于阈值a，其中Pcontrol表示控制放大器输出功率大小，Pbalance表示平衡子放大器输出功率大小，要求控制放大器提早饱和，平衡子放大器晚开启；因此首先设置控制放大器偏置在AB类，两路平衡子放大器偏置在C类；In the case of a single input, in order to improve the impedance in the low power region, P control /P balance should be kept greater than the threshold a, where P control represents the output power of the control amplifier, and P balance represents the output power of the balanced sub-amplifier, which requires the control amplifier to saturate early. , the balance sub-amplifier is turned on late; therefore, first set the control amplifier bias in class AB, and the two-way balance sub-amplifier bias in class C; 假设放大器电流为理想的线性模型，根据驱动水平对电流进行规范化：Assuming an ideal linear model for the amplifier current, normalize the current to the drive level:
Figure FDA0003388847350000041
Figure FDA0003388847350000041
Figure FDA0003388847350000042
Figure FDA0003388847350000042
 为了简化描述设置比率β＝Ib,max/Ic,max，Ic,max表示控制放大器输出电流的最大值，Ib,max表示平衡子放大器输出电流的最大值，k1表示P2打开时的驱动级别，k2表示P1饱和时的驱动级别；In order to simplify the description, set the ratio β=I b,max /I c,max , I c,max represents the maximum value of the output current of the control amplifier, I b,max represents the maximum value of the output current of the balanced sub-amplifier, and k 1 represents when P2 is turned on The driving level of , k 2 represents the driving level when P1 is saturated; 控制放大器和两路平衡子放大器都饱和时，整个电路的输出功率达到最大值，则对应的饱和负载阻抗Zb,sat表示为：When both the control amplifier and the two balanced sub-amplifiers are saturated, the output power of the whole circuit reaches the maximum value, and the corresponding saturated load impedance Z b,sat is expressed as:
Figure FDA0003388847350000043
Figure FDA0003388847350000043
 其中θ表示平衡放大器负载阻抗反射系数的相位，Z0表示输出3-dB正交耦合器的特征阻抗，j表示复数；where θ represents the phase of the reflection coefficient of the load impedance of the balanced amplifier, Z 0 represents the characteristic impedance of the output 3-dB quadrature coupler, and j represents the complex number; 总输出功率Pall是控制放大器和两路平衡子放大器的输出功率之和：The total output power P all is the sum of the output power of the control amplifier and the two balanced sub-amps:
Figure FDA0003388847350000044
Figure FDA0003388847350000044
 其中Ic表示控制放大器输出电流；Ib表示平衡子放大器输出电流，Re(Zb)表示负载阻抗Zb的实部；Wherein I c represents the output current of the control amplifier; I b represents the output current of the balanced sub-amplifier, Re(Z b ) represents the real part of the load impedance Z b ; 化简上式(6)得到总饱和输出功率Psat：Simplify the above formula (6) to obtain the total saturated output power P sat :
Figure FDA0003388847350000045
Figure FDA0003388847350000045
 根据晶体管的datasheet得到晶体管P1、P2的总饱和输出功率Psat，然后与负载牵引的结果进行反复比较寻求β和φ的最优值，进而得到饱和负载阻抗Zb,sat；Obtain the total saturated output power P sat of the transistors P1 and P2 according to the datasheet of the transistors, and then repeatedly compare with the result of the load pull to find the optimal values of β and φ, and then obtain the saturated load impedance Z b,sat ; 2)晶体管P2的回退阻抗2) Backoff impedance of transistor P2 定义在整个调制过程中β不变，则φ的值认为不发生变化，从而进一步分析P2的低功率阶段；在驱动水平为k2的时刻，晶体管P1刚刚饱和，控制放大器输出电流达到最大值Ic,max，平衡子放大器输出电流
Figure FDA0003388847350000051
则被调制的回退点负载阻抗Zb,back为：It is defined that β does not change during the whole modulation process, and the value of φ is considered to be unchanged, so as to further analyze the low power stage of P2; at the moment when the driving level is k 2 , the transistor P1 is just saturated, and the output current of the control amplifier reaches the maximum value I c,max , balanced sub-amp output current
Figure FDA0003388847350000051
Then the modulated back-off point load impedance Z b,back is:
Figure FDA0003388847350000052
Figure FDA0003388847350000052
 进一步得到回退状态下控制放大器和平衡放大器的总输出功率为：Further, the total output power of the control amplifier and the balance amplifier in the fallback state is obtained as:
Figure FDA0003388847350000053
Figure FDA0003388847350000053
 回退范围OBO通过比较Psat和Pback求得：The fallback range OBO is obtained by comparing P sat and P back :
Figure FDA0003388847350000054
Figure FDA0003388847350000054
 在给定OBO的情况下，已知Pback的前提下进而求解
Figure FDA0003388847350000055
并确定Zb,back的实虚部；In the case of a given OBO, the solution is given on the premise of known P back
Figure FDA0003388847350000055
And determine the real and imaginary parts of Z b,back ; 回退点负载阻抗Zb,back的实虚部：The real and imaginary parts of the load impedance Z b,back at the back-off point:
Figure FDA0003388847350000056
Figure FDA0003388847350000056
Figure FDA0003388847350000057
Figure FDA0003388847350000057
 3)通过自适应偏压控制电路改变栅极电压，实现对控制放大器和平衡放大器输出电流大小和相对相位的控制，进而保证Zb,sat和Zb,back的匹配；3) The gate voltage is changed by the adaptive bias control circuit to realize the control of the output current size and relative phase of the control amplifier and the balanced amplifier, thereby ensuring the matching of Z b,sat and Z b,back ; 步骤八：根据不同频率下控制放大器和平衡放大器两路电流的相对相位差进行相位补偿网络的设计，然后将相位补偿网络与上述网络组合后进行完整电路的调试。Step 8: Design the phase compensation network according to the relative phase difference between the two currents of the control amplifier and the balance amplifier at different frequencies, and then combine the phase compensation network with the above network to debug the complete circuit.
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