CN114171591B - Vertical power metal oxide semiconductor field effect transistor and preparation method thereof - Google Patents
Vertical power metal oxide semiconductor field effect transistor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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Abstract
本发明涉及一种垂直功率金属氧化物半导体场效应晶体管及其制备方法。该垂直功率金属氧化物半导体场效应晶体管包括至少一个第一单原胞和至少一个第二单原胞组成的单胞阵列，第一单原胞以及第二单原胞均包括：重掺杂衬底，外延层，第一阱区，源极区，栅氧化层，多晶硅层，绝缘层，源极金属层，以及漏极金属层，第二单原胞中还设置有第二导电类型的第二阱区，第二阱区设于外延层内且与栅氧化层贴合。该垂直功率金属氧化物半导体场效应晶体管能够在不影响开关速度等性能的条件下，降低电磁辐射以及电磁传导低。
The present invention relates to a vertical power metal oxide semiconductor field effect transistor and a preparation method thereof. The vertical power metal oxide semiconductor field effect transistor comprises a unit cell array composed of at least one first unit cell and at least one second unit cell, wherein the first unit cell and the second unit cell both comprise: a heavily doped substrate, an epitaxial layer, a first well region, a source region, a gate oxide layer, a polysilicon layer, an insulating layer, a source metal layer, and a drain metal layer, and the second unit cell is also provided with a second well region of a second conductivity type, the second well region being arranged in the epitaxial layer and being attached to the gate oxide layer. The vertical power metal oxide semiconductor field effect transistor can reduce electromagnetic radiation and electromagnetic conduction without affecting the performance such as switching speed.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a vertical power metal oxide semiconductor field effect transistor and a preparation method thereof.
Background
Vertical power metal oxide semiconductor field effect transistors (VDMOSFETs) are a type of field effect transistor that can be widely used in analog and digital circuits. In order to reduce the conduction loss and the switching loss of the vertical power mosfet and improve the switching speed, the size of the vertical power mosfet is generally reduced, however, when the performance is improved, the source-drain oscillation and the gate-source oscillation of the vertical power mosfet are caused, so that the electromagnetic conduction and the electromagnetic radiation of the vertical power mosfet exceed the standard, and the contradiction relation between the high switching speed and the low electromagnetic conduction and the electromagnetic radiation of the vertical power mosfet is difficult to solve.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a vertical power mosfet that can reduce electromagnetic radiation and lower electromagnetic conduction without affecting the switching speed, and a method of manufacturing the same.
The invention provides a vertical power metal oxide semiconductor field effect transistor, which comprises a single cell array formed by at least one first single cell and at least one second single cell, wherein the first single cell and the second single cell comprise:
a heavily doped substrate having a first conductivity type;
the epitaxial layer is covered on the surface of the heavily doped substrate and has a first conductivity type;
A first well region disposed within the epitaxial layer and having a second conductivity type different from the first conductivity type;
a source region disposed within the first well region and having a first conductivity type;
The gate oxide layer is covered on the surface of the epitaxial layer far away from the heavily doped substrate and extends from one source region to the adjacent other source region;
the polycrystalline silicon layer is covered on the surface of the gate oxide layer, which is far away from the epitaxial layer;
the insulating layer is covered on the surface of the polycrystalline silicon layer and part of the source electrode region far away from the epitaxial layer, and a contact hole penetrating through the epitaxial layer is formed in the insulating layer;
A source metal layer covering the first well region, the insulating layer, and the surface of the source region far away from the epitaxial layer, the source metal layer being connected to the epitaxial layer via a contact hole, and
The drain electrode metal layer is covered on the surface of the heavily doped substrate far away from the epitaxial layer;
and a second well region of a second conductivity type is further arranged in the second single unit cell, and the second well region is arranged in the epitaxial layer and is attached to the gate oxide layer.
In an embodiment, the well depth of the second well region is equal to the well depth of the first well region.
In an embodiment, a central axis of the second well region coincides with a central axis of the gate oxide layer.
In one embodiment, the width of the first single cell is X 1, and the width of the second single cell is X 2,X1:X2, which is 1:1.95-1:2.05.
In one embodiment, the X 1 is 4 μm to 20 μm.
In one embodiment, more than two adjacent second single primordia are included;
and/or, the kit comprises more than two second single cells which are arranged at intervals.
In an embodiment, in the plurality of second single cells arranged at intervals, the same number of the first single cells is arranged between every two adjacent second single cells;
and/or, different numbers of the first single cells are arranged between every two adjacent second single cells.
In an embodiment, the same number of the first single cells is disposed between every two adjacent second single cells, and the number of the first single cells is 1 or 2.
A method for manufacturing a vertical power mosfet as described above, comprising the steps of:
Providing a heavily doped substrate;
forming an epitaxial layer on the surface of the heavily doped substrate;
forming a second well region having a second conductivity type within the epitaxial layer;
Sequentially forming a gate oxide layer and a polysilicon layer on the surface of the epitaxial layer, which is far away from the heavily doped substrate, and etching the gate oxide layer and the polysilicon layer to form a gate region pattern of a first single unit cell and a second single unit cell in the unit cell array, wherein the gate oxide layer of the second single unit cell is attached to the second well region;
forming a first well region on the surface of the epitaxial layer which is not covered by the grid region pattern;
forming a source region in the first well region;
forming an insulating layer on the surface of the polycrystalline silicon layer and part of the source electrode region far away from the epitaxial layer, and arranging a contact hole penetrating through the epitaxial layer on the insulating layer;
Forming a source metal layer in the contact hole and on the surfaces of the first well region, the insulating layer and the source region far from the epitaxial layer, and
And forming a drain metal layer on the surface of the heavily doped substrate far away from the epitaxial layer.
Another method for manufacturing the vertical power mosfet includes the following steps:
Providing a heavily doped substrate;
forming an epitaxial layer on the surface of the heavily doped substrate;
Forming a second well region and a first well region with a second conductivity type in the epitaxial layer;
forming a source region in the first well region;
Sequentially forming a gate oxide layer and a polysilicon layer on the surface of the epitaxial layer, which is far away from the heavily doped substrate, and etching the gate oxide layer and the polysilicon layer to form a gate region pattern of a first single unit cell and a second single unit cell in the unit cell array, wherein the gate oxide layer of the second single unit cell is attached to the second well region;
forming an insulating layer on the surface of the polycrystalline silicon layer and part of the source electrode region far away from the epitaxial layer, and arranging a contact hole penetrating through the epitaxial layer on the insulating layer;
Forming a source metal layer in the contact hole and on the surfaces of the first well region, the insulating layer and the source region far from the epitaxial layer, and
And forming a drain metal layer on the surface of the heavily doped substrate far away from the epitaxial layer.
In the vertical power metal oxide semiconductor field effect transistor, the second single cell comprises the second well region, and the second well region does not influence the size of the vertical power metal oxide semiconductor field effect transistor, so that the switching speed and other performances of the vertical power metal oxide semiconductor field effect transistor are not influenced in the switching process of the vertical power metal oxide semiconductor field effect transistor, and meanwhile, parasitic capacitance is formed in the second well region, and the parasitic capacitance is matched with the gate-drain capacitance (Cgd) and the gate-source capacitance (Cgs) in the single cell, so that source-drain oscillation and gate-source oscillation are reduced, and electromagnetic conduction and electromagnetic radiation are further reduced.
Drawings
Fig. 1 is a schematic diagram of a vertical power mosfet according to an embodiment of the present invention;
Fig. 2-9 are schematic views illustrating steps of a method for fabricating a vertical power mosfet according to the present invention.
In the figure, 10 parts of a first single cell, 101 parts of a heavily doped substrate, 102 parts of an epitaxial layer, 103 parts of a first well region, 103a parts of a deep junction, 103b parts of a channel region, 104 parts of a source region, 105 parts of a gate oxide layer, 106 parts of a polysilicon layer, 107 parts of an insulating layer, 108 parts of a source electrode metal layer, 109 parts of a drain electrode metal layer, 20 parts of a second single cell, and 201 parts of a second well region.
Detailed Description
In order to facilitate understanding of the present invention, the vertical power mosfet and the method of manufacturing the same provided by the present invention will be more fully described with reference to the related examples. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the vertical power mosfet according to an embodiment of the present invention includes at least one single cell array of a first single cell 10 and at least one second single cell 20, where each of the first single cell 10 and the second single cell 20 includes a heavily doped substrate 101, an epitaxial layer 102, a first well region 103, a source region 104, a gate oxide 105, a polysilicon layer 106, an insulating layer 107, a source metal layer 108, and a drain metal layer 109.
Wherein the heavily doped substrate 101, the heavily doped substrate 101 having the first conductivity type, the heavily doped substrate 101 may be formed based on a silicon substrate, and the silicon substrate may be grown by a Czochralski method. For example, an N-type heavily doped silicon substrate may be obtained by heavily doping an N-type silicon substrate, a P-type heavily doped silicon substrate may be obtained by heavily doping a P-type silicon substrate, and the doping degree of the heavily doped substrate 101 may be determined as needed, for example, the resistivity of the heavily doped substrate 101 may be 0.5mΩ×cm to 5mΩ×cm.
The epitaxial layer 102, the epitaxial layer 102 covers the surface of the heavily doped substrate 101, and has a first conductivity type, for example, the N-type epitaxial layer 102 and the p-type epitaxial layer 102, the epitaxial layer 102 may cover the entire surface area of the heavily doped substrate 101, the thickness and the doping concentration of the epitaxial layer 102 may depend on the voltage withstanding requirement of the vertical power mosfet, and the thickness of the epitaxial layer 102 may range from 2 μm to 150 μm.
The first well region 103 is disposed in the epitaxial layer 102, and has a second conductivity type, which is different from the first conductivity type, specifically, the second conductivity type may be P-type or N-type, in which case the first conductivity type is N-type, the second conductivity type is P-type, and in which case the first conductivity type is P-type, the second conductivity type is N-type.
In this embodiment, the first well region 103 is composed of the deep junction 103a and the channel region 103b, and the well depth of the first well region 103 is equal to the sum of the depth of the deep junction 103a and the depth of the channel region 103 b.
A source region 104, the source region 104 is disposed in the first well region 103, and has a first conductivity type. The source region 104 may be provided within the channel region 103b, having a heavily doped first conductivity type.
The gate oxide layer 105, the gate oxide layer 105 is disposed on the surface of the epitaxial layer 102 far from the heavily doped substrate 101 and extends from one source region 104 to the adjacent other source region 104, and it can be understood that the gate oxide layer 105 is attached to the source region 104.
The polysilicon layer 106, the polysilicon layer 106 covers the surface of the gate oxide layer 105 away from the epitaxial layer 102, and the polysilicon layer 106 is gate polysilicon.
The insulating layer 107, where the insulating layer 107 covers the polysilicon layer 106 and a portion of the surface of the source region 104 away from the epitaxial layer 102, and contact holes penetrating through the epitaxial layer 102 are formed on the insulating layer 107, which can be understood to perform a connection function, specifically to connect the source metal layer 108 with the first well region 103, the source region 104, and the like.
The source metal layer 108, the source metal layer 108 is disposed on the surfaces of the first well region 103, the insulating layer 107 and the source region 104 away from the epitaxial layer 102, the source metal layer 108 is connected to the epitaxial layer 102, the first well region 103, the source region 104 and the insulating layer 107 through contact holes, and the source metal layer 108 serves to draw the source out and form a source metal electrode.
The drain metal layer 109 is covered on the surface of the heavily doped substrate 101 far away from the epitaxial layer 102, and the drain metal layer 109 is used for leading out the drain to form a drain electrode, so that the processes of wire bonding, welding and the like are facilitated.
In particular, a second well region 201 having a second conductivity type is further disposed in the second single cell 20, the second well region 201 is disposed in the epitaxial layer 102 and is bonded to the gate oxide layer 105, and the second well region 201 forms a parasitic capacitance, and the parasitic capacitance is matched with the gate-drain capacitance and the gate-source capacitance in the single cell, so as to avoid gate-drain oscillation and gate-source oscillation, thereby reducing electromagnetic conduction and electromagnetic radiation.
It will be appreciated that the well depth of the second well region 201 is less than or equal to the thickness of the epitaxial layer 102, and in one embodiment, the thickness of the epitaxial layer 102 is 2 μm to 150 μm.
In the second single unit cell 20, since each of the first single unit cell 10 and the second single unit cell 20 needs to withstand a withstand voltage, in order to maintain the uniformity of the overall withstand voltage and simplify the manufacturing process, in one embodiment, the well depth of the second well region 201 is equal to the well depth of the first well region 103.
In one embodiment, the depth of the first well region 103 is 2 μm to 150 μm, and correspondingly, the depth of the second well region 201 is 2 μm to 150 μm.
In order to better optimize the capacitance and improve the oscillation characteristics, in one embodiment, the central axis of the second well region 201 coincides with the central axis of the gate oxide layer 105.
The shape of the second well region 201 is not further limited in the present invention, and in an embodiment, the shape of the second well region 201 is a column or a stripe.
In the vertical power mosfet of the present invention, the width of the first single cell 10 is X 1, the width of the second single cell 20 is X 2,X1:X2 to be 1:1.95-1:2.05, and in order to make the withstand voltage of each first single cell 10 and the withstand voltage of the second single cell 20 consistent, preferably, X 1:X2 is 1:2, and in one embodiment, X 1 is 4 μm-20 μm.
In one embodiment, the vertical power mosfet of the present invention includes two or more second single cells 20 disposed adjacent to each other and/or two or more second single cells 20 disposed at intervals.
It will be appreciated that when the number of the second single cells 20 is 2, the first single cells 10 may not be disposed between the two second single cells 20, or two or more first single cells 10 may be disposed, and when the number of the second single cells 20 is 3, 4, 5, or more, the distribution of the second single cells 20 in the vertical power mosfet has three cases, namely, a first case, in which all the second single cells 20 in the vertical power mosfet are disposed adjacently, a second case, in which part of the second single cells 20 in the vertical power mosfet are disposed adjacently, and part of the second single cells 20 are disposed at intervals, and a third case, in which all the second single cells 20 in the vertical power mosfet are disposed at intervals.
Further, when the number of the second single cells 20 is 3, 4, 5, or the like, the same number of the first single cells 10 is disposed between every two adjacent second single cells 20, and/or different numbers of the first single cells 10 are disposed between every two adjacent second single cells 20 in the plurality of second single cells 20 disposed at intervals.
At this time, there are various cases of distribution of the second single unit cell 20 in the vertical power mosfet, for example:
In the first case, a part of the second single cells 20 in the vertical power mosfet are adjacently arranged, and a part of the second single cells 20 are arranged at intervals, and when the two adjacent second single cells 20 are arranged at intervals, the same number of first single cells 10 are arranged between every two adjacent second single cells 20;
In the second case, part of the second single cells 20 in the vertical power mosfet are adjacently arranged, and part of the second single cells 20 are arranged at intervals, and when the second single cells are arranged at intervals, different numbers of first single cells 10 are arranged between every two adjacent second single cells 20;
In the third case, part of the second single cells 20 are adjacently arranged in the vertical power mosfet, and part of the second single cells 20 are arranged at intervals, and when the second single cells 20 are arranged at intervals, the number of the first single cells 10 arranged between every two adjacent second single cells 20 may be the same or different;
In the fourth case, all the second single cells 20 in the vertical power mosfet are arranged at intervals, and the same number of first single cells 10 are arranged between every two adjacent second single cells 20;
In the fifth case, all the second single cells 20 in the vertical power mosfet are arranged at intervals, and a different number of first single cells 10 are arranged between every two adjacent second single cells 20;
In the sixth case, all the second single cells 20 in the vertical power mosfet are arranged at intervals, and the number of the first single cells 10 arranged between every two adjacent second single cells 20 may be the same or different.
It will be appreciated that in the third and sixth cases, the number of the first single cells 10 disposed between each two adjacent second single cells 20 may be regular or irregular, for example, when 5 second single cells 20 are included in the vertical power mosfet, 2,3 first single cells 10 may be disposed between each two adjacent second single cells 20 in sequence, 2,3, 2 first single cells 10 may be disposed in sequence, and 2,3, 4, 2 first single cells 10 may be disposed in sequence.
When the second single unit cells 20 are arranged at intervals, compared with the case that different numbers of the first single unit cells 10 are arranged between every two adjacent second single unit cells 20, when the same numbers of the first single unit cells 20 are arranged between every two adjacent second single unit cells, the on-state resistance of the vertical power metal oxide semiconductor field effect transistor can be ensured to be smaller, and the flow resistance is higher. Therefore, in order to ensure that the vertical power mosfet can improve the oscillation performance of the device under the premise of smaller on-resistance, it is preferable that the same number of first single cells 10 are arranged between every two adjacent second single cells 20, and the number of the first single cells 10 is more than 1, preferably 1 or 2, and further preferable that the second single cells 20 are arranged at intervals in the vertical power mosfet, and the same number of first single cells 10 are arranged between every two adjacent second single cells 20, and the number of the first single cells 10 is more than 1, preferably 1 or 2.
In the vertical power mosfet of the present invention, since the second single cell 20 does not affect the size of the vertical power mosfet, the switching speed and other performances of the vertical power mosfet are not affected during the switching process of the vertical power mosfet, and meanwhile, the second well region 201, the gate oxide layer 105 and the epitaxial layer 102 form parasitic capacitance, which cooperates with the gate-drain capacitance and the gate-source capacitance in the single cell, thereby avoiding gate-drain oscillation and gate-source oscillation, and further reducing electromagnetic conduction and electromagnetic radiation.
The invention also provides a preparation method of the vertical power metal oxide semiconductor field effect transistor, which comprises the following steps of the schematic diagrams shown in the figures 2-5 and 8-9:
S1, providing a heavily doped substrate 101;
S2, forming an epitaxial layer 102 on the surface of the heavily doped substrate 101;
s3, forming a second well region 201 with a second conductivity type in the epitaxial layer 102;
S4, sequentially forming a gate oxide layer 105 and a polysilicon layer 106 on the surface of the epitaxial layer 102 far away from the heavily doped substrate 101, etching the gate oxide layer 105 and the polysilicon layer 106 to form a gate region pattern of a first single cell 10 and a second single cell 20 in the unit cell array, and attaching the gate oxide layer 105 of the second single cell 20 to the second well region 201;
S5, forming a first well region 103 on the surface of the epitaxial layer 102 which is not covered by the grid region pattern;
s6, forming a source region 104 in the first well region 103;
s7, forming an insulating layer 107 on the surface of the polycrystalline silicon layer 106 and part of the source region 104, which is far away from the epitaxial layer 102, and arranging a contact hole penetrating through the epitaxial layer 102 on the insulating layer 107;
s8, forming a source metal layer 108 in the contact hole and on the surface of the first well region 103, the insulating layer 107 and the source region 104 away from the epitaxial layer 102, and
S9, a drain metal layer 109 is formed on the surface of the heavily doped substrate 101 away from the epitaxial layer 102.
In step S1, the heavily doped substrate 101 may be formed based on a silicon substrate, and in one embodiment, providing the heavily doped substrate 101 includes N-type heavily doping the silicon substrate to obtain an N-type heavily doped substrate 101, or P-type heavily doping the silicon substrate to obtain a P-type heavily doped substrate 101.
In step S2, the epitaxial layer 102 may be formed by epitaxial growth such as chemical vapor deposition, and the resistivity of the epitaxial layer 102 may be controlled by controlling the doping dose during epitaxial growth.
Step S3 specifically includes the steps of forming a trench in the surface of the epitaxial layer 102 remote from the heavily doped substrate 101, and forming a second well region 201 having the second conductivity type by epitaxially growing and doping impurities of the second conductivity type to fill the trench.
In one embodiment, the step of forming a trench in the surface of the epitaxial layer 102 away from the heavily doped substrate 101 includes forming a barrier layer on the surface of the epitaxial layer 102 away from the heavily doped substrate 101, disposing a layer of photoresist on the barrier layer, and forming the trench by photolithography and etching.
It will be appreciated that when the second conductivity type is P-type, in one embodiment, the impurity comprises at least one of phosphane (PH 3) or phosphorus trichloride (PCl 3), and when the second conductivity type is N-type, the impurity comprises at least one of diborane (B 2H6) or boron trichloride (BCl 3).
It should be noted that the doping concentration of the impurity of the second conductivity type depends on the withstand voltage and the magnitude of the turn-on voltage of the vertical power mosfet.
In step S4, the material of the gate oxide layer 105 includes silicon dioxide, and the gate oxide layer 105 may be formed by thermal oxidation.
In step S5, the step of forming the first well region 103 includes implanting impurities of the second conductivity type into the epitaxial layer 102 not covered by the gate region pattern, and forming the first well region 103 composed of the deep junction 103a and the channel region 103b by an annealing process.
The step S6 specifically includes the steps of defining the shape of the source region 104 through a mask process, then implanting impurities of the first conductivity type, and forming the source region 104 through an annealing process.
In step S7, the material of the insulating layer 107 includes at least one of silicon dioxide or silicon nitride, and the insulating layer 107 is formed by chemical vapor deposition or the like.
One or more contact holes may be formed in the insulating layer 107, and in implementation, an oxide layer is deposited on a surface of the insulating layer 107 remote from the polysilicon layer 106, and then the contact holes are etched by photolithography based on a defined contact hole pattern, and the remaining oxide layer is used as the insulating layer 107.
In step S8, the source metal layer 108 may be formed by depositing a metal, and the source metal layer 108 may be formed by depositing a metal, which in one embodiment includes at least one of aluminum, titanium nitride, or tungsten.
In step S9, the drain metal layer 109 may be formed by deposition or the like, and in one embodiment, the metal includes at least one of aluminum or copper.
The present invention also provides a second method for manufacturing the vertical power mosfet, which includes the following steps, wherein the schematic diagrams of the steps are shown in fig. 2-3 and fig. 6-9, and it can be understood that, compared with the first method for manufacturing the vertical power mosfet, the method for manufacturing the vertical power mosfet is different in that the first well region 103 and the source region 104 are formed while the second well region 201 is formed, the gate oxide layer 105 and the polysilicon layer 106 are formed, or the first well region 103 is formed while the second well region 201 is formed, the gate oxide layer 105 and the polysilicon layer 106 are formed, and finally the source region 104 is formed in the first well region 103.
The present invention will be described in further detail with reference to specific examples and comparative examples. It is understood that the instruments and materials used in the following examples are more specific and in other embodiments may not be so limited.
Example 1
Embodiment 1 provides a vertical power mosfet comprising a stripe-shaped parallel arranged cell array of 1 first single cell 10 and 2 second single cells 20, each of the first single cells 10 and the second single cells 20 comprising:
an n+ heavily doped substrate 101 having a thickness of 725 μm;
An N-type epitaxial layer 102 with the thickness of 725 mu m, wherein the N-type epitaxial layer 102 is covered on the surface of the N+ heavily doped substrate 101;
the P-type first well region 103 with the well depth of 45 μm, wherein the P-type first well region 103 is arranged in the N-type epitaxial layer 102 and consists of a p+ type deep junction 103a with the depth of 45 μm and a P-type channel region 103b with the depth of 1.5 μm;
an n+ -type source region 104 having a thickness of 0.6 μm, the n+ -type source region 104 being provided in the P-type channel region 103 b;
The gate oxide layer 105, the gate oxide layer 105 is covered on the surface of the N-type epitaxial layer 102 far away from the n+ type heavily doped substrate 101, and extends from one n+ type source region 104 to another adjacent n+ type source region 104;
the polysilicon layer 106, the polysilicon layer 106 covers the surface of the gate oxide layer 105 far away from the N-type epitaxial layer 102;
the insulating layer 107, the insulating layer 107 covers the polysilicon layer 106 and a part of the surface of the n+ type source region 104, which is far away from the N-type epitaxial layer 102, and a contact hole penetrating through the N-type epitaxial layer 102 is formed in the insulating layer 107;
a source metal layer 108, the source metal layer 108 covering the P+ type first well region 103, the insulating layer 107 and the surface of the N+ type source region 104 remote from the N-type epitaxial layer 102, the source metal layer 108 being connected to the N-type epitaxial layer 102 via a contact hole, and
The drain metal layer 109 is disposed on a surface of the heavily doped substrate 101 away from the epitaxial layer 102.
The second single cell 20 is further provided with a p+ type second well region 201 with a well depth of 45 μm, the p+ type second well region 201 is disposed in the N-type epitaxial layer 102 and is attached to the gate oxide layer 105, and a central axis of the p+ type second well region 201 is coincident with a central axis of the gate oxide layer 105.
1 P+ type first well region 103 is disposed between the p+ type second well regions 201.
Example 2
The vertical power mosfet provided in embodiment 2 is different from the mosfet provided in embodiment 1 in that the well depth of the first well region 103 is 43 μm and the well depth of the second well region 201 is 40 μm.
Example 3
The vertical power mosfet in embodiment 3 is different from that in embodiment 1 in that the second well region 201 is spaced from the central axis of the gate oxide layer 105 by 0.5 μm.
Example 4
The vertical power mosfet provided in embodiment 4 is different from the vertical power mosfet provided in embodiment 1 in that 1 and 2 first single cells 10 are sequentially arranged between the second single cells 20.
Example 5
The vertical power mosfet provided in embodiment 5 is different from that in embodiment 1 in that the first single cells 10 are not disposed between the second single cells 20 and 1 first single cell 10 is disposed.
Example 6
The vertical power mosfet of example 6 is different from example 1 in that the width of the first well region 103 is 4 μm and the width of the second well region 201 is 5 μm.
Comparative example 1
The vertical power mosfet provided in comparative example 1 is referred to example 1, except that all the second single cells 20 are replaced with the first single cells 10.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
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| SG48388A1 (en) * | 1990-02-01 | 1998-04-17 | Fred L Quigg | Mosfet structure having reduced gate capacitance and method of forming same |
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