CN114171494B - Diode and its semiconductor structure - Google Patents
Diode and its semiconductor structure Download PDFInfo
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- CN114171494B CN114171494B CN202010950252.6A CN202010950252A CN114171494B CN 114171494 B CN114171494 B CN 114171494B CN 202010950252 A CN202010950252 A CN 202010950252A CN 114171494 B CN114171494 B CN 114171494B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000004020 conductor Substances 0.000 claims abstract description 264
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000002019 doping agent Substances 0.000 claims description 10
- 230000007423 decrease Effects 0.000 claims description 4
- 239000002184 metal Substances 0.000 description 29
- 238000010586 diagram Methods 0.000 description 2
- 208000032365 Electromagnetic interference Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
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- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present disclosure relates to a diode and a semiconductor structure thereof, wherein the diode is implemented in a semiconductor structure and comprises a substrate, a first conductor, a second conductor, a third conductor and a fourth conductor. The substrate comprises a first doped region and a second doped region, wherein the first doped region is used as a first electrode of the diode, and the second doped region is used as a second electrode of the diode. The first conductor is located on a first conductor layer of the semiconductor structure and is connected with the first doped region. The second conductor is located on a second conductor layer of the semiconductor structure and is connected with the first conductor. The third conductor is located on the first conductor layer of the semiconductor structure and connected with the second doped region. The fourth conductor is located on the second conductor layer of the semiconductor structure and is connected with the third conductor. In a side view of the semiconductor structure, an overlapping area of the first conductor and the third conductor is larger than an overlapping area of the second conductor and the fourth conductor.
Description
Technical Field
The present invention relates to a diode, and more particularly, to a diode with low electromagnetic interference (Electro MAGNETIC INTERFERENCE, EMI) and a semiconductor structure thereof.
Background
Fig. 1 is a functional block diagram of a conventional chip. The chip 100 includes an internal circuit 110, an internal circuit 120, a diode 130, a diode 140, and an input/output pad 150. The internal circuits 110 and 120 are responsible for the functions of the chip 100, and the internal circuits 120 receive signals or output signals through the input/output pads 150. Diode 130 is connected in series between voltage source VDD and input/output pad 150, and diode 140 is connected in series between input/output pad 150 and ground. Diode 130 and diode 140 may prevent electrostatic discharge (electrostatic discharge, ESD) from damaging internal circuit 120.
As integrated circuits become more powerful and operate faster, the problem of electromagnetic interference on the chip 100 becomes more serious. In general, the more effective the source of the signal, the lower the cost of addressing the electromagnetic interference. Therefore, designing a diode with low electromagnetic interference is an important issue in the art.
Disclosure of Invention
In view of the shortcomings of the prior art, an object of the present invention is to provide a diode and a semiconductor structure thereof.
The invention discloses a diode which is applied to a semiconductor structure and comprises a substrate, a first conductor structure and a second conductor structure. The substrate comprises a first doped region and a second doped region, wherein the first doped region is used as a first electrode of the diode, the second doped region is used as a second electrode of the diode, and the dopant of the first doped region is different from the dopant of the second doped region. The first conductor structure is positioned above the first doped region and connected with the first doped region, and is provided with a plurality of first conductors, wherein the first conductors are distributed on a plurality of conductor layers of the semiconductor structure, and the first conductors are connected with each other through a plurality of guide holes. The second conductor structure is positioned above the second doped region and connected with the second doped region, and is provided with a plurality of second conductors, wherein the second conductors are distributed on the conductor layers of the semiconductor structure, and the second conductors are connected with each other through a plurality of guide holes. A side view of the first conductor structure presents a step shape.
The invention also discloses a diode applied to a semiconductor structure, which comprises a substrate, a first conductor, a second conductor, a third conductor and a fourth conductor. The substrate comprises a first doped region and a second doped region, wherein the first doped region is used as a first electrode of the diode, the second doped region is used as a second electrode of the diode, and the dopant of the first doped region is different from the dopant of the second doped region. The first conductor is located on a first conductor layer of the semiconductor structure and is connected with the first doped region. The second conductor is located on a second conductor layer of the semiconductor structure and is connected with the first conductor. The third conductor is located on the first conductor layer of the semiconductor structure and connected with the second doped region. The fourth conductor is located on the second conductor layer of the semiconductor structure and is connected with the third conductor. In a side view of the semiconductor structure, an overlapping area of the first conductor and the third conductor is larger than an overlapping area of the second conductor and the fourth conductor.
The diode and the semiconductor structure thereof have smaller current loop area, so that compared with the prior art, the diode and the semiconductor structure thereof generate smaller electromagnetic interference.
The features, operations and effects of the present invention will be described in detail with reference to the drawings.
Drawings
FIG. 1 is a functional block diagram of a conventional chip;
FIG. 2 is a layout of a diode on a substrate according to an embodiment of the present invention;
FIG. 3 shows a semiconductor structure according to an embodiment of the present invention;
FIG. 4A is a first cross-sectional view of a diode according to an embodiment of the present invention;
FIG. 4B is a second cross-sectional view of a diode according to an embodiment of the present invention;
FIGS. 5A, 5B, 5C, 5D, and 5E are top views of a diode according to an embodiment of the present invention;
fig. 6 is a first cross-sectional view of a diode according to another embodiment of the present invention;
Fig. 7A, 7B, 7C, 7D, and 7E are top views of a diode according to another embodiment of the present invention;
FIG. 8 is a layout of a diode on a substrate according to another embodiment of the present invention;
fig. 9A, 9B, 9C, 9D and 9E are top views of a diode according to another embodiment of the present invention, and
Fig. 10 shows the shape of a conductor according to another embodiment of the invention.
Detailed Description
Technical terms used in the following description refer to terms commonly used in the art, and as used in the specification, some terms are described or defined, and the explanation of the some terms is based on the description or the definition of the specification.
Fig. 2 is a layout of a diode on a substrate according to an embodiment of the invention. The substrate 200 has a doped region 210 and a doped region 220, wherein the doped region 210 is an N-type doped region (i.e., the cathode of the diode) and the doped region 220 is a P-type doped region (i.e., the anode of the diode). In other words, the dopant of doped region 210 is different from the dopant of doped region 220. In some embodiments, doped region 210 and doped region 220 are substantially parallel to each other.
Fig. 3 shows a semiconductor structure in accordance with an embodiment of the present invention. The semiconductor structure 300 includes a substrate 200 and an oxide layer 310 stacked over the substrate 200 (z-direction). Inside the oxide layer 310, a plurality of conductor layers 320 (including at least a conductor layer 320-1, a conductor layer 320-2, and a conductor layer 320-3) are provided. Adjacent conductor layers are connected by a plurality of vias (via) 330, and conductor layer 320-3 is connected to substrate 200 by a plurality of contacts (contacts) 340. In some embodiments, these conductor layers 320 are, in order from bottom to top (i.e., from near substrate 200 to far from substrate 200), metal layer 1 (M1), metal layer 2 (M2), metal layer 3 (M3), ultra-thick metal (Ultra-THICK METAL, UTM) layers, and Re-routing layers (Re-distribution layer, RDL). Fig. 2 is a top view (x-y plane) of the substrate 200 itself of the semiconductor structure 300.
Fig. 4A is a first cross-sectional view (i.e., side view, y-z plane) of a diode according to an embodiment of the present invention (corresponding to cross-section A-A 'of fig. 2), and fig. 4B is a second cross-sectional view (corresponding to cross-section B-B' of fig. 2) of a diode according to an embodiment of the present invention.
As shown in fig. 4A, a conductor structure 410 is disposed above the doped region 210, and the doped region 210 and the conductor structure 410 are connected by a plurality of contacts, in other words, the conductor structure 410 is the cathode of the diode. Conductor structure 410 includes a plurality of conductors 415 (i.e., conductors 415-1, 415-2, 415-3, 415-4, &..the conductor 415-n, n being an integer greater than 1). Adjacent conductors 415 are connected by a plurality of vias, and thus, the plurality of conductors 415 of the conductor structure 410 are substantially equipotential. From bottom to top, conductor 415-1 is located at metal layer M1 (having thickness h 1), conductor 415-2 is located at metal layer M2 (having thickness h 2), conductor 415-3 is located at metal layer M3 (having thickness h 3), conductor 415-4 is located at metal layer M4 (having thickness h 4),. In some embodiments, conductors 415-1 through 415-n are substantially equal length (L).
As shown in fig. 4B, a conductor structure 420 is disposed above the doped region 220, and the doped region 220 is connected to the conductor structure 420 through a plurality of contacts, in other words, the conductor structure 420 is an anode of the diode. Conductor structure 420 includes a plurality of conductors 425 (i.e., conductor 425-1, conductor 425-2, conductor 425-3, conductor 425-4, &... Adjacent conductors 425 are connected by a plurality of vias, and thus, the plurality of conductors 425 of the conductor structure 420 are substantially equipotential. From bottom to top, conductor 425-1 is at metal layer M1, conductor 425-2 is at metal layer M2, conductor 425-3 is at metal layer M3, conductor 425-4 is at metal layer M4. Conductor structure 420 exhibits a stepped shape in that conductor 425-1 is longer than conductor 425-2 by a length d1, conductor 425-2 is longer than conductor 425-3 by a length d2, conductor 425-3 is longer than conductor 425-4 by a length d3, and conductor 425-n is the shortest conductor in conductor structure 420, in other words, the conductors in conductor structure 420 are not as long. As shown in fig. 4B, the ends of the conductors 425 in the conductor structure 420 that are on the left side of the side view are substantially aligned, although the invention is not limited to whether the same ends of the conductors are substantially aligned. In some embodiments, conductors 425-1, 425-2, 425-3, 425-4, and the length of conductors 425-n are in an arithmetic series (i.e., d1=d2=d3).
As shown in fig. 2, 3, 4A and 4B, the diode of the present invention is a three-dimensional structure, and is applied to a semiconductor structure 300, and includes a doped region 210 and a doped region 220 on a substrate 200, a conductor structure 410 and a conductor structure 420.
Fig. 5A to 5E are top views of a diode according to an embodiment of the invention, which respectively show the relationship between each conductor layer and the doped region on the substrate. Fig. 5A to 5E correspond to the cross-sectional views of fig. 4A and 4B.
FIG. 5A shows the correspondence between the conductors 415-1 and 425-1 on the metal layer M1 and the doped regions 210 and 220. Conductor 415-1 completely covers doped region 210 and is substantially parallel to doped region 210. The conductor 425-1 completely covers the doped region 220 and is substantially parallel to the doped region 220. Conductor 415-1 is substantially parallel to conductor 425-1. The lengths of conductors 415-1 and 425-1 are both L.
FIG. 5B shows the correspondence between the conductors 415-2 and 425-2 on the metal layer M2 and the doped regions 210 and 220. Conductor 415-2 completely covers doped region 210 and is substantially parallel to doped region 210. Conductor 425-2 partially covers doped region 220 and is substantially parallel to doped region 220. Conductor 415-2 is substantially parallel to conductor 425-2. Conductor 415-2 has a length L and the difference in length between conductor 415-2 and conductor 425-2 is d1.
FIG. 5C shows the correspondence between conductors 415-3 and 425-3 on metal layer M3 and doped regions 210 and 220. Conductor 415-3 completely covers doped region 210 and is substantially parallel to doped region 210. Conductor 425-3 partially covers doped region 220 and is substantially parallel to doped region 220. Conductor 415-3 is substantially parallel to conductor 425-3. The length of conductor 415-3 is L and the difference in length between conductor 415-3 and conductor 425-3 is d1+d2.
Fig. 5D shows the correspondence of conductors 415-4 and 425-4 on metal layer M4 with doped regions 210 and 220. Conductor 415-4 completely covers doped region 210 and is substantially parallel to doped region 210. Conductor 425-4 partially covers doped region 220 and is substantially parallel to doped region 220. Conductor 415-4 is substantially parallel to conductor 425-4. The length of conductor 415-4 is L and the difference in length between conductor 415-4 and conductor 425-4 is d1+d2+d3.
FIG. 5E shows the correspondence between conductors 415-n and 425-n on metal layer Mn and doped regions 210 and 220. Conductors 415-n completely cover doped region 210 and are substantially parallel to doped region 210. The conductor 425-n partially covers the doped region 220 and is substantially parallel to the doped region 220. Conductors 415-n are substantially parallel to conductors 425-n. The length of conductor 415-n is L.
Please refer to fig. 4A and 4B and fig. 5A to 5E. Conductors 415-1 and 425-1 overlap each other substantially in the y-z plane (overlap area A1≡Lh 1), conductors 415-2 and 425-2 overlap partially in the y-z plane (overlap area A2≡L-d 1) withh 2), conductors 415-3 and 425-3 overlap partially in the y-z plane (overlap area A3≡L-d1-d 2) with h 3), conductors 415-4 and 425-4 overlap partially in the y-z plane (overlap area A4≡L-d1-d2-d 3) with h4, and conductors 415-n and 425-n overlap partially in the y-z plane (overlap area is the smallest of all conductor layers). If the thicknesses of all conductor layers are substantially the same (i.e., h1, h2, h3, h4, hn are substantially equal), A1> A2> A3> A4.
Because conductor structure 420 is stepped (otherwise referred to as receded (retrograde-type)), the overlap area of conductor structure 410 and conductor structure 420 in each conductor layer (in the y-z plane) is not the same. More specifically, the overlap area of conductor structure 410 and conductor structure 420 is greatest on metal layer M1, inferior on metal layer M2. Such a design may reduce the current loop area (current loop area) between the anode and cathode of the diode, thereby reducing electromagnetic interference.
Fig. 6 is a first cross-sectional view (corresponding to cross-section A-A' of fig. 2) of a diode according to another embodiment of the present invention. The difference between fig. 6 and fig. 4A is that in the embodiment of fig. 6, conductor structure 410 is stepped in that conductor 415-1 is longer than conductor 415-2 by a length d4, conductor 415-2 is longer than conductor 415-3 by a length d5, conductor 415-3 is longer than conductor 415-4 by a length d 6. As shown in fig. 6, the ends of the conductors 415 in the conductor structure 410 that are on the right side of the side view are substantially aligned, although the invention is not limited to whether the same ends of the conductors are substantially aligned. In some embodiments, conductors 415-1, 415-2, 415-3, 415-4, and the length of conductors 415-n are in an arithmetic series (i.e., d4=d5=d6).
Fig. 7A to 7E are top views of a diode according to another embodiment of the invention, which respectively show the relationship between each conductor layer and the doped region on the substrate. Fig. 7A to 7E correspond to the cross-sectional views of fig. 4B and 6.
FIG. 7A shows the correspondence between conductors 415-1 and 425-1 on metal layer M1 and doped regions 210 and 220. Conductor 415-1 completely covers doped region 210 and is substantially parallel to doped region 210. The conductor 425-1 completely covers the doped region 220 and is substantially parallel to the doped region 220. Conductor 415-1 is substantially parallel to conductor 425-1. The lengths of conductors 415-1 and 425-1 are both L.
FIG. 7B shows the correspondence between the conductors 415-2 and 425-2 on the metal layer M2 and the doped regions 210 and 220. Conductor 415-2 partially covers doped region 210 and is substantially parallel to doped region 210. Conductor 425-2 partially covers doped region 220 and is substantially parallel to doped region 220. Conductor 415-2 is substantially parallel to conductor 425-2. Conductor 415-2 has a length (L-d 4) and conductor 425-2 has a length (L-d 1).
FIG. 7C shows the correspondence between conductors 415-3 and 425-3 on metal layer M3 and doped regions 210 and 220. Conductor 415-3 partially covers doped region 210 and is substantially parallel to doped region 210. Conductor 425-3 partially covers doped region 220 and is substantially parallel to doped region 220. Conductor 415-3 is substantially parallel to conductor 425-3. Conductor 415-3 has a length (L-d 4-d 5) and conductor 425-3 has a length (L-d 1-d 2).
FIG. 7D shows the correspondence between conductors 415-4 and 425-4 on metal layer M4 and doped regions 210 and 220. Conductor 415-4 partially covers doped region 210 and is substantially parallel to doped region 210. Conductor 425-4 partially covers doped region 220 and is substantially parallel to doped region 220. Conductor 415-4 is substantially parallel to conductor 425-4. Conductor 415-4 has a length (L-d 4-d5-d 6) and conductor 425-4 has a length (L-d 1-d2-d 3).
FIG. 7E shows the correspondence of conductors 415-n and 425-n on metal layer Mn with doped regions 210 and 220. Conductor 415-n partially overlies doped region 210 and is substantially parallel to doped region 210. The conductor 425-n partially covers the doped region 220 and is substantially parallel to the doped region 220. Conductors 415-n are substantially parallel to conductors 425-n.
Please refer to fig. 4B, fig. 6 and fig. 7A to fig. 7E. Because conductor structure 410 and conductor structure 420 are both stepped, the overlap area of conductor structure 410 and conductor structure 420 in each conductor layer (in the y-z plane) is not the same. More specifically, the area of overlap of conductor structure 410 and conductor structure 420 is greatest on metal layer M1, inferior on metal layer M2, minimum on metal layer Mn (or not overlapping). The overall overlap area between the conductor structures 410 and 420 is smaller than in the previous embodiment (i.e., the embodiment corresponding to fig. 4A and 4B and fig. 5A-5E), and thus electromagnetic interference can be further reduced.
It should be noted that whether the doped region 210 is parallel to the doped region 220 and whether the two conductors of each conductor layer are parallel is not critical to the implementation of the present invention. The two components described above as being substantially parallel may also be designed to be non-parallel.
The diode of the present invention is not limited to the layout of fig. 2, and fig. 8 is a layout of a diode on a substrate according to another embodiment of the present invention. Doped region 210 surrounds doped region 220. Fig. 9A to 9E are top views of a diode according to another embodiment of the invention, which respectively show the relationship between each conductor layer and the doped region on the substrate. Fig. 9A to 9E correspond to the cross-sectional views of fig. 4B and 6. Those skilled in the art can understand the implementation details and variations of fig. 8 and fig. 9A to fig. 9E according to the above embodiments, and therefore, the details are not repeated. It is noted that in the embodiment of fig. 9A to 9E, the conductor 415 is E-shaped, the conductor 425 is U-shaped (as shown in fig. 10, the conductor 415-1 and the conductor 425-1 are taken as examples), the length of the finger structure (the portion located in the range R) of the E-shaped conductor 415 gradually decreases from fig. 9A to 9E, and the length of the finger structure (the portion located in the range R) of the U-shaped conductor 425 gradually decreases from fig. 9A to 9E.
It should be noted that the shapes, sizes, proportions, etc. of the components are merely illustrative, and are used by those skilled in the art to understand the present invention, and are not intended to limit the present invention.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art may make various changes to the technical features of the present invention according to the explicit or implicit disclosure of the present invention, and all such changes may be made within the scope of the patent protection sought herein, in other words, the scope of the patent protection of the present invention shall be defined by the claims of the present specification.
[ Symbolic description ]
100 Chip
110. 120 Internal circuitry
130. 140 Diode
150 Input/output pad
VDD voltage source
200 Substrate
210. 220 Doped regions
300 Semiconductor structure
310 Oxide layer
320. 320-1, 320-2, 320-3 Conductor layer
330 Guide hole
340 Contacts
410. 420 Conductor structure
415-1, 415-2, 415-3, 415-4, 415-N, 425-1, 425-2, 425-3, 425-4, 425-n: conductor
M1, M2, M3, M4, mn: metal layer
R is the range.
Claims (5)
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| CN202010950252.6A CN114171494B (en) | 2020-09-10 | 2020-09-10 | Diode and its semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010950252.6A CN114171494B (en) | 2020-09-10 | 2020-09-10 | Diode and its semiconductor structure |
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| Publication Number | Publication Date |
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| CN114171494A CN114171494A (en) | 2022-03-11 |
| CN114171494B true CN114171494B (en) | 2025-01-24 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972303A (en) * | 2013-01-25 | 2014-08-06 | 三星电子株式会社 | Diode, ESD protection circuit and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2006134939A (en) * | 2004-11-02 | 2006-05-25 | Nec Electronics Corp | Semiconductor device |
| US8178908B2 (en) * | 2008-05-07 | 2012-05-15 | International Business Machines Corporation | Electrical contact structure having multiple metal interconnect levels staggering one another |
| US9640483B2 (en) * | 2015-05-29 | 2017-05-02 | Stmicroelectronics, Inc. | Via, trench or contact structure in the metallization, premetallization dielectric or interlevel dielectric layers of an integrated circuit |
| CN110600465B (en) * | 2018-06-13 | 2022-02-08 | 世界先进积体电路股份有限公司 | Semiconductor structure |
| US11171131B2 (en) * | 2018-08-29 | 2021-11-09 | Stmicroelectronics International N.V. | Multi-fingered diode with reduced capacitance and method of making the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103972303A (en) * | 2013-01-25 | 2014-08-06 | 三星电子株式会社 | Diode, ESD protection circuit and method of manufacturing the same |
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