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CN114168503B - Interface IP core control method, interface IP core, device and medium - Google Patents

Interface IP core control method, interface IP core, device and medium Download PDF

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Publication number
CN114168503B
CN114168503B CN202111413564.4A CN202111413564A CN114168503B CN 114168503 B CN114168503 B CN 114168503B CN 202111413564 A CN202111413564 A CN 202111413564A CN 114168503 B CN114168503 B CN 114168503B
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data
state
read
write
fifo
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CN114168503A (en
Inventor
杨琳琳
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)

Abstract

本申请公开了一种接口IP核控制方法、接口IP核、装置及介质，涉及数据交换领域，接口IP核通过接收并缓存由主设备发送的第一数据信息后，将接收到的第一数据信息转换为AHB协议标准格式，将进行过格式转换的第一数据信息发送至从设备。本申请提供的接口IP核控制方法，输出的数据信息为AHB协议标准格式，不需要对每个接口IP核单独进行配置AHB协议转换。

The present application discloses an interface IP core control method, an interface IP core, a device and a medium, and relates to the field of data exchange. After receiving and caching first data information sent by a master device, the interface IP core converts the received first data information into an AHB protocol standard format, and sends the format-converted first data information to a slave device. The interface IP core control method provided by the present application outputs data information in an AHB protocol standard format, and does not need to configure AHB protocol conversion for each interface IP core separately.

Description

Interface IP core control method, interface IP core, device and medium
Technical Field
The present application relates to the field of data exchange, and in particular, to an interface IP core control method, an interface IP core, an apparatus, and a medium.
Background
In a System On Chip (SOC) design, a bus On Chip design is the most critical issue. The advanced high-performance Bus (ADVANCED HIGH performance Bus, AHB) is mainly used for connecting high-performance modules, such as a central processing unit (Central Processing Unit, CPU), direct memory access (Direct Memory Access, DMA), a digital signal Processor (DIGITAL SIGNAL Processor, DSP) and the like, and is used as a system-on-chip Bus of the SOC, and comprises the following characteristics of single clock edge operation, non-tri-state implementation, burst transmission support, segmented transmission support, multiple main controllers support, 32-bit to 128-bit Bus width configuration support and byte, half word and word transmission support. According to the AHB bus protocol, in a data exchange system, a special memory controller IP (Intellectual Property) core is used for completing access to an off-chip memory, and when an interface IP core is used for connecting the AHB bus, the AHB protocol conversion needs to be configured for each interface IP core independently.
Therefore, providing an interface IP core to reduce configuration AHB protocol conversion performed on the interface IP core alone is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide an interface IP core to reduce the independent configuration AHB protocol conversion of the interface IP core.
In order to solve the above technical problems, the present application provides an interface IP core control method, including:
Receiving first data information stored in a FIFO memory, wherein the first data information is sent to the FIFO memory by a main device;
Converting the first data information into an AHB protocol standard format;
And sending the converted first data information to the slave device.
Preferably, in the above method for controlling an interface IP core, after the sending the converted first data information to a slave device, the method further includes:
Receiving second data information stored in the FIFO memory, wherein the second data information is returned to the FIFO memory by the slave device;
and sending the second data information to the main equipment.
Preferably, in the above method for controlling an interface IP core, the first data information includes a read instruction and read control information;
correspondingly, the second data information comprises read data and a read response signal;
The sending the second data information to the master device includes reading out and returning the read data and the read response signal to the master device when the read FIFO is not empty.
Preferably, in the above method for controlling an interface IP core, the first data information includes a write instruction, write control information, and write data;
correspondingly, the sending the converted first data information to the slave device includes:
And when the write FIFO is empty, waiting for the write FIFO to be empty, and sending the write data read to the slave device.
Preferably, in the above method for controlling an interface IP core, the sending the converted first data information to a slave device includes:
And sending the converted first data information to a JPEG module.
The application also provides an interface IP core, which is characterized by comprising:
FIFO memory, controller;
the FIFO memory is used for receiving and caching first data information sent by the main equipment;
The controller is configured to receive the first data information stored in the FIFO memory, convert the first data information into an AHB protocol standard format, and send the converted first data information to a slave device.
Preferably, in the above interface IP core, the FIFO memory is further configured to receive and buffer second data information returned from the slave device;
The controller is further configured to receive the second data information stored in the FIFO memory and send the second data information to the master device.
The application also provides an interface IP core control device, which is characterized by comprising:
the receiving module is used for receiving first data information stored in the FIFO memory, and the first data information is sent to the FIFO memory by the main equipment;
the conversion module is used for converting the first data information into an AHB protocol standard format;
and the sending module is used for sending the converted first data information to the slave equipment.
The application also provides an interface IP core control device, which is characterized by comprising:
A memory for storing a computer program;
And the processor is used for realizing the steps of the interface IP core control method when executing the computer program.
The application also provides a computer readable storage medium, which is characterized in that the computer readable storage medium stores a computer program, and the computer program realizes the steps of the interface IP core control method when being executed by a processor.
According to the interface IP core control method provided by the application, the received first data information is converted into the AHB protocol standard format by receiving and caching the first data information sent by the master device, and the first data information subjected to format conversion is sent to the slave device. According to the interface IP core control method provided by the application, the output data information is in the AHB protocol standard format, and the interface IP core is not required to be solely configured with AHB protocol conversion.
In addition, the application also provides an interface IP core, a device and a medium, which are applied to the interface IP core control method, and have the same effects.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a flowchart of an interface IP core control method provided in an embodiment of the present application;
fig. 2 is a schematic diagram of an interface IP core according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a FIFO memory according to an embodiment of the present application;
FIG. 4 is a timing diagram of a master device performing a write operation according to the present application;
FIG. 5 is a timing diagram of a master device performing a read operation according to the present application;
fig. 6 is a block diagram of an interface IP core control device according to an embodiment of the present application
Fig. 7 is a block diagram of an interface IP core control apparatus according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
The core of the application is to provide an interface IP core control method to reduce the configuration AHB protocol conversion of the interface IP core alone.
In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description.
Fig. 1 is a flowchart of an interface IP core control method provided by an embodiment of the present application, and as shown in fig. 1, the present application provides an interface IP core control method, including:
S10, receiving first data information stored in the FIFO memory 22, wherein the first data information is sent to the FIFO memory 22 by the main device 21;
S11, converting the first data information into an AHB protocol standard format;
And S12, transmitting the converted first data information to the slave device 24.
First-in first-Out (FIRST IN FIRST Out, FIFO), the FIFO memory 22 mentioned in this embodiment is a first-in first-Out data buffer. In system design, FIFO memory 22 is widely used for the purpose of increasing data transfer rate, processing a large number of data streams, matching systems with different transfer rates, thereby improving system performance. FIFO memory 22 is a first-in first-out dual-port buffer, i.e., the first data entered therein is first shifted out, with one input port of the memory and the other port being the output port of the memory. The FIFO memory 22 is divided into a write-dedicated area and a read-dedicated area. The read operation and the write operation may be performed asynchronously, and data written on the write area is read out from the area at the read end in the order of writing.
In addition, different areas may be divided in the FIFO memory 22 for storing different data types, and the embodiment is not particularly limited.
The present embodiment is not limited to the specific form of the master device 21 and the slave device 24, for example, DSP, CPU, field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), image processor (Graphics Processing Unit, GPU), etc., any device may be used as the master device 21, any device may also be used as the slave device 24, and the present embodiment is not limited specifically and may be designed according to practical situations. When the slave device 24 and the interface IP core are connected through the AHB bus, the data received by the AHB should conform to the AHB protocol specification, and the data conforming to the AHB protocol specification is transmitted to the slave device 24 through the AHB bus. In addition, the present embodiment does not limit the connection manner between the host device 21 and the interface IP core.
The embodiment does not limit the specific information type of the first data information, such as information of a read instruction, a write instruction, write data, and the like.
Specifically, after the master device 21 sends the first data information to the FIFO memory 22, the FIFO memory 22 buffers the received first data information, and the controller 23 converts the first data information received by the FIFO memory 22 into an AHB bus protocol standard format and then transmits the converted first data information to the slave device 24.
In addition, when the slave device 24 needs to return the data information to the master device 21 after the first data information is transmitted to the slave device 24, the embodiment provides a preferred embodiment, where the method for controlling the interface IP core further includes, after transmitting the converted first data information to the slave device 24:
Receiving second data information stored in the FIFO memory 22, the second data information being returned to the FIFO memory 22 by the slave device 24;
the second data information is sent to the master device 21.
The second data information mentioned in this embodiment refers to the data information returned after the first data information is received from the device 24, and the specific information type of the second data information is not limited in this embodiment.
Specifically, when the first data information is received from the device 24, the second data information is returned, the FIFO memory 22 receives and buffers the second data information, and the controller 23 sends the second data information read-out to the master device 21.
The present embodiment provides a preferred solution, where the interface IP core receives the second data information returned from the device 24, and completes the return operation of the data information.
The interface IP core control method provided by the present application converts the received first data information into the AHB protocol standard format by receiving and buffering the first data information sent by the master device 21, and sends the first data information subjected to format conversion to the slave device 24. According to the interface IP core control method provided by the application, the output data information is in the AHB protocol standard format, and the interface IP core is not required to be solely configured with AHB protocol conversion.
According to the above embodiment, the present embodiment provides a preferred solution when the interface IP core performs a read operation, where the first data information includes a read instruction and read control information;
correspondingly, the second data information comprises read data and a read response signal;
Transmitting the second data information to the master 21 includes reading out the read data and the read response signal and returning to the master 21 when the read FIFO223 is not empty.
It should be noted that the read FIFO223 refers to a portion of the memory space in the FIFO memory 22 for storing read data and read response signals.
Specifically, the master device 21 transmits a read instruction and read control information to the FIFO memory 22, the controller 23 converts the read instruction and read control information into an AHB protocol standard format and transmits the converted read instruction and read control information to the slave device 24, the slave device 24 receives the read instruction and read control information, returns read data and read response signals, the FIFO memory 22 receives and stores the read data and read response signals, and when the read FIFO223 is not empty, the controller 23 reads out the read data and read response signals and returns them to the master device 21.
The embodiment provides a specific scheme for performing the read operation, and the controller 23 converts the read instruction and the read control information into the standard format of the AHB protocol and sends the converted data to the slave device 24, so that the problem that the common interface IP core needs to perform configuration AHB protocol conversion on the interface IP core alone is avoided.
According to the embodiment, when writing operation is performed, in the interface IP core control method, the first data information comprises a writing instruction, writing control information and writing data;
Correspondingly, transmitting the converted first data information to the slave device 24 comprises:
Write data read-outs are sent to the slave device 24 when the write FIFO222 is not empty, and write data read-outs are sent to the slave device 24 when the write FIFO222 is empty waiting for the write FIFO222 to be non-empty.
It should be noted that, the write FIFO222 refers to a portion of the storage space in the FIFO memory for writing data.
Specifically, the master device 21 sends a write command, write control information, and write data to the FIFO memory 22, and after the controller 23 converts the write data into an AHB protocol standard format, the controller 23 determines that the current data FIFO is not empty, sends a write data read to the slave device 24, and waits for the write FIFO222 to be empty when the write FIFO222 is empty, and sends a write data read to the slave device 24.
The embodiment provides a specific scheme for performing the writing operation, and the controller 23 converts the writing data into the standard format of the AHB protocol and sends the standard format of the AHB protocol to the slave device 24, so that the problem that a common interface IP core needs to perform configuration AHB protocol conversion on the interface IP core alone is avoided.
According to the above embodiment, the present embodiment provides a preferred embodiment, in which the interface IP core is connected to the JPEG module of the slave device 24 through the AHB bus, and in the above interface IP core control method, the sending the converted first data information to the slave device 24 includes:
and sending the converted first data information to a JPEG module.
When the JPEG module is required to be debugged by the FPGA, the JPEG module register is checked by the interface IP provided by the application to read and write, so that the configuration of JPEG is completed, and the interface IP core is not required to be independently configured with AHB protocol conversion, so that the debugging speed is accelerated, the labor force is saved, and the debugging period is shortened.
Fig. 2 is a schematic diagram of an interface IP core provided by an embodiment of the present application, and as shown in fig. 2, the present application further provides an interface IP core, including:
FIFO memory 22, controller 23;
The FIFO memory 22 is for receiving and buffering the first data information transmitted by the master device 21;
The controller 23 is configured to receive the first data information stored in the FIFO memory 22, convert the first data information into an AHB protocol standard format, and transmit the converted first data information to the slave device 24.
The FIFO memory 22 according to the present embodiment is a first-in first-out data buffer. In system design, FIFO memory 22 is widely used for the purpose of increasing data transfer rate, processing a large number of data streams, matching systems with different transfer rates, thereby improving system performance. FIFO memory 22 is a first-in first-out dual-port buffer, i.e., the first data entered therein is first shifted out, with one input port of the memory and the other port being the output port of the memory. The FIFO memory 22 is divided into a write-dedicated area and a read-dedicated area. The read operation and the write operation may be performed asynchronously, and data written on the write area is read out from the area at the read end in the order of writing.
The present embodiment does not limit what the controller 23 is specifically, such as a CPU, an MCU, or the like. The present embodiment is not particularly limited.
The present embodiment is not limited to the specific form of the master device 21 and the slave device 24, for example, DSP, CPU, field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), image processor (Graphics Processing Unit, GPU), etc., any device may be used as the master device 21, any device may also be used as the slave device 24, and the present embodiment is not limited specifically and may be designed according to practical situations. When the slave device 24 and the interface IP core are connected through the AHB bus, the data received by the AHB should conform to the AHB protocol specification, and the data conforming to the AHB protocol specification is transmitted to the slave device 24 through the AHB bus. In addition, the present embodiment does not limit the connection manner between the host device 21 and the interface IP core.
After the master device 21 transmits the first data information to the FIFO memory 22, the FIFO memory 22 is configured to receive and buffer the first data information transmitted by the master device 21, and the controller 23 receives the first data information stored in the FIFO memory 22, converts the first data information into an AHB protocol standard format, and transmits the converted first data information to the slave device 24.
In addition, when the slave device 24 needs to return the data information to the master device 21 after the first data information is transmitted to the slave device 24, the embodiment provides a preferred scheme
The FIFO memory 22 is also used to receive and buffer the second data information returned from the device 24;
the controller 23 is further configured to receive the second data information stored in the FIFO memory 22 and to transmit the second data information to the master device 21.
When the slave device 24 returns the second data information to the FIFO memory 22, the FIFO stores the second data information received and buffered from the slave device 24, and the controller 23 receives the second data information stored in the FIFO memory 22 and transmits the second data information to the master device 21.
The present embodiment provides a preferred solution, where the interface IP core receives the second data information returned from the device 24, and completes the return operation of the data information.
The interface IP core provided by the present application receives and caches the first data information sent by the master device 21 through the FIFO memory 22, and the controller 23 converts the received first data information into an AHB protocol standard format, and sends the first data information subjected to format conversion to the slave device 24. The interface IP core provided by the application outputs the data information in the AHB protocol standard format, and the interface IP core does not need to be solely configured with AHB protocol conversion.
According to the above embodiment, when the interface IP core performs a read operation, the present embodiment provides a preferred scheme, and fig. 3 is a schematic diagram of a FIFO memory according to an embodiment of the present application;
The control information FIFO221 is used for receiving and buffering the read instruction and the read control information;
The read FIFO223 is for receiving and buffering read data and read response signals;
The controller 23 is configured to read the read data and the read response signal from the read FIFO223 and return the read data and the read response signal to the master 21 when the read FIFO223 is not empty.
The read FIFO223 is used to buffer read data and response signals returned from the device 24, and the control information FIFO221 is used to buffer read instructions and read control information sent by the master device 21.
When the master device 21 sends a read command and read control information to the interface IP core, the control information FIFO221 receives and buffers the read command and read control information, the controller 23FIFO converts the read command and read control information into an AHB protocol standard format according to the AHB protocol and transmits the converted read command and read control information to the slave device 24, the slave device 24 returns read data and read response signals, the read FIFO223 receives and buffers the read data and read response signals, and when the read FIFO223 is not empty, the controller 23 reads the read data and read response signals from the read FIFO223 and returns the read data and read response signals to the master device 21.
The present embodiment provides an interface IP core, where the controller 23 converts the read command and the read control information into the standard format of the AHB protocol and sends the converted read command and the read control information to the slave device 24, so that the need of configuring the AHB protocol conversion on the interface IP core alone by the common interface IP core is avoided.
According to the above embodiment, when the interface IP core is used for performing a write operation, the present embodiment provides a preferred scheme in which the FIFO memory 22 includes a write FIFO222;
The control information FIFO221 is also used to receive and buffer write instructions and write control information;
Write FIFO222 is used to receive and buffer write data;
the controller 23 is configured to send the write data read-out to the slave device 24 when the write FIFO222 is not empty, and to wait for the write FIFO222 to be empty to send the write data read-out to the slave device 24 when the write FIFO222 is empty.
Write FIFO222 is used to receive and buffer write data information sent by master device 21.
When a write operation is required, the master 21 sends a write instruction, write control information and write data to the interface IP core, the control information FIFO221 receives and buffers the write instruction and write control information, the write FIFO222 receives and buffers the write data, the controller 23 converts the write data into an AHB protocol standard format according to the AHB protocol, sends write data readout to the slave 24 when the write FIFO222 is not empty, and waits for the write FIFO222 to be sent to the slave 24 when the write FIFO222 is not empty.
The present embodiment provides an interface IP core when performing a write operation, where the controller 23 converts write data into an AHB protocol standard format and sends the write data to the slave device 24, so that a common interface IP core is avoided from needing to perform configuration AHB protocol conversion on the interface IP core alone.
According to the above embodiment, the present embodiment provides a preferred embodiment, where the interface IP core is connected to the slave device 24JPEG module via an AHB bus,
The controller 23 is connected to the JPEG module and is configured to send the converted first data information to the JPEG module.
When the JPEG module is required to be debugged by the FPGA, the JPEG module register is checked by the interface IP provided by the application to read and write, so that the configuration of JPEG is completed, and the interface IP core is not required to be independently configured with AHB protocol conversion, so that the debugging speed is accelerated, the labor force is saved, and the debugging period is shortened.
In addition, it should be noted that the controller 23 in this embodiment is mainly implemented by a state machine, and includes 6 states, FIDLE, BUSREQ, ADDR, RD _data, wr_data, and FRETRY.
The state is specifically described as follows:
FIDLE an idle state, a default state after the interface IP core is reset, and returning to the state when the main equipment 21 does not send an instruction or after all the instructions sent by the main equipment 21 are executed;
BUSREQ, requesting bus state, applying bus control right to arbiter by m_ hbusreq signal, obtaining bus control right and then entering ADDR state;
address field state, send out initial address and control signal to slave device 24, when master device 21 sends out read command and read FIFO223 is not full, go into RD_DATA state, when master device 21 sends out write command and write FIFO222 is not empty, go into WR_DATA state;
RD_DATA is read DATA state, according to the received control information, the control address and htrans are changed, the DATA and response of slave end are received, when the last DATA of the instruction is received, the state is FIDLE, when the response of slave end is RETRY, the state is FRETRY;
writing DATA state, controlling address and htrans change according to received control information, sending DATA to slave end, when the last DATA of said instruction is sent, making FIDLE state, when the response of slave end is RETRY, making FRETRY state;
FRETRY a RETRY state, which re-reads and writes the DATA of the RETRY address, and resumes the bus transfer operation after two clock cycles, and enters the rd_data state or the wr_data state.
The main signals of the interface at the end of the main device 21 are as follows:
Fig. 4 is a timing chart of a write operation performed by a master device according to the present application, as shown in fig. 4, the control information FIFO221 and the write FIFO222 use independent full signals, when the control information is valid and the control information FIFO221 is not full, control information (l_addr, l_burst, l_size, l_length) of the master device 21 is put into the control information FIFO221, and when the data is valid and the write data FIFO is not full, data to be transmitted by the master device 21 is put into the write data FIFO in sequence.
Fig. 5 is a timing chart of a read operation performed by a master device according to the present application, as shown in fig. 5, a read operation master device 21 only needs to send control information, and a l_resp signal is a read response signal returned to the master device 21, and is output after being buffered in a read data FIFO and synchronized with returned data l_rdata, where one data corresponds to one response signal on an AHB bus.
In the above embodiments, the detailed description is given to the method for controlling the interface IP core, and the present application further provides a corresponding embodiment of the device for controlling the interface IP core. It should be noted that the present application describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.
Fig. 6 is a block diagram of an interface IP core control device according to an embodiment of the present application, and the present application further provides an interface IP core control device, including:
A receiving module 61, configured to receive first data information stored in the FIFO memory, where the first data information is sent to the FIFO memory by the master device;
A conversion module 62, configured to convert the first data information into an AHB protocol standard format;
A sending module 63, configured to send the converted first data information to the slave device.
The receiving module 61 receives the first data information stored in the FIFO memory, the first data information is transmitted from the master device to the FIFO memory, the converting module 62 converts the first data information into an AHB protocol standard format, and the transmitting module 63 transmits the converted first data information to the slave device.
The interface IP core control device provided by the application outputs the data information in the AHB protocol standard format, and the interface IP core is not required to be solely configured with AHB protocol conversion.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
Fig. 7 is a block diagram of an interface IP core control apparatus according to another embodiment of the present application, and as shown in fig. 7, the interface IP core control apparatus includes a memory 70 for storing a computer program;
The processor 71 is configured to implement the steps of the method for acquiring user operation habit information according to the above-described embodiment (interface IP core control method) when executing the computer program.
The interface IP core control device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 71 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 71 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable gate array (fieldprogrammable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 71 may also include a main processor, which is a processor for processing data in a wake-up state, also referred to as a central processor (Central Processing Unit, CPU), and a coprocessor, which is a low-power processor for processing data in a standby state. In some embodiments, the processor 71 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor 71 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.
Memory 70 may include one or more computer-readable storage media, which may be non-transitory. Memory 70 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 70 is used to store at least a computer program 701 that, when loaded and executed by the processor 71, is capable of performing the relevant steps of the xxxxxx method disclosed in any of the previous embodiments. In addition, the resources stored in the memory 70 may further include an operating system 702, data 703, and the like, where the storage manner may be transient storage or permanent storage. Operating system 702 may include Windows, unix, linux, among other things. The data 703 may include, but is not limited to, data involved in implementing the interface IP core control method, and the like.
In some embodiments, the interface IP core control device may further include a display screen 72, an input/output interface 73, a communication interface 74, a power supply 75, and a communication bus 76.
Those skilled in the art will appreciate that the architecture shown in fig. 7 is not limiting of the interface IP core control device and may include more or fewer components than shown.
The interface IP core control apparatus provided by the embodiment of the present application includes a memory and a processor, where the processor is capable of implementing a method of receiving and buffering first data information sent by a master device 21, converting the received first data information into an AHB protocol standard format, and sending the first data information subjected to format conversion to a slave device 24 when executing a program stored in the memory. Because the output data information is in an AHB protocol standard format, the interface IP core does not need to be solely configured with AHB protocol conversion.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps described in the above-described method embodiments (the method may be a method corresponding to the server side, a method corresponding to the diagnostic apparatus side, or a method corresponding to the server side and the diagnostic apparatus side).
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present application. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RandomAccess Memory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The computer readable storage medium provided in this embodiment has a computer program stored thereon, and when the processor executes the program, the interface IP core control method is implemented to convert the received first data information into an AHB protocol standard format by receiving and buffering the first data information transmitted by the master device 21, and transmit the first data information subjected to the format conversion to the slave device 24. Because the output data information is in an AHB protocol standard format, the interface IP core does not need to be solely configured with AHB protocol conversion.
The method, the interface IP core, the device and the medium for controlling the interface IP core are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

Claims (6)

1.一种接口IP核控制方法，其特征在于，接口IP核中包含FIFO存储器，控制器，主设备与从设备通过接口IP核连接，从设备与接口IP核之间通过AHB总线连接；所述FIFO存储器中包括控制信息FIFO、写FIFO以及读FIFO；接口IP核应用在数据交换系统中；包括：1. An interface IP core control method, characterized in that the interface IP core includes a FIFO memory, a controller, a master device and a slave device are connected through the interface IP core, and the slave device and the interface IP core are connected through an AHB bus; the FIFO memory includes a control information FIFO, a write FIFO and a read FIFO; the interface IP core is applied in a data exchange system; comprising: 接收FIFO存储器中存储的第一数据信息，所述第一数据信息由主设备发送至所述FIFO存储器；Receiving first data information stored in a FIFO memory, wherein the first data information is sent to the FIFO memory by a master device; 将所述第一数据信息转换为AHB协议标准格式；Converting the first data information into an AHB protocol standard format; 将转换后的所述第一数据信息发送至从设备；Sending the converted first data information to the slave device; 所述第一数据信息包括：读指令和读控制信息；The first data information includes: read instructions and read control information; 主设备向FIFO存储器发送读指令和读控制信息，控制器将读指令和读控制信息转换成AHB协议标准格式后发送至从设备；The master device sends a read instruction and read control information to the FIFO memory, and the controller converts the read instruction and read control information into the AHB protocol standard format and sends it to the slave device; 所述第一数据信息包括：写指令、写控制信息和写数据；The first data information includes: write instructions, write control information and write data; 主设备向FIFO存储器发送写指令、写控制信息和写数据，控制器将写数据转换成AHB协议标准格式；The master device sends write instructions, write control information and write data to the FIFO memory, and the controller converts the write data into the AHB protocol standard format; 对应地，所述将转换后的所述第一数据信息发送至从设备包括：Correspondingly, sending the converted first data information to the slave device includes: 当写FIFO非空时，将转换后的所述写数据读出发送至所述从设备；当所述写FIFO为空时，等待所述写FIFO非空时将所述写数据读出发送至所述从设备；When the write FIFO is not empty, the converted write data is read out and sent to the slave device; when the write FIFO is empty, the write data is read out and sent to the slave device when the write FIFO is not empty; 所述将转换后的所述第一数据信息发送至从设备之后，还包括：After sending the converted first data information to the slave device, the method further includes: 接收所述FIFO存储器中存储的第二数据信息，所述第二数据信息由所述从设备返回至所述FIFO存储器；receiving second data information stored in the FIFO memory, the second data information being returned by the slave device to the FIFO memory; 将所述第二数据信息发送至所述主设备；Sending the second data information to the master device; 所述第二数据信息包括读数据和读响应信号；The second data information includes read data and a read response signal; 所述将所述第二数据信息发送至所述主设备包括：当读FIFO非空时，将所述读数据和所述读响应信号读出并返回至所述主设备；The sending the second data information to the master device comprises: when the read FIFO is not empty, reading out the read data and the read response signal and returning them to the master device; 其中，控制器是通过状态机实现的，包括6个状态：FIDLE、BUSREQ、ADDR、RD_DATA、WR_DATA、FRETRY；Among them, the controller is implemented through a state machine, including 6 states: FIDLE, BUSREQ, ADDR, RD_DATA, WR_DATA, FRETRY; FIDLE状态表征空闲状态，接口IP核复位后的默认状态，当主设备未发送指令时或主设备发送的指令全部执行完成后，回到此状态；当主设备发送指令且控制FIFO非满时，进入BUSREQ状态；The FIDLE state represents the idle state, which is the default state after the interface IP core is reset. When the master device does not send any instructions or all the instructions sent by the master device are executed, it returns to this state; when the master device sends instructions and the control FIFO is not full, it enters the BUSREQ state; BUSREQ状态用于表征请求总线状态，通过m_hbusreq信号向仲裁器申请总线控制权，获得总线控制权后进入ADDR状态；The BUSREQ state is used to indicate the request bus state. The arbiter is requested to control the bus through the m_hbusreq signal. After obtaining the bus control, the ADDR state is entered. ADDR状态用于表征地址段状态，向从设备端送出起始地址与控制信号，当主设备发送读指令且读FIFO非满时，进入RD_DATA状态，当主设备发送写指令且写FIFO非空时，进入WR_DATA状态；The ADDR state is used to represent the address segment state, sending the starting address and control signal to the slave device. When the master device sends a read command and the read FIFO is not full, it enters the RD_DATA state. When the master device sends a write command and the write FIFO is not empty, it enters the WR_DATA state. RD_DATA状态用于表征读数据状态，根据接收到的控制信息，控制地址和htrans变化，接收slave端的数据和响应，当接收完该指令的最后一个数据时，进入FIDLE状态，当从设备端响应为RETRY时，进入FRETRY状态；The RD_DATA state is used to represent the read data state. According to the received control information, the control address and htrans change, the slave end data and response are received. When the last data of the instruction is received, the FIDLE state is entered. When the slave end responds with RETRY, the FRETRY state is entered. WR_DATA状态用于表征写数据状态，根据接收到的控制信息，控制地址和htrans变化，向slave端发送数据,当发送完该指令的最后一个数据时，进入FIDLE状态，当从设备端响应为RETRY时，进入FRETRY状态；The WR_DATA state is used to represent the write data state. According to the received control information, the control address and htrans change, data is sent to the slave end. When the last data of the instruction is sent, it enters the FIDLE state. When the slave device responds with RETRY, it enters the FRETRY state. FRETRY状态用于表征重试状态，此状态会重新读写RETRY地址的那一笔数据，两个时钟周期后重新开始总线的传输操作，进入RD_DATA状态或WR_DATA状态；The FRETRY state is used to represent the retry state. In this state, the data at the RETRY address will be re-read and written. After two clock cycles, the bus transmission operation will be restarted and the RD_DATA state or WR_DATA state will be entered. 主设备进行写操作时，控制信息FIFO和写FIFO使用独立的full信号，当控制信息有效且控制信息FIFO非满时，将主设备端控制信息放入控制信息FIFO中，当数据有效且写数据FIFO非满时，将主设备端需要发送的数据依次放入写数据FIFO中；所述主设备端控制信息包括：指令操作地址、突发传输类型信号、一次传输字节数、写/读数据的长度；When the master device performs a write operation, the control information FIFO and the write FIFO use independent full signals. When the control information is valid and the control information FIFO is not full, the control information of the master device is placed in the control information FIFO. When the data is valid and the write data FIFO is not full, the data to be sent by the master device is placed in the write data FIFO in sequence. The control information of the master device includes: instruction operation address, burst transmission type signal, number of bytes transmitted at one time, and length of write/read data. 主设备进行读操作时，读操作主设备端只需要发送控制信息，l_resp信号为返回至主设备端的读响应信号，经过读数据FIFO缓存后输出，与返回的数据l_rdata同步；AHB总线上一个数据对应一个响应信号。When the master device performs a read operation, the master device only needs to send control information. The l_resp signal is the read response signal returned to the master device. It is output after being cached by the read data FIFO and is synchronized with the returned data l_rdata. One data on the AHB bus corresponds to one response signal. 2.根据权利要求1所述的接口IP核控制方法，其特征在于，所述将转换后的所述第一数据信息发送至从设备，包括：2. The interface IP core control method according to claim 1, wherein sending the converted first data information to the slave device comprises: 将转换后的所述第一数据信息发送至JPEG模块。The converted first data information is sent to the JPEG module. 3.一种接口IP核，其特征在于，接口IP核中包含FIFO存储器，控制器，主设备与从设备通过接口IP核连接，从设备与接口IP核之间通过AHB总线连接；接口IP核应用在数据交换系统中；包括：3. An interface IP core, characterized in that the interface IP core includes a FIFO memory, a controller, a master device and a slave device are connected through the interface IP core, and the slave device and the interface IP core are connected through an AHB bus; the interface IP core is applied in a data exchange system; comprising: FIFO存储器，控制器；所述FIFO存储器中包括控制信息FIFO、写FIFO以及读FIFO；FIFO memory, controller; the FIFO memory includes a control information FIFO, a write FIFO and a read FIFO; 所述FIFO存储器用于接收并缓存由主设备发送的第一数据信息；The FIFO memory is used to receive and buffer the first data information sent by the master device; 所述控制器用于接收所述FIFO存储器中存储的所述第一数据信息，将所述第一数据信息转换为AHB协议标准格式，并将转换后的所述第一数据信息发送至从设备；所述第一数据信息包括：写指令、写控制信息和写数据；The controller is used to receive the first data information stored in the FIFO memory, convert the first data information into an AHB protocol standard format, and send the converted first data information to the slave device; the first data information includes: write instructions, write control information and write data; 所述第一数据信息包括：读指令和读控制信息；The first data information includes: read instructions and read control information; 主设备向FIFO存储器发送读指令和读控制信息，控制器将读指令和读控制信息转换成AHB协议标准格式后发送至从设备；The master device sends a read instruction and read control information to the FIFO memory, and the controller converts the read instruction and read control information into the AHB protocol standard format and sends it to the slave device; 主设备向FIFO存储器发送写指令、写控制信息和写数据，控制器将写数据转换成AHB协议标准格式；The master device sends write instructions, write control information and write data to the FIFO memory, and the controller converts the write data into the AHB protocol standard format; 对应地，所述将转换后的所述第一数据信息发送至从设备包括：Correspondingly, sending the converted first data information to the slave device includes: 当写FIFO非空时，将转换后的所述写数据读出发送至所述从设备；当所述写FIFO为空时，等待所述写FIFO非空时将所述写数据读出发送至所述从设备；When the write FIFO is not empty, the converted write data is read out and sent to the slave device; when the write FIFO is empty, the write data is read out and sent to the slave device when the write FIFO is not empty; 所述FIFO存储器还用于：接收并缓存所述从设备返回的第二数据信息；The FIFO memory is also used to: receive and cache the second data information returned by the slave device; 所述控制器还用于：接收所述FIFO存储器中存储的所述第二数据信息，将所述第二数据信息发送至所述主设备；The controller is further configured to: receive the second data information stored in the FIFO memory, and send the second data information to the master device; 所述第二数据信息包括读数据和读响应信号；The second data information includes read data and a read response signal; 所述将所述第二数据信息发送至所述主设备包括：当读FIFO非空时，将所述读数据和所述读响应信号读出并返回至所述主设备；The sending the second data information to the master device comprises: when the read FIFO is not empty, reading out the read data and the read response signal and returning them to the master device; 其中，控制器是通过状态机实现的，包括6个状态：FIDLE、BUSREQ、ADDR、RD_DATA、WR_DATA、FRETRY；Among them, the controller is implemented through a state machine, including 6 states: FIDLE, BUSREQ, ADDR, RD_DATA, WR_DATA, FRETRY; FIDLE状态表征空闲状态，接口IP核复位后的默认状态，当主设备未发送指令时或主设备发送的指令全部执行完成后，回到此状态；当主设备发送指令且控制FIFO非满时，进入BUSREQ状态；The FIDLE state represents the idle state, which is the default state after the interface IP core is reset. When the master device does not send any instructions or all the instructions sent by the master device are executed, it returns to this state; when the master device sends instructions and the control FIFO is not full, it enters the BUSREQ state; BUSREQ状态用于表征请求总线状态，通过m_hbusreq信号向仲裁器申请总线控制权，获得总线控制权后进入ADDR状态；The BUSREQ state is used to indicate the request bus state. The arbiter is requested to control the bus through the m_hbusreq signal. After obtaining the bus control, the ADDR state is entered. ADDR状态用于表征地址段状态，向从设备端送出起始地址与控制信号，当主设备发送读指令且读FIFO非满时，进入RD_DATA状态，当主设备发送写指令且写FIFO非空时，进入WR_DATA状态；The ADDR state is used to represent the address segment state, sending the starting address and control signal to the slave device. When the master device sends a read command and the read FIFO is not full, it enters the RD_DATA state. When the master device sends a write command and the write FIFO is not empty, it enters the WR_DATA state. RD_DATA状态用于表征读数据状态，根据接收到的控制信息，控制地址和htrans变化，接收slave端的数据和响应，当接收完该指令的最后一个数据时，进入FIDLE状态，当从设备端响应为RETRY时，进入FRETRY状态；The RD_DATA state is used to represent the read data state. According to the received control information, the control address and htrans change, the slave end data and response are received. When the last data of the instruction is received, the FIDLE state is entered. When the slave end responds with RETRY, the FRETRY state is entered. WR_DATA状态用于表征写数据状态，根据接收到的控制信息，控制地址和htrans变化，向slave端发送数据,当发送完该指令的最后一个数据时，进入FIDLE状态，当从设备端响应为RETRY时，进入FRETRY状态；The WR_DATA state is used to represent the write data state. According to the received control information, the control address and htrans change, data is sent to the slave end. When the last data of the instruction is sent, it enters the FIDLE state. When the slave device responds with RETRY, it enters the FRETRY state. FRETRY状态用于表征重试状态，此状态会重新读写RETRY地址的那一笔数据，两个时钟周期后重新开始总线的传输操作，进入RD_DATA状态或WR_DATA状态；The FRETRY state is used to represent the retry state. In this state, the data at the RETRY address will be re-read and written. After two clock cycles, the bus transmission operation will be restarted and the RD_DATA state or WR_DATA state will be entered. 主设备进行写操作时，控制信息FIFO和写FIFO使用独立的full信号，当控制信息有效且控制信息FIFO非满时，将主设备端控制信息放入控制信息FIFO中，当数据有效且写数据FIFO非满时，将主设备端需要发送的数据依次放入写数据FIFO中；所述主设备端控制信息包括：指令操作地址、突发传输类型信号、一次传输字节数、写/读数据的长度；When the master device performs a write operation, the control information FIFO and the write FIFO use independent full signals. When the control information is valid and the control information FIFO is not full, the control information of the master device is placed in the control information FIFO. When the data is valid and the write data FIFO is not full, the data to be sent by the master device is placed in the write data FIFO in sequence. The control information of the master device includes: instruction operation address, burst transmission type signal, number of bytes transmitted at one time, and length of write/read data. 主设备进行读操作时，读操作主设备端只需要发送控制信息，l_resp信号为返回至主设备端的读响应信号，经过读数据FIFO缓存后输出，与返回的数据l_rdata同步；AHB总线上一个数据对应一个响应信号。When the master device performs a read operation, the master device only needs to send control information. The l_resp signal is the read response signal returned to the master device. It is output after being cached by the read data FIFO and is synchronized with the returned data l_rdata. One data on the AHB bus corresponds to one response signal. 4.一种接口IP核控制装置，其特征在于，接口IP核中包含FIFO存储器，控制器，主设备与从设备通过接口IP核连接，从设备与接口IP核之间通过AHB总线连接；所述FIFO存储器中包括控制信息FIFO、写FIFO以及读FIFO；接口IP核应用在数据交换系统中；包括：4. An interface IP core control device, characterized in that the interface IP core includes a FIFO memory, a controller, a master device and a slave device are connected through the interface IP core, and the slave device and the interface IP core are connected through an AHB bus; the FIFO memory includes a control information FIFO, a write FIFO and a read FIFO; the interface IP core is applied in a data exchange system; comprising: 接收模块，用于接收FIFO存储器中存储的第一数据信息，所述第一数据信息由主设备发送至所述FIFO存储器；A receiving module, used for receiving first data information stored in the FIFO memory, wherein the first data information is sent to the FIFO memory by the master device; 转换模块，用于将所述第一数据信息转换为AHB协议标准格式；A conversion module, used for converting the first data information into an AHB protocol standard format; 发送模块，用于将转换后的所述第一数据信息发送至从设备；A sending module, used for sending the converted first data information to a slave device; 所述第一数据信息包括：写指令、写控制信息和写数据；The first data information includes: write instructions, write control information and write data; 所述第一数据信息包括：读指令和读控制信息；The first data information includes: read instructions and read control information; 主设备向FIFO存储器发送读指令和读控制信息，控制器将读指令和读控制信息转换成AHB协议标准格式后发送至从设备；The master device sends a read instruction and read control information to the FIFO memory, and the controller converts the read instruction and read control information into the AHB protocol standard format and sends it to the slave device; 主设备向FIFO存储器发送写指令、写控制信息和写数据，控制器将写数据转换成AHB协议标准格式；The master device sends write instructions, write control information and write data to the FIFO memory, and the controller converts the write data into the AHB protocol standard format; 对应地，所述发送模块具体用于当写FIFO非空时，将转换后的所述写数据读出发送至所述从设备；当所述写FIFO为空时，等待所述写FIFO非空时将所述写数据读出发送至所述从设备；Correspondingly, the sending module is specifically used for, when the write FIFO is not empty, reading out the converted write data and sending it to the slave device; when the write FIFO is empty, waiting for the write FIFO to be not empty and then reading out the write data and sending it to the slave device; 所述将转换后的所述第一数据信息发送至从设备之后，还包括：After sending the converted first data information to the slave device, the method further includes: 接收所述FIFO存储器中存储的第二数据信息，所述第二数据信息由所述从设备返回至所述FIFO存储器；receiving second data information stored in the FIFO memory, the second data information being returned by the slave device to the FIFO memory; 将所述第二数据信息发送至所述主设备；Sending the second data information to the master device; 所述第二数据信息包括读数据和读响应信号；The second data information includes read data and a read response signal; 所述将所述第二数据信息发送至所述主设备包括：当读FIFO非空时，将所述读数据和所述读响应信号读出并返回至所述主设备；The sending the second data information to the master device comprises: when the read FIFO is not empty, reading out the read data and the read response signal and returning them to the master device; 其中，控制器是通过状态机实现的，包括6个状态：FIDLE、BUSREQ、ADDR、RD_DATA、WR_DATA、FRETRY；Among them, the controller is implemented through a state machine, including 6 states: FIDLE, BUSREQ, ADDR, RD_DATA, WR_DATA, FRETRY; FIDLE状态表征空闲状态，接口IP核复位后的默认状态，当主设备未发送指令时或主设备发送的指令全部执行完成后，回到此状态；当主设备发送指令且控制FIFO非满时，进入BUSREQ状态；The FIDLE state represents the idle state, which is the default state after the interface IP core is reset. When the master device does not send any instructions or all the instructions sent by the master device are executed, it returns to this state; when the master device sends instructions and the control FIFO is not full, it enters the BUSREQ state; BUSREQ状态用于表征请求总线状态，通过m_hbusreq信号向仲裁器申请总线控制权，获得总线控制权后进入ADDR状态；The BUSREQ state is used to indicate the request bus state. The arbiter is requested to control the bus through the m_hbusreq signal. After obtaining the bus control, the ADDR state is entered. ADDR状态用于表征地址段状态，向从设备端送出起始地址与控制信号，当主设备发送读指令且读FIFO非满时，进入RD_DATA状态，当主设备发送写指令且写FIFO非空时，进入WR_DATA状态；The ADDR state is used to represent the address segment state, sending the starting address and control signal to the slave device. When the master device sends a read command and the read FIFO is not full, it enters the RD_DATA state. When the master device sends a write command and the write FIFO is not empty, it enters the WR_DATA state. RD_DATA状态用于表征读数据状态，根据接收到的控制信息，控制地址和htrans变化，接收slave端的数据和响应，当接收完该指令的最后一个数据时，进入FIDLE状态，当从设备端响应为RETRY时，进入FRETRY状态；The RD_DATA state is used to represent the read data state. According to the received control information, the control address and htrans change, the slave end data and response are received. When the last data of the instruction is received, the FIDLE state is entered. When the slave end responds with RETRY, the FRETRY state is entered. WR_DATA状态用于表征写数据状态，根据接收到的控制信息，控制地址和htrans变化，向slave端发送数据,当发送完该指令的最后一个数据时，进入FIDLE状态，当从设备端响应为RETRY时，进入FRETRY状态；The WR_DATA state is used to represent the write data state. According to the received control information, the control address and htrans change, data is sent to the slave end. When the last data of the instruction is sent, it enters the FIDLE state. When the slave device responds with RETRY, it enters the FRETRY state. FRETRY状态用于表征重试状态，此状态会重新读写RETRY地址的那一笔数据，两个时钟周期后重新开始总线的传输操作，进入RD_DATA状态或WR_DATA状态；The FRETRY state is used to represent the retry state. In this state, the data at the RETRY address will be re-read and written. After two clock cycles, the bus transmission operation will be restarted and the RD_DATA state or WR_DATA state will be entered. 主设备进行写操作时，控制信息FIFO和写FIFO使用独立的full信号，当控制信息有效且控制信息FIFO非满时，将主设备端控制信息放入控制信息FIFO中，当数据有效且写数据FIFO非满时，将主设备端需要发送的数据依次放入写数据FIFO中；所述主设备端控制信息包括：指令操作地址、突发传输类型信号、一次传输字节数、写/读数据的长度；When the master device performs a write operation, the control information FIFO and the write FIFO use independent full signals. When the control information is valid and the control information FIFO is not full, the control information of the master device is placed in the control information FIFO. When the data is valid and the write data FIFO is not full, the data to be sent by the master device is placed in the write data FIFO in sequence. The control information of the master device includes: instruction operation address, burst transmission type signal, number of bytes transmitted at one time, and length of write/read data. 主设备进行读操作时，读操作主设备端只需要发送控制信息，l_resp信号为返回至主设备端的读响应信号，经过读数据FIFO缓存后输出，与返回的数据l_rdata同步；AHB总线上一个数据对应一个响应信号。When the master device performs a read operation, the master device only needs to send control information. The l_resp signal is the read response signal returned to the master device. It is output after being cached by the read data FIFO and is synchronized with the returned data l_rdata. One data on the AHB bus corresponds to one response signal. 5.一种接口IP核控制装置，其特征在于，包括：5. An interface IP core control device, characterized in that it includes: 存储器，用于存储计算机程序；Memory for storing computer programs; 处理器，用于执行所述计算机程序时实现如权利要求1或2所述的接口IP核控制方法的步骤。A processor, configured to implement the steps of the interface IP core control method as claimed in claim 1 or 2 when executing the computer program. 6.一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1或2所述的接口IP核控制方法的步骤。6. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the interface IP core control method according to claim 1 or 2 are implemented.
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