CN114157275B - Wide-range low-jitter high-precision clock signal duty ratio stabilizer circuit and adjusting method - Google Patents

Abstract

The invention discloses a wide-range, low-jitter, high-precision clock signal ratio stabilizer circuit. The original clock signal generates a narrow pulse signal corresponding to the duty cycle through a pulse generation circuit, and the narrow pulse signal enters the capacitor discharge current adjustment circuit all the way. One channel enters the pulse detection and restoration circuit, and the two channels of narrow pulse signals generate restored square waves through the pulse detection and restoration circuit, and enter the capacitor discharge current adjustment circuit to adjust the slope of the triangle wave signal output by the inverter, and the triangle wave signal enters the clock signal shaping. The circuit further adjusts the phase of the narrow pulse signal, and the last two narrow pulse signals pass through the pulse detection and restoration circuit to generate a restored square wave with a duty cycle of 1:1. This circuit solves the input clock duty cycle problem well and provides an accurate clock signal for the converter core circuit. The present invention also provides a clock signal adjustment method using a wide calibration range, low jitter, and high-precision clock signal ratio stabilizer circuit.

Description

Wide-range, low-jitter, high-precision clock signal ratio stabilizer circuit and adjustment method

Technical field

The invention relates to a wide calibration range, low jitter and high-precision clock ratio stabilizer circuit, and belongs to the technical field of analog-to-digital converters.

Background technique

Converters are key components for the interface between analog systems and digital systems and are widely used in industry, communications, radar and other fields. The rapid development of converters in recent years has led to increasing requirements for sampling rates. In ultra-high-speed converters, most converter circuits use multi-channel time interleaving technology to increase the sampling rate of the overall circuit. Multi-channel time interleaving technology must Signal sampling and digital-to-analog conversion are performed strictly in accordance with the time sequence, thus placing strict requirements on the clock circuit. With the improvement of manufacturing process technology, the proportion of the rise time and fall time of the clock in the entire clock cycle continues to increase, and the problem of duty cycle imbalance becomes more and more serious. In modern communications and radio frequency transceiver standards, A 50% duty cycle clock is very necessary. The clock duty cycle calibration circuit is an important part of modern ultra-high-speed analog-to-digital converters, which generally requires the clock duty cycle to be an accurate 50%. However, due to the non-ideality of the clock signal path, temperature, power supply voltage, process angle variables and other factors, even if the clock duty cycle of the input signal source is 50%, the duty cycle of the clock signal entering the circuit will deviate. . For optimal performance, a duty cycle stabilizer circuit must be included in the converter. This circuit can adjust a clock signal whose duty cycle seriously deviates from 50% to a duty cycle of 50% within a certain clock frequency range. In addition, clock jitter directly affects parameters such as the signal-to-noise ratio of the converter. In actual circuits, the clock transition edge has slight changes in speed, causing the actual clock cycle to deviate from the ideal clock cycle, that is, clock jitter. Clock jitter affects converter dynamics. When the input signal frequency is low, clock jitter can usually be ignored. However, as the signal frequency increases, clock jitter will become a decisive factor limiting the dynamic performance of the converter. It will limit the conversion rate of the converter, reduce the signal-to-noise ratio of the converter, and even cause errors in the data conversion of the converter. In order to realize a high-speed and high-precision converter, a clock management circuit is required that can process the input clock signal with any duty cycle into a clock signal with a stable duty cycle (usually 50%) within a wide input frequency range, and Keeping it jitter low. Currently, there are many methods to implement low-jitter high-speed clock circuits, including clock circuits based on delay-locked loop technology, clock circuits based on continuous-time integrators, and clock circuits based on pulse-width control loops. They each have their own characteristics and are suitable for different types of AD converters, but they cannot meet the requirements of high precision, wide calibration range and low clock jitter at the same time.

Contents of the invention

The purpose of the present invention is to overcome the above defects and provide a wide calibration range, low jitter and high-precision clock signal ratio stabilizer circuit. Before the clock signal enters the ADC core circuit, the original clock signal generates a narrow pulse corresponding to the duty cycle through the pulse generation circuit. Pulse signal, narrow pulse signal enters the capacitor discharge current adjustment circuit all the way, and enters the pulse detection reduction circuit all the way. The two narrow pulse signals generate a reduction square wave through the pulse detection reduction circuit, and enter the capacitor discharge current adjustment circuit through the buffer module. The superposition and extraction process of charge during the charging and discharging process of the capacitor is used to adjust the rise and fall of the capacitor discharge current of the inverter, thereby adjusting the slope of the decline of the triangular wave signal output by the inverter. The triangular wave signal enters the clock signal shaping circuit to adjust the narrow pulse. The phase of the signal, the last two narrow pulse signals pass through the pulse detection and restoration circuit to generate a restored square wave with a duty cycle of 1:1. The circuit has a wide calibration range and can adjust the clock signal with a clock duty cycle of 20%-80%. The calibrated output clock signal has high-precision and low-jitter characteristics, which improves the dynamic performance of the converter and solves the problem of conversion rate caused by clock jitter. and the problem of reduced signal-to-noise ratio. And it can maintain a very high calibration accuracy in a wide calibration range, and the output clock signal duty cycle is 49%-51%. This circuit solves the input clock duty cycle problem well and provides an accurate clock signal for the converter core circuit. The invention also provides a clock signal adjustment method implemented by using a wide calibration range, low jitter, and high-precision clock signal ratio stabilizer circuit.

In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

A wide-range, low-jitter, high-precision clock ratio stabilizer circuit, including a first pulse generation circuit, a capacitor discharge current adjustment circuit, a clock signal shaping circuit and a pulse detection and restoration circuit;

The first pulse generation circuit receives the original clock signal and generates a narrow pulse signal according to the duty cycle of the original clock signal, outputs the first narrow pulse signal to the capacitor discharge current adjustment circuit, and outputs the second narrow pulse signal to the pulse detection and restoration circuit. circuit;

The capacitor discharge current adjustment circuit receives the restored square wave signal input by the pulse detection and restoration circuit and the first narrow pulse signal input by the first pulse generating circuit, converts the first narrow pulse signal into a triangular wave signal, and restores the square wave signal according to the restored square wave signal. After the duty cycle of the signal adjusts the decreasing slope of the triangular wave signal, the triangular wave signal is output to the clock signal shaping circuit;

The clock signal shaping circuit receives the triangular wave signal input by the capacitor discharge current adjustment circuit, shapes the triangular wave adjustment signal to generate a corresponding third narrow pulse signal, and outputs it to the pulse detection and restoration circuit;

The pulse detection and restoration circuit receives the first narrow pulse signal input by the first pulse generating circuit and the third narrow pulse signal input by the clock signal shaping circuit, and generates restoration according to the first narrow pulse signal and the third narrow pulse signal. Square wave signals are output to the capacitor discharge current adjustment circuit and external circuit respectively.

Furthermore, the wide calibration range low-jitter high-precision clock ratio stabilizer circuit also includes a buffer module, and the pulse detection restoration circuit outputs the restored square wave signal to the capacitor discharge current adjustment circuit through the buffer module.

Further, the capacitor discharge current adjustment circuit includes an amplifier circuit and a triangle wave adjustment circuit;

The amplifier circuit receives the restored square wave signal generated by the pulse detection and restoration circuit, adjusts the charge and discharge of the feedback capacitor according to the duty cycle of the restored square wave signal, and then adjusts the voltage signal output by the amplifier circuit to the triangle wave adjustment circuit; the triangle wave adjustment circuit receives the first The first narrow pulse signal input by a pulse generation circuit is converted into a triangular wave signal, and the slope of the triangle wave signal is adjusted according to the voltage signal input by the amplifier circuit, and then the triangular wave signal is output to the clock signal shaping circuit. Specifically, Said, the amplifier circuit receives the restored square wave signal input by the pulse detection and restoration circuit, adjusts the charging and discharging process of the feedback capacitor according to the duty cycle of the restored square wave signal, and then generates the amplifier circuit output voltage, and the amplifier circuit output voltage is determined by the current mirror. The size of the current of the inverter circuit in the triangle wave adjustment circuit is determined, thereby determining the size of the discharge current of the capacitor in the triangle wave adjustment circuit, thereby adjusting the slope of the triangle wave generated by the first narrow pulse signal, and outputting it to the clock signal shaping circuit;

Further, the amplifier circuit includes a differential amplifier and a capacitor C1. The non-inverting input terminal of the differential amplifier is connected to the reference voltage, and the inverting input terminal is the input terminal of the restored square wave signal generated by the pulse detection and restoration circuit. The capacitor C1 is connected to the differential amplifier respectively. The inverting input terminal and output terminal of the amplifier; when the square wave signal is restored to high level and low level, capacitor C1 charges and discharges respectively, and the voltage signal at the output terminal of the differential amplifier is adjusted according to the charge and discharge balance state of capacitor C1.

Further, the amplifier circuit includes NMOS transistors M0~M4, M9~M10 and M17~M23, PMOS transistors M5~M8, M11~16, fixed resistors R1~R4, adjustable resistor R5, and capacitors C1~C3;

M9 and M10 are the differential amplifier amplifier tubes in the amplifier circuit, M7 and M8 are current source loads, M17 provides current bias for the differential amplifier, M1, M2, M3 and M4 form a current mirror structure, and provide M17, M18, M19 and M22 Provide gate voltage;

The gate of M9 is connected to the output of the pulse detection reduction circuit through R3, the gate of M10 is connected to the reference voltage through the adjustable resistor R5, the drains of M9 and M10 are connected to the drains of M7 and M8 respectively, the sources of M9 and M10 are connected to the drain of M17, M0 The drain is the external reference current PIBI input terminal. The source of M0 is connected to the drain of M1 through R1. The gate of M1 is connected to the gate of M2. The gate of M3 is connected to the gate of M4. The drain of M2 is connected to the drain of M5 and the gate of M5 through R2. They are connected to the M13 gate, M14 gate and M16 gate respectively. The M6 gate is connected to the M11 gate, M12 gate and M15 gate respectively. The M13 drain, M14 drain and M16 drain are connected to the M18 drain respectively. The drain of M19 is connected to the drain of M22. The source of M18 and the source of M19 are connected to the drain of M20 and the drain of M21 respectively. One end of capacitor C2 is connected to the gate of M9 and the other end is grounded. One end of capacitor C3 is connected to the drain of M22 through resistor R4. The other end is connected to the gate of M23, the drain of M22 and the drain of M16 are the output ends of the capacitor discharge adjustment circuit, one end of the capacitor C1 is connected to the output end of the capacitor discharge adjustment circuit, and the other end is connected to the gate of M9.

Further, the triangle wave adjustment circuit includes NMOS transistors M25~M27, PMOS transistors M24, M28 and capacitor C4; the bias current source I1 and the amplifier circuit output are connected to the gate of M24, the drain of M24 is connected to the drain of M25, and the gate of M25 The pole is connected to the gate of M26 to form a current mirror structure, the drain of M26 is connected to the source of M27, the drain of M27 is connected to the drain of M28, and the gate of M27 is connected to the gate of M28 to form an inverter structure. The gate inputs of M27 and M28 are For narrow pulse signals, the drain outputs of M27 and M28 are connected to capacitor C4.

Further, the clock signal shaping circuit includes a Schmitt trigger and a second pulse generating circuit. The Schmitt trigger receives the triangular wave signal input by the capacitor discharge current adjustment circuit and shapes the triangular wave adjustment signal into a square wave. The two-pulse generating circuit converts the square wave signal into a narrow pulse signal.

Further, the specific method for the pulse detection and restoration circuit to generate and restore the square wave signal based on the first narrow pulse signal and the third narrow pulse signal is:

When the first narrow pulse signal and the third narrow pulse signal are both high level, the output of the pulse detection and restoration circuit remains unchanged; when the first narrow pulse signal is low level, the third narrow pulse signal is high level , the pulse detection and restoration circuit outputs a high level; when the first narrow pulse signal is a high level and the third narrow pulse signal is a low level, the pulse detection and restoration circuit outputs a low level.

Further, the pulse detection and restoration circuit includes a first NAND gate and a second NAND gate; the first input end of the first NAND gate is connected to the output end of the clock signal shaping circuit, and the second input end is connected to the output end of the second NAND gate. , the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the second input terminal is connected to the output terminal of the first pulse generating circuit, and the output terminals of the first NAND gate and the second NAND gate are pulses at the same time. Detect the recovery circuit output.

A wide-range, low-jitter, high-precision clock signal adjustment method is implemented using the above-mentioned wide-range, low-jitter, high-precision clock ratio stabilizer circuit, and includes the following steps:

(1) The first pulse generation circuit receives the original clock signal and generates a narrow pulse signal according to the duty cycle of the original clock signal, outputs the first narrow pulse signal to the capacitor discharge current adjustment circuit, and outputs the second narrow pulse signal to Pulse detection recovery circuit;

(2) The capacitor discharge current adjustment circuit receives the reduced square wave signal input by the pulse detection reduction circuit and the first narrow pulse signal input by the first pulse generation circuit, converts the first narrow pulse signal into a triangular wave signal, and converts the first narrow pulse signal into a triangular wave signal, and converts the first narrow pulse signal into a triangular wave signal. After restoring the duty cycle of the square wave signal and adjusting the decreasing slope of the triangular wave signal, the triangular wave signal is output to the clock signal shaping circuit;

(3) The clock signal shaping circuit receives the triangular wave signal input by the capacitor discharge current adjustment circuit, shapes the triangular wave adjustment signal to generate a corresponding third narrow pulse signal, and outputs it to the pulse detection and restoration circuit;

(4) The pulse detection and restoration circuit receives the first narrow pulse signal input from the first pulse generation circuit and the third narrow pulse signal input from the clock signal shaping circuit. According to the first narrow pulse signal and the third narrow pulse The signal is generated to restore the square wave signal and output to the capacitor discharge current adjustment circuit and external circuit respectively.

(5) Repeat steps (1) to (4) until the duty cycle of the restored square wave signal output by the pulse detection and restoration circuit is 1:1.

Compared with the prior art, the present invention has the following beneficial effects:

(1) The invention has a wide calibration range, low jitter and high precision clock signal duty cycle stabilizer circuit. Compared with other clock signal duty cycle adjustment circuits, it has a wide calibration range and can adjust the clock signal duty cycle between 20% and 80%. The original clock signal within the range is adjusted to a clock signal with a stable duty cycle;

(2) The invention has a wide calibration range, low jitter and high precision clock signal ratio stabilizer circuit, and the output clock signal can achieve low jitter. The clock jitter is about 50fs, ensuring the dynamic characteristics of the converter;

(3) The wide calibration range, low jitter and high precision clock ratio stabilizer circuit of the present invention can still ensure the high accuracy of the clock signal while ensuring the wide calibration range and low clock jitter. The clock output signal duty after adjustment by the circuit The ratio can reach 49%-51%;

(4) The wide calibration range, low jitter and high-precision clock ratio stabilizer circuit of the present invention adjusts the clock signal duty ratio through the capacitor discharge current, which can meet the input clock signal frequency up to 3GHz.

Description of the drawings

Figure 1 is an overall structural diagram of the clock ratio stabilizer circuit of the present invention;

Figure 2 is an overall circuit diagram of the clock ratio stabilizer circuit of the present invention;

Figure 3 is a circuit diagram of the amplifier in the capacitor discharge current adjustment circuit of the present invention;

Figure 4 is a diagram of the triangular wave adjustment circuit in the capacitor discharge current adjustment circuit of the present invention;

Figure 5(a) is a diagram of a triangular wave adjustment circuit of the present invention, and Figure 5(b) is a schematic diagram of a triangular wave signal generated by the triangular wave adjustment circuit of the present invention that advances the phase of a narrow pulse signal;

Figure 6(a) is a diagram of the triangular wave adjustment circuit of the present invention, and Figure 6(b) is a schematic diagram of the triangular wave signal generated by the triangular wave adjustment circuit of the present invention delaying the phase of the narrow pulse signal;

Figure 7 is a structural diagram of the clock signal shaping circuit of the present invention;

Figure 8 is a schematic diagram of the signal shaping process of the clock signal shaping circuit of the present invention;

Figure 9 is a schematic diagram of the signal restoration process of the clock detection and restoration circuit of the present invention.

Detailed ways

By describing the present invention in detail below, the features and advantages of the present invention will become clearer and clearer with these descriptions.

The word "exemplary" as used herein means "serving as an example, example, or illustrative." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or superior to other embodiments. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

High-speed and high-precision pipeline-level A/D converters require a low-jitter duty cycle and stable clock signal to ensure the normal operation of the A/D converter and improve the dynamic characteristics of the A/D converter. The present invention provides a wide calibration range, low jitter, and high-precision clock ratio stabilizer circuit for high-speed and high-precision pipeline A/D converters of more than 14 bits, which can be used to adjust the external input clock duty cycle and reduce clock jitter. , to meet the clock requirements of the converter core and improve the overall performance of the A/D converter.

The technical solution of the present invention is: a wide calibration range, low jitter and high-precision clock ratio stabilizer circuit, including a pulse generation circuit, a buffer module, a capacitor discharge current adjustment circuit, a clock signal shaping circuit; and a pulse detection and restoration circuit.

The first pulse generation circuit is used to receive a clock signal and detect the duty cycle of the clock signal and generate a corresponding narrow pulse signal;

The buffer module transmits the square wave signal generated by the pulse detection and reduction circuit to the capacitor discharge current adjustment circuit;

Capacitor discharge current adjustment circuit, the capacitor discharge current adjustment circuit receives the restored square wave signal input by the pulse detection and restoration circuit, generates a triangle wave signal according to the duty cycle of the restored square wave signal, and outputs it to the clock signal shaping circuit;

The clock signal shaping circuit receives the triangular wave signal input by the capacitor discharge current adjustment circuit, shapes the triangular wave signal through the Schmitt trigger, and converts the square wave generated after shaping into a narrow pulse signal and outputs it to the pulse detection and restoration circuit;

The pulse detection and restoration circuit detects the narrow pulse signal of the clock signal shaping circuit and the first pulse generation circuit, generates a restored square wave signal, and outputs it to the capacitor discharge current adjustment circuit through the buffer module, and finally restores it to a pulse signal with a duty cycle of 1:1. Restore the square wave clock signal.

Further, the first pulse generation circuit is connected to the original clock signal. The original clock signal enters the pulse generation circuit through an inverter to generate a corresponding narrow pulse circuit, all the way to the capacitor discharge current adjustment circuit, and all the way to the pulse detection circuit. Restore the circuit.

Further, the capacitor discharge current adjustment circuit includes an amplifier circuit and a triangle wave adjustment circuit; the main body of the amplifier circuit is an amplifier and a charging and discharging capacitor, and the superposition and extraction process of charges during the charging and discharging process of the capacitor is used to adjust the input to the triangle wave adjusting circuit Gate voltage; the increase or decrease in the gate voltage of the triangular wave adjustment circuit can determine the discharge current of the inverter through the current mirror, thereby adjusting the slope of the triangle wave signal decline, thereby adjusting the duty cycle of the clock signal.

Further, the clock signal shaping circuit includes a Schmitt trigger and a second pulse generating circuit. The triangular wave signal is shaped into a square wave by the Schmitt trigger. Finally, the narrow pulse signal is generated by the second pulse generating circuit and is input to the pulse signal. Detection and recovery circuit.

Further, the pulse detection and restoration circuit detects the narrow pulse signal of the clock signal shaping circuit and the first pulse generation circuit, and finally generates a clock signal with a duty cycle of 1:1.

Further, a clock signal adjustment method is implemented using a wide calibration range, low jitter, and high-precision clock signal ratio stabilizer circuit. The signal adjustment process includes the following steps:

S1, the external clock signal enters the pulse generation circuit through the inverter to generate a corresponding narrow pulse circuit, all the way to the capacitor discharge current adjustment circuit, and all the way to the pulse detection and restoration circuit;

S2, the restored square wave signal generated by the pulse detection and restoration circuit enters the capacitor discharge current adjustment circuit through the buffer module, as shown in Figure 2. According to the virtual short principle of the op amp, the voltage at the output terminal 4 of the first pulse generation circuit is 0.9V. , the voltage at the inverting input terminal 3 of the differential amplifier is a square wave signal. When the voltage at the inverting input terminal 3 of the differential amplifier is 1.8V, the capacitor C1 is charged. When the voltage at 3 points is 0V, the charge is extracted from the capacitor C1. If the clock duty cycle If it is not 1:1, then the charge superimposed during the charging process and the charge extracted during the discharging process are not consistent, and the voltage at the output terminal 5 of the differential amplifier increases or decreases. As shown in Figure 5 and Figure 6, the voltage at the output terminal 5 of the differential amplifier passes through The current mirror structure determines the discharge current of the inverter in the triangle wave regulation circuit. Because the capacitor is charged and discharged through the inverter, the charging current is very large, and the discharge current is constant and adjustable. When the output terminal 5 is high level, the capacitor discharges As the current increases, the falling edge slope of the triangle wave circuit becomes steeper, causing the narrow pulse signal to advance. Similarly, when the output terminal 5 is low level, the capacitor discharge current becomes smaller, and the falling edge slope of the triangle wave circuit becomes slower, causing the narrow pulse signal to delay.

S3, the triangular wave signal enters the clock signal shaping circuit, is shaped by the Schmitt trigger, and the corresponding narrow pulse signal is generated by the narrow pulse signal generation circuit and enters the pulse detection and restoration circuit;

S4, two narrow pulse signals enter the pulse detection and restoration circuit. The function of this circuit is: when the second input terminal 1 of the second NAND gate and the first input terminal 8 of the first NAND gate are both set to 1, the second The output of the output terminal 9 of the NAND gate and the output terminal 10 of the first NAND gate remains unchanged, and the output of the pulse detection and restoration circuit remains unchanged; and when a low-level pulse comes from the first input terminal 8 of the first NAND gate When , the output terminal 9 of the second NAND gate and the output terminal 10 of the first NAND gate output 0 and 1 respectively, and the pulse detection recovery circuit outputs a high level. When the second input terminal 1 of the second NAND gate When a low-level pulse comes, the output terminal 9 of the second NAND gate and the output terminal 10 of the first NAND gate output 1 and 0 respectively, and the pulse detection and restoration circuit outputs a low level. After the two narrow pulse signals enter the pulse detection and restoration circuit, the detection and restoration circuit will restore the clock signal and enter the capacitor discharge current adjustment circuit through the buffer module for further adjustment;

Repeat S1, S2, S3, and S4 to finally generate a clock signal with a duty cycle of 1:1.

Example 1

The overall structure diagram of the circuit structure of the present invention is shown in Figure 1. The circuit includes a pulse signal generation circuit, a pulse signal detection and restoration circuit, a buffer module, a capacitor discharge current adjustment circuit, and a clock signal shaping circuit.

In this embodiment, the first pulse signal generation circuit and the second pulse signal generation circuit included in the clock signal shaping circuit are respectively used to receive the original clock signal and the square wave signal after preliminary shaping, and generate the corresponding narrow pulse signal into the to the pulse detection restoration circuit.

As shown in Figure 2, after the two narrow pulse signals enter the pulse detection and restoration circuit, the detection and restoration circuit will restore the clock signal and enter the capacitor discharge current adjustment circuit through the buffer module for further adjustment. The specific process is: the pulse detection and restoration circuit consists of two The NAND gate is configured. When the second input terminal 1 of the second NAND gate and the first input terminal 8 of the first NAND gate are both set to 1, the output terminal 9 of the second NAND gate and the first NAND gate The output of the output terminal 10 remains unchanged, and the output of the pulse detection and restoration circuit remains unchanged; and when a low-level pulse comes from the first input terminal 8 of the first NAND gate, the output terminal 9 of the second NAND gate and the first The output terminal 10 of the NAND gate outputs 0 and 1 respectively, and the pulse detection and restoration circuit outputs a high level. When a low-level pulse comes from the second input terminal 1 of the second NAND gate, the second NAND gate The outputs of the output terminal 9 and the output terminal 10 of the first NAND gate are 1 and 0 respectively, and the pulse detection and restoration circuit outputs a low level.

The capacitor discharge current adjustment circuit is mainly composed of an amplifier circuit and a triangle wave adjustment circuit. The amplifier circuit consists of a differential amplifier and a capacitor, as shown in Figure 2. According to the virtual short principle of the operational amplifier, the voltage at the input terminal 4 of the differential amplifier is 0.9V. The voltage at input terminal 3 of the differential amplifier is a square wave signal. When the voltage at input terminal 3 of the differential amplifier is 1.8V, the capacitor C1 is charged. When the voltage at point 3 is 0V, the charge is extracted from the capacitor C1. If the clock duty cycle is not 1: 1, then the charge superimposed during the charging process and the charge extracted during the discharging process are not consistent, and the voltage at the output terminal 5 of the differential amplifier increases or decreases.

The specific circuit of the differential amplifier circuit is shown in Figure 3. NMOS M9 and M10 are amplifier tubes of the differential amplifier circuit. The gates of M9 and M10 are the input terminals of the narrow pulse signal and the reference voltage generated by the pulse detection unit respectively. R5 is the adjustable resistor. , the drains of M9 and M10 are connected to the drains of PMOS tubes M7 and M8. M7 and M8 are current source loads. The sources of NMOS M9 and M10 are connected to the drains of M17. M17 provides current bias for the amplifier. The external reference current PIBI enters the NMOS tube M0. The source of M0 is connected to the drain of M1 through R1. M1 is connected to the gate of M2. M3 is connected to the gate of M4. M1, M2, M3, and M4 form a current mirror structure and are NMOS tubes. M17, M18, M19, M22 provide gate voltage. The drain of M2 is connected to the drain of PMOS tube M5 through R2. The gate of M5 is connected to the gates of M13, M14 and M16 respectively. The gate of M6 is connected to the gates of M11, M12 and M15 respectively. PMOS M13 and M14 , the drain of M16 is connected to the drain of NMOS M18, M19 and M22 respectively, and the source of NMOS M18 and M19 is connected to the drain of M20 and M21 respectively. One end of the capacitor C3 is connected to the drain of M22 through the resistor R4, and the other end is connected to the gate of M23. The output signal is fed back to the gate of the differential amplifier tube M9 through the capacitor C1.

As shown in Figure 4, the triangle wave adjustment circuit includes NMOS transistors M25~M27, PMOS transistors M24, M28 and capacitor C4, bias current source I1, the output of the differential amplifier circuit is connected to the gate of M24, the drain of M24 is connected to the drain of M25, and the drain of M25 The gate is connected to the gate of M26 to form a current mirror structure, the drain of M26 is connected to the source of M27, the drain of M27 is connected to the drain of M28, and the gates of M27 and M28 are also connected to each other to form an inverter structure. The pole input is a narrow pulse signal, and the drain output is connected to capacitor C4.

As shown in Figures 5 and 6, the voltage at the output terminal 5 of the differential amplifier determines the discharge current of the inverter, thereby adjusting the slope of the triangle wave signal (waveform 6 in Figure 8) generated in the triangle wave adjustment circuit. Then it enters the clock signal shaping circuit to advance or delay the phase of the narrow pulse signal. The shaping process is shown in Figure 7. The triangular wave signal passes through the inverter to charge and discharge the capacitor and Schmitt trigger shaping to generate a preliminary shaping signal. The square wave signal (waveform 7 in Figure 8) generates a narrow pulse signal through the pulse signal generation circuit. , that is, waveform 8 in Figure 8, enters the pulse detection and restoration circuit.

As shown in Figure 9, the second narrow pulse signal (waveform 1) and the shaped first narrow pulse signal (waveform 8) pass through the pulse detection and restoration circuit to generate a restored square wave (waveform 9), and so on, and finally Generate a low-jitter, high-precision clock signal with a 1:1 duty cycle.

The present invention has been described in detail above with reference to specific embodiments and exemplary examples. However, these descriptions should not be construed as limitations of the present invention. Those skilled in the art understand that without departing from the spirit and scope of the invention, various equivalent substitutions, modifications or improvements can be made to the technical solution and its implementation of the invention, and these all fall within the scope of the invention. The scope of protection of the present invention is determined by the appended claims.

Contents not described in detail in the specification of the present invention are well-known technologies to those skilled in the art.

Claims (10)

1. A wide-range, low-jitter, high-precision clock ratio stabilizer circuit, characterized by including a first pulse generation circuit, a capacitor discharge current adjustment circuit, a clock signal shaping circuit and a pulse detection and restoration circuit; The first pulse generation circuit receives the original clock signal and generates a narrow pulse signal according to the duty cycle of the original clock signal, outputs the first narrow pulse signal to the capacitor discharge current adjustment circuit, and outputs the second narrow pulse signal to the pulse detection and restoration circuit. circuit; The capacitor discharge current adjustment circuit receives the restored square wave signal input by the pulse detection and restoration circuit and the first narrow pulse signal input by the first pulse generating circuit, converts the first narrow pulse signal into a triangular wave signal, and restores the square wave signal according to the restored square wave signal. After the duty cycle of the signal adjusts the decreasing slope of the triangular wave signal, the triangular wave signal is output to the clock signal shaping circuit; The clock signal shaping circuit receives the triangular wave signal input by the capacitor discharge current adjustment circuit, shapes the triangular wave signal to generate a corresponding third narrow pulse signal, and outputs it to the pulse detection and restoration circuit; The pulse detection and restoration circuit receives the second narrow pulse signal input by the first pulse generating circuit and the third narrow pulse signal input by the clock signal shaping circuit, and generates restoration according to the second narrow pulse signal and the third narrow pulse signal. Square wave signals are output to the capacitor discharge current adjustment circuit and external circuit respectively. 2. A wide-range low-jitter high-precision clock ratio stabilizer circuit according to claim 1, characterized in that the wide-range low-jitter high-precision clock ratio stabilizer circuit further includes a buffer module, and the pulse The detection and restoration circuit outputs the restored square wave signal to the capacitor discharge current adjustment circuit through the buffer module. 3. A wide-range, low-jitter, high-precision clock ratio stabilizer circuit according to claim 1, characterized in that the capacitor discharge current adjustment circuit includes an amplifier circuit and a triangle wave adjustment circuit; The amplifier circuit receives the restored square wave signal generated by the pulse detection and restoration circuit, and adjusts the voltage signal output by the amplifier circuit to the triangle wave adjustment circuit according to the duty cycle of the restored square wave signal; the triangle wave adjustment circuit receives the first pulse input from the first pulse generation circuit. The narrow pulse signal is converted into a triangular wave signal, and the slope of the triangle wave signal is adjusted according to the voltage signal input by the amplifier circuit, and then the triangular wave signal is output to the clock signal shaping circuit. 4. A wide-range low-jitter high-precision clock ratio stabilizer circuit according to claim 3, characterized in that the amplifier circuit includes a differential amplifier and a capacitor C1, and the positive-phase input end of the differential amplifier is connected to a reference voltage. , the inverting input terminal is the input terminal of the restored square wave signal generated by the pulse detection and restoration circuit, and the capacitor C1 is connected to the inverting input terminal and the output terminal of the differential amplifier respectively; when the restored square wave signal is high level and low level, the capacitor C1 performs During charging and discharging, the voltage signal at the output end of the differential amplifier is adjusted according to the charge and discharge balance state of capacitor C1. 5. A wide-range low-jitter high-precision clock ratio stabilizer circuit according to claim 4, characterized in that the amplifier circuit includes NMOS transistors M0~M4, M9~M10 and M17~M23, and PMOS transistor M5 ~M8, M11~16, fixed resistors R1~R4, adjustable resistors R5, and capacitors C1~C3; M9 and M10 are the differential amplifier amplifier tubes in the amplifier circuit, M7 and M8 are current source loads, M17 provides current bias for the differential amplifier, M1, M2, M3 and M4 form a current mirror structure, and provide M17, M18, M19 and M22 Provide gate voltage; The gate of M9 is connected to the output of the pulse detection reduction circuit through R3, the gate of M10 is connected to the reference voltage through the adjustable resistor R5, the drains of M9 and M10 are connected to the drains of M7 and M8 respectively, the sources of M9 and M10 are connected to the drain of M17, M0 The drain is the external reference current PIBI input terminal. The source of M0 is connected to the drain of M1 through R1. The gate of M1 is connected to the gate of M2. The gate of M3 is connected to the gate of M4. The drain of M2 is connected to the drain of M5 and the gate of M5 through R2. They are connected to the M13 gate, M14 gate and M16 gate respectively. The M6 gate is connected to the M11 gate, M12 gate and M15 gate respectively. The M13 drain, M14 drain and M16 drain are connected to the M18 drain and M16 drain respectively. The drain of M19 is connected to the drain of M22. The source of M18 and the source of M19 are connected to the drain of M20 and the drain of M21 respectively. One end of capacitor C2 is connected to the gate of M9 and the other end is grounded. One end of capacitor C3 is connected to the drain of M22 through resistor R4. The other end is connected to the gate of M23, the drain of M22 and the drain of M16 are the output ends of the amplifier circuit, one end of the capacitor C1 is connected to the output end of the capacitor discharge adjustment circuit, and the other end is connected to the gate of M9. 6. A wide-range low-jitter high-precision clock ratio stabilizer circuit according to claim 3, characterized in that the triangle wave adjustment circuit includes NMOS transistors M25~M27, PMOS transistors M24, M28 and capacitor C4; amplifier The circuit output is connected to the gate of M24, the bias current source I1 is connected to the drain of M24 and the drain of M25, the gate of M25 is connected to the gate of M26 to form a current mirror structure, the drain of M26 is connected to the source of M27, and the drain of M27 is connected to the drain of M28. poles are connected, and at the same time, the gates of M27 and M28 are connected to form an inverter structure. The gate inputs of M27 and M28 are the first narrow pulse signal, and the drain outputs of M27 and M28 are connected to the capacitor C4. 7. A wide-range, low-jitter, high-precision clock ratio stabilizer circuit according to claim 1, characterized in that the clock signal shaping circuit includes a Schmitt trigger and a second pulse generation circuit, and the clock signal shaping circuit The Mitter trigger receives the triangular wave signal input from the capacitor discharge current regulating circuit and shapes the triangular wave regulating signal into a square wave. The second pulse generating circuit converts the square wave signal into a narrow pulse signal. 8. A wide-range, low-jitter, high-precision clock ratio stabilizer circuit according to claim 1, characterized in that the pulse detection and restoration circuit generates a restored square wave based on the second narrow pulse signal and the third narrow pulse signal. The specific method of signal is: When the second narrow pulse signal and the third narrow pulse signal are both high level, the output of the pulse detection and restoration circuit remains unchanged; when the second narrow pulse signal is low level, the third narrow pulse signal is high level , the pulse detection and restoration circuit outputs a low level; when the second narrow pulse signal is at a high level and the third narrow pulse signal is at a low level, the pulse detection and restoration circuit outputs a high level. 9. A wide-range, low-jitter, high-precision clock ratio stabilizer circuit according to claim 1, characterized in that the pulse detection recovery circuit includes a first NAND gate and a second NAND gate; the first NAND gate The first input terminal is connected to the output terminal of the clock signal shaping circuit, the second input terminal is connected to the output terminal of the second NAND gate, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the second input terminal is connected to The output terminal of the first pulse generating circuit, the output terminals of the first NAND gate and the second NAND gate are simultaneously the output terminals of the pulse detection and restoration circuit. 10. A wide-range, low-jitter, high-precision clock signal adjustment method, characterized in that it is implemented using a wide-range, low-jitter, high-precision clock ratio stabilizer circuit according to any one of claims 1 to 9, including the following steps : (1) The first pulse generation circuit receives the original clock signal and generates a narrow pulse signal according to the duty cycle of the original clock signal, outputs the first narrow pulse signal to the capacitor discharge current adjustment circuit, and outputs the second narrow pulse signal to Pulse detection recovery circuit; (2) The capacitor discharge current adjustment circuit receives the reduced square wave signal input from the pulse detection reduction circuit and the first narrow pulse signal input from the first pulse generation circuit, converts the first narrow pulse signal into a triangle wave signal, and converts the first narrow pulse signal into a triangular wave signal. After restoring the duty cycle of the square wave signal and adjusting the decreasing slope of the triangular wave signal, the triangular wave signal is output to the clock signal shaping circuit; (3) The clock signal shaping circuit receives the triangular wave signal input by the capacitor discharge current adjustment circuit, shapes the triangular wave adjustment signal to generate a corresponding third narrow pulse signal, and outputs it to the pulse detection and restoration circuit; (4) The pulse detection and restoration circuit receives the second narrow pulse signal input from the first pulse generation circuit and the third narrow pulse signal input from the clock signal shaping circuit. According to the second narrow pulse signal and the third narrow pulse The signal generates and restores the square wave signal and outputs it to the capacitor discharge current adjustment circuit and external circuit respectively; (5) Repeat steps (1) to (4) until the duty cycle of the restored square wave signal output by the pulse detection and restoration circuit is 1:1.