CN114156946B - Parallel inverter power balance control method based on common-mode voltage injection - Google Patents

Abstract

The invention discloses a parallel inverter power balance control method based on common mode voltage injection. The method injects an intrinsic and an additional common-mode voltage component into the main inverter reference output voltage, wherein the additional common-mode voltage component comprises the main inverter reference output current signal. The N slave inverters on the slave inverter side are connected in parallel, and the N slave inverters are controlled as follows: and performing proportional-integral-multimode resonance control on the zero sequence component of the output current to obtain an additional common-mode voltage component of the slave inverter, and extracting a reference output current signal of the master inverter from the zero sequence current controller to serve as a reference output current of the slave inverter. The invention can eliminate the communication wires required by the traditional master-slave control, reduce the structural complexity of the parallel inverter system, ensure that the system automatically realizes power balance, has good dynamic and steady-state performances, and is beneficial to improving the running performance of the parallel inverter.

Description

A Power Balance Control Method for Parallel Inverters Based on Common Mode Voltage Injection

technical field

The invention belongs to the technical field of power electronics, in particular to a control method for parallel inverters based on common-mode voltage injection.

Background technique

With the rapid development of various new energy power generation technologies such as photovoltaic power generation and wind power generation, renewable energy will gradually become the main force in the field of power generation. Most of the current renewable energy generates DC power, which needs to be integrated into the grid through an inverter link. Therefore, the inverter plays an irreplaceable role.

At present, the power required by electrical equipment is increasing, and a single inverter can no longer meet the requirements. Simply increasing the power of a single inverter will not only bring about problems such as increased manufacturing costs and increased volume, but also a single inverter. Inverter faults also have a great impact on the continuous operation of the overall system, so a parallel inverter system as shown in Figure 1 is produced. Parallel inverters can not only effectively increase the power to meet the requirements of high-power electrical equipment, but also enhance the flexibility of the entire system, making the system safer and more reliable during operation. With the continuous development and improvement of control theory, the master-slave control mode based on communication and the droop control mode without communication are derived in the control of parallel inverter system. The principle of traditional master-slave control is shown in Figure 2. The control signal generated by the master inverter is used as the given signal of the slave inverter to achieve load balancing. This control method can make the parallel inverter system obtain better dynamic And steady-state performance, but the existence of communication lines makes the structure of the whole system more complicated, and there is also equipment coupling phenomenon, which is not conducive to the development of parallel inverters. Although there is no communication line in the traditional droop control method, the automatic power balance effect is poor, and the dynamic and steady-state performance is poor.

Contents of the invention

The purpose of the present invention is to provide a parallel inverter power equalization control method based on common-mode voltage injection, which does not require communication lines, and only injects common-mode voltage to realize information transmission.

The purpose of the present invention can be achieved through the following technical solutions:

S1: according to the actual value i _mo of the output current of the main inverter, perform closed-loop control on the active component i _mod and the reactive component i _moq of i _mo respectively, and obtain the output voltage reference value u _mo ^* of the main inverter;

S2: Calculate the intrinsic common-mode voltage component u _moc1 of the main inverter from u _mo ^* , and construct the additional common-mode voltage component u _moc2 of the main inverter with reference to the active and reactive current signals;

S3: superimpose u _moc1 and u _moc2 obtained in step S2 on u _mo ^* , generate a control signal of the main inverter through sinusoidal pulse width modulation, and realize control of the main inverter;

S4: use the zero-sequence current controller to perform closed-loop control on the zero-sequence current generated by the n-th slave inverter, and obtain the additional common-mode voltage component u _sonc2 of the n-th slave inverter;

S5: Obtain the reference active and reactive current signals of the main inverter from the zero-sequence current controller, as the active and reactive components of the reference output current of the nth slave inverter;

S6: According to the actual output current i _son of the nth slave inverter, perform closed-loop control on the active component i _sond and the reactive component i _sonq of i _son respectively, and obtain the output voltage reference value u _son ^* of the slave inverter;

_S7 ^: Calculate the intrinsic common mode voltage component u _sonc1 of the nth inverter from uson*, superimpose the obtained _usonc1 and _usonc2 on _uson ^* , and control the nth inverter by generating a control signal through sinusoidal pulse width modulation from the inverter.

Further, the method for calculating the intrinsic and additional common-mode voltage components injected by the main inverter in S2 specifically includes:

S2.1: Calculate the intrinsic common mode voltage component u _moc1 of the main inverter by the following formula:

where max and min are the operators for calculating the maximum and minimum values of the main inverter reference output voltage reference value u _mo ^* respectively;

S2.2: Calculate the additional common-mode voltage component u _moc2 of the main inverter by the following formula:

u _moc2 ＝i _mod ^* sin(ω ₁ t)+i _moq ^* sin(ω ₂ t) (2)

Among them, i _mod ^* and i _moq ^* are the reference output active current and reactive current of the main inverter respectively, ω ₁ and ω ₂ are two different frequencies for transmitting information, and t is time.

Further, the specific method of controlling the main inverter in said S3 is:

Add the obtained main inverter's intrinsic common-mode voltage component u _moc1 , additional common-mode voltage component u _moc2 and reference output voltage u _mo ^* to obtain the synthesized voltage vector u _mo ^** , and use sinusoidal pulse width modulation to synthesize The voltage vector u _mo ^** is modulated to obtain the control signal of the main inverter to realize the control of the main inverter.

Further, in said S4, the method for obtaining the nth additional common-mode voltage component u _sonc2 from the inverter specifically includes:

S4.1: Calculate the zero-sequence current actual value i _son-0 of the nth slave inverter by the following formula:

Among them, _isona , _isonb and _isonc are the three-phase output currents of the nth slave inverter respectively;

S4.2: Calculate the difference between the actual value ison _-0 of the zero-sequence current of the nth slave inverter and its reference value, and set the calculated result to e _ison-0 ;

S4.3: The zero-sequence current controller G _0n (s) adjusts the obtained e _ison-0 to obtain the additional common-mode voltage component u _sonc2 of the nth slave inverter, and the zero-sequence current controller G _0n (s ) includes 5 sub-controllers, whose expressions are as follows:

G _0n (s) = G _0n1 (s) + G _0n2 (s) + G _0n3 (s) + G _0n4 (s) + G _0n5 (s) (4)

in:

In formula (5), G _0n1 (s) and G _0n2 (s) are the proportional and integral controllers respectively, k _P and k _I are the corresponding controller coefficients respectively; G _0n3 (s) is the resonance for suppressing the third harmonic controller, k _R is its coefficient, ω _g is the grid voltage frequency; G _0n4 (s) and G _0n5 (s) are resonant controllers that suppress the zero-sequence current generated by the additional common-mode voltage of the main inverter, k ₁ and k ₂ are the corresponding controller coefficients, s is the differential link.

Further, in said S5, the method for obtaining the reference active component i _sond ^* and the reference reactive component i _sonq ^* of the output current of the nth inverter from the inverter specifically includes:

S5.1: According to the adjustment result of the zero-sequence current controller G _0n (s), obtain the signal containing the reference output current information of the main inverter from the results of G _0n4 (s) and G _0n5 (s) respectively;

S5.2: square each component in the signal obtained in S5.1, and filter out the double frequency component generated by the square with the corresponding double frequency notch filter;

S5.3: Expand the filtering result of the notch filter obtained in S5.2 to 2 times, and then carry out the square root to obtain the reference output active current i _sond ^* and reactive current i _sonq ^* of the nth slave inverter, where i _sond ^* and i _sonq ^* are equal to i _mod ^* and i _moq ^* respectively.

Further, in said S7, the method for controlling the nth slave inverter specifically includes:

S7.1: According to the obtained u _son ^* , calculate the intrinsic voltage component u _sonc1 of the nth slave inverter by the following formula:

where max and min are operators for calculating the maximum and minimum values of _uson ^* , respectively;

S7.2: superimpose the intrinsic common-mode voltage component _usonc1 of the n-th slave inverter, the additional common-mode voltage component _usonc2 and the reference output voltage _uson ^* to obtain a composite voltage vector _uson ^** ;

S7.3: Use sinusoidal pulse width modulation to modulate the synthesized voltage vector _uson ^** to obtain the control signal of the nth slave inverter, realize the control of the nth slave inverter, and finally realize the control of the entire parallel Control of the inverter system.

After adopting the above scheme, the present invention has the following beneficial effects:

1. Effectively ensure that the power of the parallel inverter system is automatically balanced between the master inverter and the slave inverter;

2. It only needs to improve and add the controller to eliminate the complex communication lines required for master-slave control, the structure and hardware costs of the whole system are reduced, and there is no equipment coupling phenomenon at the same time.

Description of drawings

Fig. 1 is the topological structure diagram of the parallel inverter of the present invention;

Fig. 2 is the basic schematic diagram of traditional master-slave control of the present invention;

Fig. 3 is a block diagram of the system control method proposed by the present invention;

Fig. 4 is the control block diagram of main inverter in the embodiment of the present invention;

Fig. 5 is a schematic diagram of the present invention calculating the additional common-mode voltage component u _mo (u _son ) of the master inverter (slave inverter);

Fig. 6 is a control block diagram of slave inverter #1 in a specific embodiment of the present invention;

Fig. 7 is the zero-sequence current controller G _0n (s) from inverter #1 in the specific embodiment of the present invention;

Fig. 8 is a schematic diagram of obtaining reference active output current i _so1d ^* and reference reactive output current i _so1q ^* from inverter #1 in a specific embodiment of the present invention;

Fig. 9 is the output current simulation result using the proposed control method on the parallel inverter.

Detailed ways

For the various steps of the method for controlling parallel inverters based on common-mode voltage injection proposed by the present invention, the following will combine Figure 3-Figure 8 in the embodiment of the present invention to use two inverters (master inverter + slave inverter Inverter #1) parallel connection is taken as an example, and the control method is described in detail. Fig. 9 is the output current simulation result of two inverters,

According to the main inverter control block diagram shown in Figure 4, the actual grid voltage u _g is obtained by the voltage measuring device, and the actual output current i _mo of the main inverter and the actual output current of the slave inverter #1 are obtained by the current measuring device i _so1 .

According to the obtained u _g and i _mo , calculate the phase angle difference θ between them, and calculate the active component i _mod and reactive component i _moq of i _mo by formula (1):

According to the reference active component i _mod ^* and reactive component i _moq ^* of the given main inverter output current, calculate the errors e _imod and e _imoq of the actual value and reference value of i _mod and i _moq respectively, and use the current PI controller G _m (s) adjusts e _imod and e _imoq respectively, combined with the grid voltage u _g , obtains the reference output voltage u _mo ^* of the main inverter through inverse PARK transformation.

According to the schematic diagram shown in Figure 5, the intrinsic common-mode voltage component u _moc1 of the main inverter is calculated by combining formula (2):

Then u _moc1 has three different values u _moa ^* /2, u _mob ^* /2 and u _moc ^* /2 in one cycle;

Assuming ω ₁ and ω ₂ are 100Hz and 200Hz respectively, calculate the additional common-mode voltage component u _moc2 of different frequencies injected by the main inverter according to formula (3):

u _moc2 ＝i _mod ^* sin(200πt)+i _moq ^* sin(400πt)(3)

Superimpose the obtained u _moc1 and u _moc2 into u _mo ^* to obtain the composite voltage component u _mo ^** , modulate u _mo ^** through sinusoidal pulse width modulation to obtain the control signal of the main inverter, and realize the control of the main inverter Inverter control.

The control block diagram of slave inverter #1 is shown in Figure 6. According to the measured actual output current i _so1 of slave inverter #1, the actual zero-sequence current value i _so1 of slave inverter #1 is calculated by formula (4) _-0 :

Calculate the error e _iso1-0 between i _so1-0 and _iso1-0 ^* according to the zero-sequence current reference value 0 from inverter #1, and use the zero-sequence current controller G ₀₁ (s) shown in Figure 7 The error e _io1-0 is adjusted to obtain an additional common-mode voltage component u _so1c2 from inverter #1.

According to the principle that the circulating current of parallel inverters is zero, the signal containing the reference output current information of the main inverter is obtained from the results of G ₀₁₄ (s) and G ₀₁₅ (s) in the zero-sequence current controller shown in Figure 7; according to The schematic diagram shown in Figure 8, square the i _mod ^* sin(200πt) and i _moq ^* sin(400πt) contained in the signal to obtain the result shown in formula (5), using two notches with frequencies of 400π and 800π respectively Filter out the frequency components of 400π and 800π in the result of formula (5), expand the filtered result to 2 times and take the square root, and get the output reference active current i _so1d ^* and reference reactive current i from inverter #1 _so1q ^* , where i _so1d ^* and i _so1q ^* are equal to i _mod ^* and i _moq ^* respectively.

According to the measured actual output current i _so1 of inverter #1 and the actual voltage u _g of the grid, the power factor angle θ ₁ between them is calculated, and the active component i _so1d and reactive component of _iso1 are calculated by formula (6) i _so1q :

Calculate the difference _e iso1d and e iso1q between i _so1d ^* and i _so1d , i _so1q ^* and i _so1q , use the current PI controller G _s1 (s) to control e _iso1d and _{e iso1q respectively} , combined with the grid voltage u _g , the reference output voltage u _so1 ^* from inverter #1 is obtained by inverse PARK transformation.

According to the schematic diagram shown in Figure 5, the intrinsic common-mode voltage component u _so1c1 of slave inverter #1 is calculated by combining formula (7):

Then u _so1c2 also has three different values u _so1a ^* /2, u _so1b ^* /2 and u _so1c ^* /2 in one cycle;

Superimpose the obtained u _so1c1 and u _so1c2 into u _so1 ^* to obtain the synthesized voltage component u _so1 ^** , and modulate u _so1 ^** through sinusoidal pulse width modulation to obtain the control signal from inverter #1 to realize the The control of the slave inverter #1 finally realizes the control of the parallel inverter system composed of the master inverter and the slave inverter #1.

It can be seen from FIG. 9 that both the master inverter and the slave inverter #1 can achieve output current balance, and then realize automatic power balance.

The above embodiments are only to illustrate the technical ideas of the present invention, and cannot limit the scope of protection of the present invention with this. Any changes made on the basis of technical solutions according to the technical ideas proposed in the present invention all fall within the scope of protection of the present invention. Inside.

Claims (3)

1. The parallel inverter power balance control method based on common mode voltage injection is characterized in that a parallel system is formed by a master inverter and N slave inverters, the structure and the control method of the N slave inverters are the same, and the control method of the master inverter and the slave inverters comprises the following steps:

s1: according to the actual value i of the output current of the main inverter _mo For i _mo Active component i of (2) _mod And reactive component i _moq Respectively performing closed-loop control to obtain a reference value u of the output voltage of the main inverter _mo ^* ；

S2: from u _mo ^* Calculating an intrinsic common-mode voltage component u of a main inverter _moc1 Constructing an additional common mode voltage component u of the main inverter by the main inverter with reference to the active and reactive current signals _moc2 ；

S3: in u _mo ^* U obtained in step S2 of upper superposition _moc1 And u _moc2 Generating a control signal of the main inverter through sine pulse width modulation, and controlling the main inverter;

s4: closed-loop control is carried out on zero-sequence current generated by the nth slave inverter by using a zero-sequence current controller to obtain an additional common-mode voltage component u of the nth slave inverter _sonc2 ；

S5: obtaining reference active and reactive current signals of the main inverter from the zero sequence current controller as active and reactive components of reference output current of the nth slave inverter;

s6: according to the actual output current i of the nth slave inverter _son For i _son Active component i of (2) _sond And reactive component i _sonq Respectively performing closed-loop control to obtain the output voltage reference value u of the slave inverter _son ^* ；

S7: from u _son ^* Calculating an intrinsic common-mode voltage component u of the nth slave inverter _sonc1 In u _son ^* Superimposed on the resulting u _sonc1 And u _sonc2 Generating a control signal through sine pulse width modulation to control an nth slave inverter;

in S2, the method for calculating the intrinsic and additional common-mode voltage components injected by the main inverter is:

s2.1: the intrinsic common-mode voltage component u of the main inverter is calculated by _moc1 ：

Wherein max and min are respectively calculated reference output voltage reference value u of the main inverter _mo ^* Operators of maximum and minimum values;

s2.2: calculating an additional common mode voltage component u of the main inverter by _moc2 ：

u _moc2 ＝i _mod ^* sin(ω ₁ t)+i _moq ^* sin(ω ₂ t) (2)

Wherein i is _mod ^* And i _moq ^* The reference output active current and reactive current of the main inverter, omega ₁ And omega ₂ Two different frequencies for transmitting information, t is time;

in the S4, an additional common-mode voltage component u of the nth slave inverter is obtained _sonc2 The method of (1) is as follows:

s4.1: the actual value i of the zero sequence current of the nth slave inverter is calculated by the following method _son-0 ：

Wherein i is _sona 、i _sonb And i _sonc The n-th three-phase output current of the slave inverter;

s4.2: calculating the actual value i of the zero sequence current of the nth slave inverter _son-0 The difference from the reference value is calculated as e _ison-0 ；

S4.3: by zero sequence current controller G _0n (s) for the obtained e _ison-0 Adjusting to obtain additional common-mode voltage component u of the nth slave inverter _sonc2 Zero sequence current controller G _0n (s) including 5 sub-controllers, the expression of which is as follows:

G _0n (s)＝G _0n1 (s)+G _0n2 (s)+G _0n3 (s)+G _0n4 (s)+G _0n5 (s) (4)

wherein:

in the formula (5), G _0n1 (s) and G _0n2 (s) are proportional and integral controllers, k, respectively _P And k _I Respectively corresponding controller coefficients; g _0n3 (s) a resonant controller for suppressing third harmonic, k _R For its coefficient, omega _g Is the grid voltage frequency; g _0n4 (s) and G _0n5 (s) resonant controllers k for suppressing zero-sequence currents generated by additional common-mode voltages of the main inverter ₁ And k ₂ Respectively corresponding controller coefficients, and s is a differential link;

in the step 7, the method for controlling the nth slave inverter is as follows:

s7.1: according to the obtained u _son ^* The intrinsic voltage component u of the nth slave inverter is calculated by the following formula _sonc1 ：

Wherein max and min are calculated u respectively _son ^* Operators of maximum and minimum values;

s7.2: the n-th slave inverter is subjected to an intrinsic common-mode voltage component u _sonc1 Additional common-mode voltage component u _sonc2 And a reference output voltage u _son ^* The three are superimposed to obtain a composite voltage vector u _son ^** ；

S7.3: the sinusoidal pulse width modulation is adopted for synthesizing the voltage vector u _son ^** Modulating to obtain a control signal of the nth slave inverter, and controlling the nth slave inverter, so as to finally control the whole parallel inverter system.

2. The parallel inverter power balance control method based on common mode voltage injection as claimed in claim 1, wherein: the specific method in the step S3 is as follows:

the obtained intrinsic common-mode voltage component u of the main inverter _moc1 Additional common-mode voltage component u _moc2 And a reference output voltage u _mo ^* The three components are added to obtain a composite voltage vector u _mo ^** The sinusoidal pulse width modulation is adopted for synthesizing the voltage vector u _mo ^** Modulating to obtain a control signal of the main inverter, and controlling the main inverter.

3. The parallel inverter power balance control method based on common mode voltage injection as claimed in claim 2, wherein: in the step 5, the nth reference active component i of the output current from the inverter is obtained _sond ^* And reference reactive component i _sonq ^* The method of (1) is as follows:

s5.1: according to zero sequence current controller G _0n The adjustment results of(s) are respectively from G _0n4 (s) and G _0n5 Obtaining a signal containing primary inverter reference output current information from the result of(s);

s5.2: squaring each component in the signal obtained in the step S5.1 respectively, and filtering the square frequency doubling components by using corresponding frequency doubling wave traps respectively;

s5.3: expanding the filtering result of the wave trap obtained in the step S5.2 to 2 times, and then opening the square to obtain the nth active current i output from the reference of the inverter _sond ^* And reactive current i _sonq ^* Wherein i is _sond ^* And i _sonq ^* Respectively equal to i _mod ^* And i _moq ^* 。