CN114142852B - High-speed burst mode clock data recovery circuit suitable for PAM4 signal - Google Patents

Abstract

The invention discloses a high-speed burst mode clock data recovery circuit suitable for PAM4 signals, including: a sampling judgment circuit, a phase detection circuit, a majority voting circuit, an oversampling logic unit, a digital phase control module, a digital loop filter, Quadrature clock generation circuit and phase synthesis module; the oversampling logic unit controls the switching of the loop locking mode between the oversampling mode and the phase detection locking mode, oversamples the PAM4 data signal quantization result and outputs the control signal. Due to the addition of an oversampling locked loop, the invention quickly samples the initial coded sequence to determine a rough clock phase, cooperates with a locking mechanism with a smaller bandwidth in the locked loop of a binary phase detector, and realizes low-jitter reception. The sampling unit in the oversampling mode of the present invention will reuse the sampler originally used for edge sampling and part of the sampler for PAM4 decoding, without the need for additional sampling circuits, and reduces system power consumption while realizing fast loop locking.

Description

A High Speed Burst Mode Clock Data Recovery Circuit for PAM4 Signals

technical field

The invention belongs to the fields of optical communication and integrated circuits, and more specifically relates to a high-speed burst mode clock data recovery circuit suitable for PAM4 signals.

Background technique

A clock and data recovery circuit (CDR for short) plays a vital role in a serial communication system. In a high-speed serial communication system, only serial data is transmitted on the channel, and no clock signal is transmitted, and the data receiving end receives the data signal and performs clock recovery. The function of the clock data recovery circuit is to extract the clock from the data signal according to the reference clock, and then use the recovered clock to retime the received data to obtain a data reception result that meets the specification.

The use of the PAM4 signal increases the data rate, and the receiver performs simultaneous phase detection on the decoded three-way data signals, which improves the phase detection density. As shown in Figure 1, most PAM4 CDRs in the prior art are composed of a Bang Bang Phase Detector (BBPD for short) and a digital loop filter, as Changzhi Yu et al published in the journal IEEE Journal of Solid-State Circuits in 2020 architecture. However, in order to reduce the jitter of the recovered clock signal, it is usually necessary to set the loop bandwidth to be small to meet the requirements of the communication standard, which makes it take a long time for the system to stabilize. In PAM4 CDR in burst mode, however, a fast loop tracking response needs to be achieved.

In the non-return-to-zero code (None-Return-to-Zero) NRZ data format, a common method to achieve burst mode reception is Gated-VCO, which injects the input signal into the oscillator through a logic gate to achieve fast locking . Another common method is Time-to-Digital Converter, which converts the phase error into a digital signal and performs fast phase locking. Both of these methods require the use of logic gates for number crunching and are therefore only applicable to the NRZ format. One way to achieve fast loop tracking response is to use oversampling mode. However, for PAM4 data recovery in high-speed burst mode, a high-speed and relatively high-resolution ADC unit is required, which increases the complexity of circuit design and increases circuit power consumption.

Contents of the invention

Aiming at the defects of the prior art, the purpose of the present invention is to provide a high-speed burst mode clock data recovery circuit and receiver suitable for PAM4 signals, aiming to solve the complex circuit caused by the introduction of the ADC in the oversampling mode in the prior art. The problem of a substantial increase in speed and power consumption.

The present invention provides a high-speed burst mode clock data recovery circuit suitable for PAM4 signals, including: a sampling judgment circuit, a phase detection circuit, a majority voting circuit, an oversampling logic unit, a digital phase control module, a digital loop filter, Orthogonal clock generation circuit and phase synthesis module; the first input end of sampling judgment circuit is used to receive the PAM4 data signal of external input, and the second input end of described sampling judgment circuit is connected to the output end of described phase synthesis module, with It is used to digitally quantize the input level according to the set reference voltage and output the quantized result; the input terminal of the phase detection circuit is connected to the output terminal of the sampling decision circuit, and is used to receive the quantized data signal and the output signal of the phase synthesis module Clock signal, and according to the phase relationship between the two, generate the clock’s leading voltage signal and lagging voltage signal relative to the data signal; the input end of the majority voting circuit is connected to the output end of the phase detector circuit, which is used to connect the phase detector The output data of the output data is combined to output a unique clock with respect to the leading voltage signal and the lagging voltage signal of the data signal; the input end of the oversampling logic unit is connected to the output end of the sampling decision circuit for controlling the loop locking mode Switching between the oversampling mode and the phase detection and locking mode, the PAM4 data signal quantization result is oversampled and the control signal is output; the first input terminal of the digital phase control module is connected to the output terminal of the majority voting circuit, and the second The input end is connected to the output end of the oversampling logic unit, and is used to output digital logic signals according to the phase discrimination result output by the majority voter and the control signal; the input end of the digital loop filter is connected to the digital phase control The output terminal of the module is used to perform low-pass filtering processing on the digital logic signal; the quadrature clock generation circuit is used to receive an externally input reference clock signal, filter the external clock and generate two orthogonal clock signals ; The first input end of the phase synthesis module is connected to the output end of the digital loop filter, and the second input end of the phase synthesis module is connected to the output end of the quadrature clock generation circuit, for according to the The digital logic signal shifts the phases of the two quadrature clocks, and sends the phase-shifted clock signals to the sampling decision circuit and the phase detector.

Furthermore, the sampling decision circuit includes: a first sampler A, a second sampler B, a third sampler C, a fourth sampler D, a first D flip-flop DFF_A, a second D flip-flop DFF_B, a third D Flip-flop DFF_C, fourth D flip-flop DFF_D and four sets of two-stage inverters; the first input terminal of the first sampler A, the first input terminal of the second sampler B, the third sampler The first input terminal of the first sampler C and the first input terminal of the fourth sampler D are both used to connect external input signals, the second input terminal of the first sampler A is connected to the first reference voltage REF1, the The second input end of the second sampler B is connected to the second reference voltage REF2, the second input end of the third sampler C is connected to the third reference voltage REF3, and the second input end of the fourth sampler D is connected to the The second reference voltage REF2; the first input end of the first D flip-flop DFF_A is connected to the output end of the first sampler A, and the first input end of the second D flip-flop DFF_B is connected to the The output terminal of the second sampler B, the first input terminal of the third D flip-flop DFF_C is connected to the output terminal of the third sampler C, the first input terminal of the fourth D flip-flop DFF_D is connected to The output terminal of the fourth sampler D; the second input terminal of the first D flip-flop DFF_A, the second input terminal of the second D flip-flop DFF_B and the second input terminal of the third D flip-flop DFF_C The input ends are used to connect the data sampling clock, the output end of the fourth D flip-flop DFF_D is used to connect the edge sampling clock; the input ends of the first group of two-stage inverters are connected to the first D flip-flop DFF_A Output terminal, the output terminal of the first group of two-stage inverters is used to output data A; the input terminal of the second group of two-stage inverters is connected to the output terminal of the second D flip-flop DFF_B, the second group of two-stage inverters The output terminal of the inverter is used to output data B; the input terminal of the third group of two-stage inverters is connected to the output terminal of the third D flip-flop DFF_C, and the output terminal of the third group of two-stage inverters is used for Output data C; the input end of the fourth group of two-stage inverters is connected to the output end of the fourth D flip-flop DFF_D, and the output end of the fourth group of two-stage inverters is used to output edge A; wherein, the The first reference voltage REF1 is smaller than the second reference voltage REF2, and the second reference voltage REF2 is smaller than the third reference voltage REF3.

Further, the phase detection circuit includes: a Bang Bang phase detector; the Bang Bang phase detector includes an exclusive OR gate A and an exclusive OR gate B; the first input end of the exclusive OR gate A is connected to the fourth group of two The output end of the stage inverter, the second input end is connected to the output end of the second group of two-stage inverters, and the exclusive OR gate A outputs a clock advance signal for adjusting the clock phase and realizing phase locking; The first input end of the exclusive OR gate B is connected to the output end of the second group of two-stage inverters, the second input end is connected to the data of the previous sampling point, and the output of the exclusive OR gate B is used to adjust the clock phase And achieve phase-locked clock lag signal.

Furthermore, the oversampling logic unit includes: an oversampling control logic module, which is used to realize the phase locking logic in the oversampling mode, and judge whether it is in a state close to locking according to the phase result: if it is in a state close to locking, the oversampling control The logic module assigns the value of the internal register to the digital phase control module.

Further, the oversampling control logic module includes: a NOT gate, an OR gate, a NOR gate, an AND gate and a register; the input terminal of the NOT gate is connected with the third sampling signal Sample[2], and the output of the NOT gate The terminal is connected with the first input terminal of the OR gate, the second input terminal of the OR gate is connected with the second sampling signal Sample[1], the output terminal of the OR gate is connected with the first input terminal of the AND gate, The second input end of the AND gate is connected to the first sampling signal Sample[0], and the output end of the AND gate is connected to the first input end of the register for outputting a phase leading signal; the first NOR gate An input terminal is connected to the second sampling signal Sample[1], a second input terminal of the NOR gate is connected to the first sampling signal Sample[0], an output terminal of the NOR gate is connected to the The second input end of the register is connected to output a phase lag signal, and the register is used to output a phase control signal according to the phase lag signal and the phase lead signal.

Furthermore, the phase synthesis module includes: four groups of phase interpolation units; wherein, two groups of phase interpolation units are used to generate clocks with four phases of 0 degree, 90 degrees, 180 degrees and 270 degrees as data sampling clocks, which are respectively supplied to each Sampling channel; the other two sets of phase interpolation units are used to generate clocks with four phases of 45 degrees, 135 degrees, 225 degrees, and 315 degrees as edge sampling clocks.

The present invention also provides an oversampling logic control method based on the above-mentioned high-speed burst mode clock data recovery circuit, comprising the following steps:

(1) whether the three phase judgment signals of judging input are 110, if so, then control CDR to enter BBPD locking mode; Otherwise enter step (2);

(2) judge whether the three phase judgment signals of input are 111 or 011 or 001, if so, then control and reduce sampling phase and clock lag; If not, then enter step (3);

(3) Determine whether the three input phase judgment signals are 100 or 000, if so, control to increase the sampling phase, otherwise no phase operation is required and return to step (1).

The present invention also provides a PAM4 receiver. The PAM4 receiver includes: a clock data recovery circuit, a PAM4 decoding circuit and an analog combiner; output data; the PAM4 decoding circuit is used to decode the data A, data B, and data C output in the sampler into NRZ-coded binary codes MSB1 and LSB1; the analog combiner is used to convert 1/4 rate 4 MSB1, MSB2, MSB3, and MSB4 of four sampling channels are fused into one MSB in series; and LSB1, LSB2, LSB3, and LSB4 of four sampling channels will also be fused into one LSB in series; it is characterized in that the clock data recovery The circuit is the above-mentioned high-speed burst mode clock data recovery circuit.

In the existing BBPD loop locking scheme, Razavi et al. have proved that there is a direct correlation between the loop bandwidth and the locking time. If faster lock times are required, greater loop bandwidth is required. However, communication standards generally require that the CDR loop bandwidth should not be too large, so it is difficult to achieve fast locking through the traditional BBPD loop locking scheme. Through the above technical scheme conceived by the present invention, compared with the prior art, due to multiplexing the data sampling unit and changing the phase of the edge sampling, the oversampling locking mode is introduced on the basis of the BBPD loop locking mode, avoiding the existing There is a trade-off between loop bandwidth and phase locking time in the BBPD loop locking scheme, and fast phase locking can be achieved in the preamble stage (Preamble). At the same time, since the oversampling fast locked loop can be switched to the BBPD locked mode, the CDR circuit can maintain the advantages of low bandwidth in the prior art.

Description of drawings

FIG. 1 is a structural diagram of a PAM4 CDR system in the prior art.

FIG. 2 is a structural diagram of the PAM4 CDR system in the burst mode in the example of the present invention.

Fig. 3 is a specific circuit structure diagram of the sampling decision circuit and the phase detector in the example of the present invention.

Fig. 4 is a specific circuit structure diagram of the digital phase control module in the example of the present invention.

Fig. 5 is a specific circuit structure diagram of the digital loop filter in the example of the present invention.

Fig. 6 is a specific circuit structure diagram of the quadrature clock generation circuit in the example of the present invention.

Fig. 7 is a schematic diagram of the principle of low-power fast over-sampling in the example of the present invention.

Figure 8 is the result of the three sample data traditions in the case of loop lock.

FIG. 9 is the result of three sampled data in the case that the sampled signal leads the data.

Figure 10 is the result of three sampled data in the case of two sampled signals leading the data.

Figure 11 is the result of three sampled data under the condition that two sampled signals lag behind the data.

FIG. 12 is a logic block diagram of an oversampling logic unit.

FIG. 13 is a specific circuit structure diagram of the oversampling logic unit.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

The present invention is based on the CDR formed by the Bang Bang phase detector and digital loop filter adopted in the prior art, introduces an oversampling logic unit, and realizes an equivalent 3 times oversampling by changing the phase of edge sampling and multiplexing the data sampling unit. Sampling does not introduce a new sampling channel. The introduction of BBPD lock mode and oversampling lock mode enables PAM4CDR in burst mode to lock quickly and improve the jitter characteristics of the recovered clock.

As shown in Figure 2, a high-speed burst mode clock data recovery circuit suitable for PAM4 signals provided by the present invention, its basic structure is: sampling decision circuit 1, phase detection circuit 2, majority voting circuit 3, digital phase control module 5. Digital loop filter 6. Quadrature clock generation circuit 7. Phase synthesis module 8. In order to realize fast locking, the present invention introduces a second set of fast locking loops, including: an oversampling logic unit 4;

Sampling and decision circuit 1, used to receive the external input PAM4 data signal and the clock signal output by the phase synthesis module, and set the reference voltage to 0.25A, 0.5A and 0.75A according to the highest swing A of the signal, and digitally determine the input level Quantize, send the quantized result to the phase detector;

The phase detection circuit 2 is used to receive the quantized data signal and the clock signal output by the phase synthesis module, and generate a leading voltage signal and a lagging voltage signal of the clock relative to the data signal according to the phase relationship between the two, and convert the clock data The phase error voltage signal is sent to the majority voting circuit;

The majority voting circuit 3 is used to receive the output of the phase detector, combine the output data of the phase detector, output the only clock leading voltage signal and lagging voltage signal relative to the data signal, and send the phase error result to the digital phase control module ;

The oversampling logic unit 4 is used to control the switching of the loop lock mode between the oversampling mode, that is, the fast lock mode and the phase detector lock mode, oversample the input PAM4 data quantization result, and output the control signal to the digital phase control module;

The digital phase control module 5 is used to receive the phase detection result output by the majority of voters and the control signal sent by the oversampling logic unit, and output according to the different loop modes (oversampling loop mode or BBPD loop mode) in Control logic signal to phase synthesis module or digital loop filter;

The digital loop filter 6 is used to receive the digital logic signal sent by the digital phase control module and perform low-pass filtering processing on it, and send the output to the phase synthesis module;

The quadrature clock generation circuit 7 is used to receive an externally input reference clock signal, filter the external clock and generate two orthogonal clock signals, and send the generated I/Q two-way clock signals to the phase synthesis module;

The phase synthesizing module 8 is used to receive the logic control signal transmitted by the digital phase control module filtered by the digital loop filter, and two quadrature clocks. The two clocks are phase-shifted through the control logic, and the phase-shifted The clock signal is sent to the sampling decision circuit.

The high-speed burst mode clock data recovery circuit provided by the present invention introduces an oversampling locking mode on the basis of the BBPD loop locking mode by multiplexing the data sampling unit and changing the phase of edge sampling, thereby accelerating the loop locking speed, At the same time, lower power consumption can be achieved at the same locking speed.

In the embodiment of the present invention, as shown in FIG. 3 , the sampling decision circuit 1 includes: four samplers, four D flip-flops DFF and four groups of two-stage inverters; wherein, the sampler is used to compare the input level with the reference The level is compared and the comparison result is output.

Among the four samplers, sampler A, sampler B, and sampler C are used for sampling PAM-4 signals, and sampler D is used for edge sampling. The input terminals of the four samplers are all connected to the input signal. If the input signal is the highest level (for example, 600mV), the threshold levels of the samplers A, B, C, and D are 0.25A, 0.5A, 0.75A, respectively. 0.5A; the outputs of the four samplers are respectively connected to D flip-flops, marked as DFF_A, DFF_B, DFF_C and DFF_D. The sampling clocks of DFF_A, DFF_B, and DFF_C are all connected to the data sampling clock, and the sampling clock of DFF_D is connected to the edge sampling clock. The outputs of the four D flip-flops are all connected to two cascaded inverters, and the outputs of the four sets of inverters are respectively called data A, data B, data C and edge A, where data A, data B, data C is the sampling result of the input signal at time t, and edge A is the sampling result of the input signal at time 1.125t.

In the embodiment of the present invention, as shown in FIG. 3 , the phase detection circuit 2 includes: a Bang Bang phase detector; the Bang Bang phase detector is composed of two high-speed XOR gates. The first input end of the XOR gate A is connected to the output end of the fourth group of two-stage inverters, the second input end of the XOR gate A is connected to the output end of the second group of two-stage inverters, and the XOR gate A The output of is the clock advance signal. The first input end of the exclusive OR gate B is connected to the output end of the second group of two-stage inverters, the second input end of the exclusive OR gate B is connected to the data of the previous sampling point, and the output of the exclusive OR gate B is a clock delay Signal. The clock advance or lag information generated by the XOR gate can be used to adjust the system clock phase to achieve phase lock.

In the embodiment of the present invention, the input of the oversampling logic unit 4 is connected after the sampling decision circuit 1, and the output is connected with the digital phase control module 5, thereby introducing an oversampling locked loop except the BBPD locked loop, and the oversampling mode complex The data sampling unit, the edge sampling unit and the phase synthesis module of the BBPD locked loop are used.

When the CDR is initially started, the CDR will be in the oversampling mode by default. At this time, in the loop of the CDR, only the sampling decision circuit 1, the oversampling logic unit 4, the digital phase control module 5 and the phase synthesis module 8 are in the working state. The phase detection circuit 2, the majority voting circuit 3 and the digital loop filter 6 are all in an off state; when the oversampling logic unit 4 judges that the system is close to locking, the oversampling logic unit 4 will close the module and start the phase detection circuit 2, The majority voting circuit 3 and the digital loop filter 6 constitute the second phase-locked loop. The locked loop has the characteristic of small loop bandwidth, which can lead to better jitter performance.

In the embodiment of the present invention, as shown in Figure 4, the digital phase control module 5 includes: a clock frequency division module and a register set, the clock frequency division module is implemented as a D flip-flop with input and output short-circuited, and the clock input is a CDR master Clock, the output signal is connected to the register bank. The register group is a synchronous trigger logic, which receives the clock lag or clock advance information of the phase detector, and at the same time, the register group can receive the value of the oversampling register.

In the embodiment of the present invention, as shown in FIG. 5 , the digital loop filter 6 includes: a differential path gain G _prop , an integral path gain G _int , an integrator 1/(1-Z ^-1 ), and an integral path delay Z ^-Nint and accumulator Σ; wherein, the input digital signal is connected to the differential path gain and the integral path gain at the same time; the output of the integral path gain is connected to the input of the integrator; the output of the integrator is connected to the integral path delay; the output of the differential path gain The output delayed by the integration path is connected to the input terminal of the accumulator, and the output terminal of the accumulator is the output digital signal of the digital loop filter.

In the embodiment of the present invention, as shown in FIG. 6 , the quadrature clock generation circuit 7 includes: a filter network, wherein the filter network is composed of a capacitor C and a resistor R; the input clock signal is a differential signal, which is recorded as in+ and in-; the output The clock signal is an orthogonal differential signal, denoted as I+, Q+, I-, Q-; the A terminal of the resistor R1 is connected to in+, and the B terminal is connected to I+; the upper plate of the capacitor C1 is connected to in+, and the lower plate is connected to Q+ The A terminal of the resistor R2 is connected to the ground, and the B terminal is connected to the Q+; the upper plate of the capacitor C2 is connected to the ground, and the lower plate is connected to I-; the A terminal of the resistor R3 is connected to in-, and the B terminal is connected to I- The upper plate of capacitor C3 is connected to in-, the lower plate is connected to Q-; the A terminal of resistor R4 is connected to ground, and the B terminal is connected to Q-; the upper plate of capacitor C4 is connected to ground, and the lower plate Connected to I+.

In the embodiment of the present invention, the phase synthesis module 8 includes four groups of phase interpolation units; wherein, the four groups of phase interpolation units are independent of each other and controlled by different digital control signals. Two of the four groups of phase interpolation units are responsible for the phase generation of the sampling clock. Since the output of each group of phase interpolation units is a differential signal, it can generate clocks with four phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees as data sampling clocks. , respectively for each sampling channel. Similarly, the other two sets of phase interpolation units will generate clocks with four phases of 45 degrees, 135 degrees, 225 degrees, and 315 degrees as edge sampling clocks.

In the embodiment of the present invention, when in the burst mode, the oversampling logic unit 4 and the control logic control loop are in the oversampling mode. FIG. 7 shows a schematic diagram of the low-power fast oversampling principle adopted in the present invention. In the example of the present invention, according to the IEEE specification, in the 28Gbuad PAM-4 burst mode, the Preamble will be an NRZ format with the same height as the PAM4 data alternating 0 and 1. Therefore, at 28Gbps, this signal can be equivalent to a 14GHz clock. In 28Gbaud 4 time-interleaved sampling channel CDR, the sampling master clock is 7GHz. If we divide the 7GHz clock into 12 equal phases, it is equivalent to oversampling the input data by 6 times. Carefully observe the sampling results of each phase. Since the input data is regularly alternating 01, the data obtained by 6 times oversampling also has certain regularity. If we group the data into three groups, we can find that the results of every three sampled data will repeat continuously. Therefore, the oversampling can be simplified, and only three sampling phases are used to realize an equivalent 3 times oversampling.

The PAM4 CDR in the burst mode of the present invention realizes the fast oversampling function only by the multiplexing of the sampling circuit without adding additional sampling circuits. Compared with the traditional method: it avoids the generation of multiple equidistant phases , reducing the circuit complexity. According to data analysis, only 3 phases are used to achieve 3 times equivalent oversampling. In the traditional way, 6 phases are required and at the same locking speed, lower power consumption can be achieved.

In the example of the present invention, the lead-lag relation of the clock data is judged according to the data analysis. Fig. 8 is a loop locked situation. In this case, the result of every three sampled data is 110 and repeats non-stop; A situation where the sampling signal leads the data, in this case, the result of every three sampling data is 111 and repeats non-stop; Figure 10 shows the situation where the two sampling signals lead the data, in this case, every three sampling data The result is 011 or 001 and repeats non-stop; Figure 11 shows the case of two sampled signal lag data, in this case, the result of every three sampled data is 100 or 000 and repeats non-stop. Therefore, by simplifying the oversampling, only three sampling phases are used to realize an equivalent 3 times oversampling.

FIG. 12 is a logic block diagram of the oversampling logic unit 4 . When the CDR circuit is in the reset state, the oversampling logic unit 4 will control the CDR to be in the oversampling mode. If the three phase judgment signals input at this time are 110, it means that the CDR is in a state close to locking, and the oversampling logic unit 4 will control CDR enters BBPD lock mode; when the three input judgment signals are 111/011/001, it means that the phase is ahead, and the clock will lag behind; when the data is 100 or 000, it means that the phase is lagging, and the sampling phase will be increased at this time. The system will continue to repeat this process until it is locked (the decision signal is 110).

FIG. 13 is a specific implementation circuit block diagram of the oversampling logic unit 4, and the three sampled decision signals are respectively set as Sample[2], Sample[1], and Sample[0]. In order to achieve high speed, all circuits of the oversampling logic unit 4 need to work at a very high frequency. Therefore, in order to reduce the delay introduced by the logic unit, the logic of judging the lead and lag is optimized, and only 4 logic gates are needed to realize the judgment, and only 3 logic gates are needed in the longest path. The register control is a synthesizable bank of 8-bit registers. When the phase leading signal is high level (VDD), the register control will decrease the value of the 8-bit register group; when the phase lagging signal is high level (VDD), the register control will increase the value of the 8-bit register group value.

By adopting the above oversampling logic, the compromise between loop bandwidth and loop lock time in the traditional BBPD phase detection method is avoided, so that the reduction of the entire loop phase lock time does not depend on increasing the loop bandwidth. Based on this, the CDR chip example adopting the method of the present invention can realize phase locking within 7 ns while maintaining a loop bandwidth of 5 MHz.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (8)

1. A high speed burst mode clock data recovery circuit adapted for use with a PAM4 signal, comprising: the phase detection circuit comprises a sampling decision circuit (1), a phase discrimination circuit (2), a majority voting circuit (3), an oversampling logic unit (4), a digital phase control module (5), a digital loop filter (6), a quadrature clock generation circuit (7) and a phase synthesis module (8);

a first input end of the sampling decision circuit (1) is used for receiving an externally input PAM4 data signal, and a second input end of the sampling decision circuit (1) is connected to an output end of the phase synthesis module (8) and used for carrying out digital quantization on an input level according to a set reference voltage and outputting a quantization result;

the input end of the phase demodulation circuit (2) is connected to the output end of the sampling decision circuit (1) and is used for receiving the quantized data signal and the clock signal output by the phase synthesis module and generating a leading voltage signal and a lagging voltage signal of the clock relative to the data signal according to the phase relation between the quantized data signal and the clock signal;

the input end of the majority voting circuit (3) is connected to the output end of the phase detection circuit (2) and is used for outputting a unique leading voltage signal and a unique lagging voltage signal of a clock relative to a data signal after output data of the phase detection circuit are combined;

the input end of the over-sampling logic unit (4) is connected to the output end of the sampling decision circuit (1) and is used for controlling the switching of a loop locking mode between an over-sampling mode and a phase discrimination locking mode, over-sampling the PAM4 data signal quantization result and outputting a control signal;

a first input end of the digital phase control module (5) is connected to an output end of the majority voting circuit (3), and a second input end of the digital phase control module is connected to an output end of the oversampling logic unit (4) and used for outputting a digital logic signal according to a phase discrimination result output by the majority voter and the control signal;

the input end of the digital loop filter (6) is connected to the output end of the digital phase control module (5) and is used for performing low-pass filtering processing on the digital logic signal;

the orthogonal clock generating circuit (7) is used for receiving an externally input reference clock signal, filtering an external clock and generating two orthogonal clock signals;

a first input end of the phase synthesis module (8) is connected to an output end of the digital loop filter (6), and a second input end of the phase synthesis module (8) is connected to an output end of the quadrature clock generation circuit (7), and is configured to shift phases of two quadrature clocks according to the digital logic signal, and send a clock signal after the phase shift to the sampling decision circuit and the phase discriminator;

when the phase discrimination circuit is initially started, the phase discrimination circuit is preset to be in an oversampling mode, only a sampling decision circuit (1), an oversampling logic unit (4), a digital phase control module (5) and a phase synthesis module (8) in a loop are in a working state, and a phase discrimination circuit (2), a majority voting circuit (3) and a digital loop filter (6) are in a closed state; when the sampling logic unit (4) judges that the system is close to locking, the sampling logic unit (4) closes the module and starts the phase discrimination circuit (2), the majority voting circuit (3) and the digital loop filter (6) so as to switch to a phase discrimination locking mode.

2. A high speed burst mode clock data recovery circuit as claimed in claim 1, characterized in that the sampling decision circuit (1) comprises: a first sampler A, a second sampler B, a third sampler C, a fourth sampler D, a first D flip-flop DFF _ A, a second D flip-flop DFF _ B, a third D flip-flop DFF _ C, a fourth D flip-flop DFF _ D and four groups of two-stage inverters;

the first input end of the first sampler A, the first input end of the second sampler B, the first input end of the third sampler C and the first input end of the fourth sampler D are all used for connecting external input signals, the second input end of the first sampler A is connected with a first reference voltage REF1, the second input end of the second sampler B is connected with a second reference voltage REF2, the second input end of the third sampler C is connected with a third reference voltage REF3, and the second input end of the fourth sampler D is connected with the second reference voltage REF2;

a first input terminal of the first D flip-flop DFF _ a is connected to an output terminal of the first sampler a, a first input terminal of the second D flip-flop DFF _ B is connected to an output terminal of the second sampler B, a first input terminal of the third D flip-flop DFF _ C is connected to an output terminal of the third sampler C, and a first input terminal of the fourth D flip-flop DFF _ D is connected to an output terminal of the fourth sampler D; a second input terminal of the first D flip-flop DFF _ a, a second input terminal of the second D flip-flop DFF _ B, and a second input terminal of the third D flip-flop DFF _ C are all used for connecting a data sampling clock, and an output terminal of the fourth D flip-flop DFF _ D is used for connecting an edge sampling clock;

the input end of the first group of two-stage inverters is connected to the output end of the first D flip-flop DFF _ A, and the output end of the first group of two-stage inverters is used for outputting data A; the input end of the second group of two-stage inverters is connected to the output end of the second D flip-flop DFF _ B, and the output end of the second group of two-stage inverters is used for outputting data B; the input end of the third group of two-stage inverters is connected to the output end of the third D flip-flop DFF _ C, and the output end of the third group of two-stage inverters is used for outputting data C; the input end of the fourth group of two-stage inverters is connected to the output end of the fourth D flip-flop DFF _ D, and the output end of the fourth group of two-stage inverters is used for outputting an edge a;

wherein the first reference voltage REF1 is smaller than the second reference voltage REF2, and the second reference voltage REF2 is smaller than the third reference voltage REF3.

3. A high speed burst mode clock data recovery circuit as claimed in claim 2, characterized in that the phase detection circuit (2) comprises: a Bang phase discriminator; the Bang phase discriminator comprises an exclusive-or gate A and an exclusive-or gate B;

the first input end of the exclusive-or gate A is connected to the output end of the fourth group of two-stage inverters, the second input end of the exclusive-or gate A is connected to the output end of the second group of two-stage inverters, and the exclusive-or gate A outputs a clock leading signal for adjusting the clock phase and realizing phase locking;

and the first input end of the exclusive-OR gate B is connected to the output end of the second group of two-stage inverters, the second input end of the exclusive-OR gate B is connected with data of a previous sampling point, and the exclusive-OR gate B outputs a clock lagging signal for adjusting the clock phase and realizing phase locking.

4. A high speed burst mode clock data recovery circuit as claimed in claim 1, characterized in that the oversampling logic unit (4) comprises: the over-sampling control logic module is used for realizing phase locking logic in an over-sampling mode and judging whether the phase locking module is in a close locking state according to a phase result: if the digital phase control module is in a close locking state, the oversampling control logic module gives the value of the internal register to the digital phase control module.

5. The high speed burst mode clock data recovery circuit of claim 4 wherein the oversampling control logic module comprises: NOT gate, OR gate, NOR gate, AND gate and register;

the input end of the NOT gate is connected with a third sampling signal Sample [2], the output end of the NOT gate is connected with the first input end of the OR gate, the second input end of the OR gate is connected with a second sampling signal Sample [1], the output end of the OR gate is connected with the first input end of the AND gate, the second input end of the AND gate is connected with a first sampling signal Sample [0], and the output end of the AND gate is connected with the first input end of the register and used for outputting a phase advance signal; the first input end of the NOR gate is connected with the second sampling signal Sample [1], the second input end of the NOR gate is connected with the first sampling signal Sample [0], the output end of the NOR gate is connected with the second input end of the register and used for outputting a phase lag signal, and the register is used for outputting a phase control signal according to the phase lag signal and the phase lead signal.

6. A high speed burst mode clock data recovery circuit according to any of claims 1 to 5, characterized in that the phase synthesis block (8) comprises: four groups of phase interpolation units;

the two groups of phase interpolation units are used for generating clocks with four phases of 0 degree, 90 degrees, 180 degrees and 270 degrees as data sampling clocks which are respectively supplied to each sampling channel;

the other two groups of phase interpolation units are used for generating clocks with four phases of 45 degrees, 135 degrees, 225 degrees and 315 degrees as edge sampling clocks.

7. An oversampling logic control method based on the high speed burst mode clock data recovery circuit according to any one of claims 1 to 6, comprising the steps of:

(1) Judging whether the three input phase decision signals are 110, if so, controlling the CDR to enter a BBPD locking mode; if not, entering the step (2);

(2) Judging whether the three input phase judgment signals are 111, 011 or 001, if so, controlling to reduce the sampling phase and delaying the clock; if not, entering the step (3);

(3) And (4) judging whether the input three phase judgment signals are 100 or 000, if so, controlling to increase the sampling phase, otherwise, not needing phase operation and returning to the step (1).

8. A PAM4 receiver, the PAM4 receiver comprising: the device comprises a clock data recovery circuit, a PAM4 decoding circuit and an analog combiner;

the clock data recovery circuit is used for recovering data from an input signal by extracting a correct sampling phase; the PAM4 decoding circuit is used for decoding the data A, the data B and the data C output from the sampler into NRZ coded binary codes MSB1 and LSB1; the analog combiner is used for combining MSB1, MSB2, MSB3 and MSB4 of 4 sampling channels with 1/4 rate into a series MSB; and the LSB1, LSB2, LSB3 and LSB4 of the 4 sampling channels are fused into one LSB in series connection; the clock data recovery circuit is the high-speed burst mode clock data recovery circuit according to any one of claims 1 to 6.

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