CN114121900A - ESD device processing method with overvoltage and over-current protection functions - Google Patents
ESD device processing method with overvoltage and over-current protection functions Download PDFInfo
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- CN114121900A CN114121900A CN202210099219.6A CN202210099219A CN114121900A CN 114121900 A CN114121900 A CN 114121900A CN 202210099219 A CN202210099219 A CN 202210099219A CN 114121900 A CN114121900 A CN 114121900A
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- 238000003672 processing method Methods 0.000 title claims abstract description 13
- 238000012545 processing Methods 0.000 claims abstract description 49
- 238000004806 packaging method and process Methods 0.000 claims abstract description 7
- 238000003466 welding Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 26
- 239000010949 copper Substances 0.000 claims description 26
- 230000008021 deposition Effects 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 239000005022 packaging material Substances 0.000 claims description 4
- 238000001746 injection moulding Methods 0.000 claims description 3
- 238000004381 surface treatment Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 23
- 238000000151 deposition Methods 0.000 description 16
- 239000000243 solution Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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Abstract
The application discloses an ESD device processing method with overvoltage and overvoltage protection functions, which comprises the following steps: primarily plastically packaging and filling the frame to enable two end faces of each bonding pad in the frame to correspondingly protrude out of the two end faces of the frame; processing a fuse for connecting the voltage input electric connection pad and the voltage output electric connection pad between the voltage input electric connection pad and the voltage output electric connection pad; welding and mounting an antistatic chip on the top surface of the grounding bonding pad; the secondary plastic package filling frame forms an electric connection processing layer of the anti-static chip and the voltage output electric connection bonding pad, and the electric connection processing layer is electrically connected with the anti-static chip and the voltage output electric connection bonding pad; and plastically packaging the filling frame again to form a complete ESD device. The ESD device processing method with the overvoltage and overcurrent protection functions has the overvoltage and overcurrent double protection functions, sensitive electronic products are effectively protected, and the situation that the electronic products are damaged due to overvoltage and overcurrent failure is effectively avoided.
Description
Technical Field
The application relates to the technical field of electronic components, in particular to a processing method of an ESD device with overvoltage and overvoltage protection functions.
Background
In practical applications, a semiconductor device often suffers from an EOS (electrical over stress) fault, unstable power output quality, various noises of over-voltage and over-current, and an inrush current phenomenon in hot plug applications, which may cause EOS, and the device may be damaged by a spike voltage or a spike current in a short time.
How to effectively reduce the EOS fault risk of electronic components, improve the voltage resistance and the electric resistance of the components in the application process, and improve the reliability of products is worthy of research.
Disclosure of Invention
In view of this, the present application provides a method for processing an ESD device with overvoltage and overcurrent protection functions, which can protect a sensitive electronic product and prevent the product from being damaged due to overvoltage or overcurrent impact.
The application provides a processing method of an ESD device with overvoltage and overvoltage protection functions, which comprises the following steps:
primarily plastically packaging and filling the frame to enable two end faces of each bonding pad in the frame to correspondingly protrude out of the two end faces of the frame;
processing a fuse for connecting the voltage input electric connection pad and the voltage output electric connection pad between the voltage input electric connection pad and the voltage output electric connection pad;
welding and mounting an antistatic chip on the top surface of the grounding bonding pad;
the secondary plastic package filling frame forms an electric connection processing layer of the anti-static chip and the voltage output electric connection bonding pad, and the electric connection processing layer is electrically connected with the anti-static chip and the voltage output electric connection bonding pad;
and plastically packaging the filling frame again to form a complete ESD device.
Optionally, the step of "processing a fuse connecting the voltage input electrical connection pad and the voltage output electrical connection pad" includes the following steps:
carrying out whole-surface copper deposition treatment on the top surface of the primary plastic package frame to form a copper deposition layer;
and etching the dry film on the copper deposition layer to form a fuse for connecting the voltage input electric connection pad and the voltage output electric connection pad.
Optionally, two ends of the fuse are connected above the voltage input electric connection pad and the voltage output electric connection pad respectively.
Optionally, the step of "processing a fuse connecting the voltage input electrical connection pad and the voltage output electrical connection pad" includes the following steps:
performing local plasma surface treatment on the top surface of the primary plastic package frame between the voltage input electric connection bonding pad and the voltage output electric connection bonding pad to process a groove;
and carrying out local copper deposition treatment on the groove to form a fuse connected between the voltage input electric connection pad and the voltage output electric connection pad.
Optionally, the depth of the groove is 2 μm to 5 μm, and the width of the groove is 10 μm to 20 μm.
Optionally, the copper material obtained by the local copper deposition has a deposition thickness ranging from 1 μm to 3 μm and a width ranging from 10 μm to 20 μm.
Optionally, the step of forming an electrical connection processing layer of the anti-static chip and the voltage output electrical connection pad by the secondary plastic package filling frame, and electrically connecting the anti-static chip and the voltage output electrical connection pad on the electrical connection processing layer includes the following steps:
performing secondary injection molding on the plastic packaging material until the plastic packaging material exceeds the top surface of the anti-static chip to form an electric connection processing layer;
respectively processing a first blind hole and a second blind hole on the electric connection processing layer above the anti-static chip and the voltage output electric connection bonding pad;
and connecting electric connecting wires are electroplated between the first blind holes and the second blind holes.
Optionally, the first blind hole and the second blind hole are both flared blind holes.
Optionally, the upper and lower aperture ratio of the flared blind hole is greater than 0.65.
Optionally, the flared blind hole has a ratio of upper diameter to hole depth in the range of 0.6 to 1.
According to the ESD device processing method with the overvoltage and overcurrent protection functions, the fuse is connected between the voltage input electric connection pad and the voltage output electric connection pad, and the top surface of the grounding pad is pasted with the anti-static chip, so that the ESD device has the overvoltage and overcurrent double protection functions, sensitive electronic products are protected, and the situation that the electronic products are damaged due to overvoltage and overcurrent failure is avoided.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a conventional ESD device;
fig. 2 is a flowchart of a method for manufacturing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present disclosure;
FIG. 5 is a schematic view of the section A in FIG. 4;
FIG. 6 is a schematic view of section B of FIG. 4;
FIG. 7 is a schematic circuit diagram;
fig. 8 is a schematic diagram illustrating an implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 9 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 10 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 11 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 12 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 13 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 14 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 15 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 16 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
FIG. 17 is a schematic diagram of a fuse connection provided in an embodiment of the present application;
FIG. 18 is a schematic view of another connection of the fuse according to the embodiment of the present application;
FIG. 19 is a schematic diagram of another connection of the fuse according to the embodiment of the present application;
fig. 20 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 21 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 22 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 23 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 24 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 25 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application;
fig. 26 is a schematic diagram illustrating another implementation step of a method for processing an ESD device with overvoltage and overvoltage protection functions according to an embodiment of the present application.
In the figure, 10, the frame; 21. a ground pad; 22. a voltage input electrical connection pad; 23. a voltage output electrical connection pad; 31. an anti-static chip; 32. an electrical connection wire; 321. a first blind hole; 322. a second blind hole; 33. an ultra-thin ultra-fine line; 41. a copper deposition layer; 42. drying the film; 51. and (4) a groove.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Before the technical solutions of the present application are introduced, it is necessary to explain the background of the invention of the present application.
Referring to fig. 1, a conventional ESD device includes a frame 10, and a ground pad 21, a voltage output electrical connection pad 23, and a voltage input electrical connection pad 22 in the frame 10, and in practical applications, the ESD device plays an anti-static role in protecting electronic components in a circuit, but the electronic components may also encounter an EOS fault, and the electronic components are subjected to a spike voltage or a spike current in a short time, which is likely to damage the electronic components, especially expensive sensitive electronic components. According to the ESD protection circuit, the EOS fault problem easily suffered by electronic components is solved, and the overvoltage and overcurrent protection functions of the electronic components are integrated in the ESD device.
From physical knowledge, the calculation formula of the heat Q and the resistivity rho is shown as the following equation
In the formula, I is current, R is resistance, T is electrifying time, S is the sectional area of the lead, and L is the length of the lead. Therefore, effective overcurrent protection is added to electronic components electrically connected with the ESD device by connecting low-resistivity fuses between the bonding pads.
Referring to fig. 2, a method for processing an ESD device with overvoltage and overvoltage protection functions provided in the present application includes the following steps:
s100, referring to fig. 8, selecting a package frame 10 required by a product, referring to fig. 9, injecting a plastic package material to primarily package and fill the package frame 10, so that two end surfaces of each pad in the package frame 10 correspondingly protrude out of two end surfaces of the package frame 10;
s200, processing a fuse for connecting the voltage input electric connection pad 22 and the voltage output electric connection pad 23;
s300, referring to fig. 20, the anti-static chip 31 is soldered and mounted on the top surface of the grounding pad 21;
s400, referring to fig. 21 to 24, the secondary plastic package filling frame 10 forms an electrical connection processing layer of the anti-static chip 31 and the voltage output electrical connection pad 23, and electrically connects the anti-static chip 31 and the voltage output electrical connection pad 23;
s500, referring to fig. 25-26, the filling frame 10 is plastically molded again to form an ESD device as shown in fig. 3-6, so as to achieve full protection of the overvoltage and overcurrent protection circuit inside the product.
According to the ESD device processing method with the overvoltage and overcurrent protection functions, the fuse is connected between the voltage input electric connection pad 22 and the voltage output electric connection pad 23, once the fuse is subjected to overcurrent load, a large amount of heat is generated by a large current, the fuse is heated and fused, an open circuit is formed between the voltage output electric connection pad 23 and the voltage input electric connection pad 22, and the fuse heating and fusing characteristic under the large current is utilized to play an overcurrent protection role in a voltage output rear-stage circuit and an electronic component;
by means of the mode that the anti-static chip 31 is attached to the top surface of the grounding pad 21, the ultra-sensitive characteristic of the anti-static chip 31 to voltage is utilized, once an overvoltage load is applied, the anti-static chip 31 between the voltage output electric connection pad 23 and the grounding pad 21 can act to release damage load, the circuit and the components at the rear section of the voltage output electric connection pad 23 are fully protected, overvoltage protection between the voltage output electric connection pad 23 and the grounding pad 21 is achieved, the ESD device has the overvoltage and overcurrent double protection function, sensitive electronic products are protected, and the problems of repair and quality protection of expensive electronic products caused by overvoltage and overcurrent failure are avoided.
Fig. 7 is a schematic circuit diagram of an ESD device with overvoltage and overvoltage protection functions obtained by the method of the present application.
In one embodiment, the anti-static chip 31 is a TVS (Transient Voltage Suppressor) chip.
In one embodiment, the fuse is a copper wire.
In one embodiment, the fuse is an ultra-thin ultra-fine line 33 processed through a PCB or substrate. Compared with the traditional fuse which adopts fusing materials such as special polymers, complex alloys and the like, the copper material in the field of conventional PCBs or substrates has great cost advantage.
In one embodiment, the fuse may be an ultra-thin ultra-fine copper line formed by a dry film 42 etching process or by localized copper deposition.
In an embodiment, the step of "S200, processing a fuse connecting the voltage input electrical connection pad 22 and the voltage output electrical connection pad 23" includes the following steps:
s211, referring to fig. 10, performing a full-surface copper deposition process on the top surface of the primary plastic frame 10 to form a copper deposition layer 41;
s212, referring to fig. 11, the dry film 42 covers the predetermined fuse line between the voltage output electrical connection pad 23 and the voltage input electrical connection pad 22 above the copper deposition layer 41;
s213, referring to fig. 12, the ultra-thin ultra-fine line 33 connected to the voltage input electrical connection pad 22 and the voltage output electrical connection pad 23 is etched on the dry film 42 on the copper deposition layer 41 by using a conventional patterning process of a PCB or a substrate, and the ultra-thin ultra-fine line 33 is implemented as a fuse.
In one embodiment, since the ultra-thin ultra-fine line 33 has an extremely small line thickness and an extremely small line width, in order to ensure that both ends of the fuse are effectively connected to both the voltage output terminal electrical connection pad and the voltage input terminal electrical connection pad, both ends of the fuse are excessively connected above the voltage input electrical connection pad 22 and the voltage output electrical connection pad 23, respectively.
In a more specific embodiment, referring to FIGS. 13-14, the distance D between the ends of the fuse that are connected to the pads is greater than 50 μm. Meanwhile, in order to ensure that both ends of the ultra-thin ultra-fine line 33 are effectively connected to the voltage output electrical connection pad 23 and the voltage input electrical connection pad 22, the line width of the ultra-thin ultra-fine line 33 is 10 μm to 20 μm.
In an embodiment, considering the manner of processing the ultra-thin ultra-fine lines 33 by the dry film 42 etching process, the dry film 42 with better resolution is required, the implementation cost is higher, and in addition, the ultra-thin ultra-fine lines 33 are easy to have the risk that the dry film 42 or the bonding pads are bitten by etching liquid penetrating into the bottom of the dry film 42. The ultra-thin ultra-fine line 33 can also be formed by copper deposition, and the step of "machining a fuse connecting the voltage input electrical connection pad 22 and the voltage output electrical connection pad 23" can also be realized to specifically include the steps of:
s221, referring to fig. 15, performing a local plasma surface treatment on the top surface of the primary plastic package frame 10 between the voltage input electrical connection pad 22 and the voltage output electrical connection pad 23 to form a groove 51;
s222, referring to fig. 16, a fuse for connecting the voltage input connection pad 22 and the voltage output connection pad 23 is formed by performing a local copper deposition or a local sputtering process on the recess 51.
The ultrathin superfine circuit 33 electrically connected between the voltage output electric connection pad 23 and the voltage input electric connection pad 22 processed in the mode does not protrude out of the top surfaces of the two pads, provides an overcurrent protection function between the voltage output electric connection pad 23 and the voltage input electric connection pad 22, and does not affect the circuit connection on the top surface of the ESD device even if the ESD device is not subjected to secondary plastic packaging treatment.
In one embodiment, the local copper deposition is realized by a circuit board hole filling process, and the copper in the redundant part is removed by etching.
In one embodiment, the depth of the groove 51 is 2 μm to 5 μm, and the width of the groove 51 is 10 μm to 20 μm.
In one embodiment, the copper material obtained by the local copper deposition has a deposition thickness ranging from 1 μm to 3 μm and a width ranging from 10 μm to 20 μm.
In one embodiment, the length of the ultra-thin ultra-fine line 33 can be flexibly adjusted according to the requirements of different products on the overcurrent capacity.
In one embodiment, the fuse routing pattern between the voltage output electrical connection pad 23 and the voltage input electrical connection pad 22 may be implemented in various ways, taking into account the fuse length design requirements within the limited routing space and the electrical connection requirements of the pad-connected electronic components. As shown in fig. 17 to 19, the fuse traces are designed to be bent according to the distribution of the voltage output terminal electrical connection pads and the voltage input terminal electrical connection pads inside the frame 10 of the ESD device. The two bent sections of the fuse can also be realized in such a way that one of the sections is of a bent design.
In an embodiment, the step of "S400, forming an electrical connection processing layer of the anti-static chip 31 and the voltage output electrical connection pad 23 by the secondary plastic package filling frame 10, and electrically connecting the anti-static chip 31 and the voltage output electrical connection pad 23" specifically includes the following steps:
s410, referring to fig. 21, performing a secondary injection molding of the molding compound until the molding compound exceeds the top surface of the anti-static chip 31 to form an electrical connection processing layer;
s420, referring to fig. 22, a first blind via 321 and a second blind via 322 are respectively formed on the electrical connection processing layer above the anti-static chip 31 and the voltage output electrical connection pad 23;
s430, referring to fig. 24, the electrical connection line 32 is electroplated between the first via hole 321 and the second via hole 322.
In one embodiment, the first blind hole 321 and the second blind hole 322 are flared blind holes, which facilitates the electroplating process of welding the electrical connection wire 32 in the blind holes.
In one embodiment, the conventional bonding pad size of the currently used anti-static chip 31 is about 70 μm to 80 μm, the laser drilling process requires that the upper-lower aperture ratio (B/a or B/a) of the flared blind hole is greater than 0.65, and the upper-lower aperture ratio (H/a or H/a) of the flared blind hole is in the range of 0.6 to 1. Specifically, as shown in fig. 23, the first blind via 321 above the anti-static chip 31 has a via depth h ranging from 30 μm to 50 μm, an upper aperture a of the first blind via 321 ranges from 30 μm to 80 μm, a lower aperture b of the first blind via 321 ranges from 25 μm to 50 μm, and a lower aperture b of the first blind via 321 has a size that just matches a conventional pad size of the anti-static chip 31.
In other embodiments of the present application, if the product circuit including the electrical connection lines and the fuses does not require physical protection, then a secondary plastic encapsulation process is not required.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A method for processing an ESD device with overvoltage and overvoltage protection functions is characterized by comprising the following steps:
primarily plastically packaging and filling the frame to enable two end faces of each bonding pad in the frame to correspondingly protrude out of the two end faces of the frame;
processing a fuse for connecting the voltage input electric connection pad and the voltage output electric connection pad between the voltage input electric connection pad and the voltage output electric connection pad;
welding and mounting an antistatic chip on the top surface of the grounding bonding pad;
the secondary plastic package filling frame forms an electric connection processing layer of the anti-static chip and the voltage output electric connection bonding pad, and the electric connection processing layer is electrically connected with the anti-static chip and the voltage output electric connection bonding pad;
and plastically packaging the filling frame again to form a complete ESD device.
2. The ESD device processing method with overvoltage and overvoltage protection function according to claim 1, wherein said step of processing a fuse connecting the voltage input electrical connection pad and the voltage output electrical connection pad includes the following steps:
carrying out whole-surface copper deposition treatment on the top surface of the primary plastic package frame to form a copper deposition layer;
and etching the dry film on the copper deposition layer to form a fuse for connecting the voltage input electric connection pad and the voltage output electric connection pad.
3. The ESD device with overvoltage and overvoltage protection as claimed in claim 2, wherein two ends of said fuse are connected over said voltage input electrical connection pad and said voltage output electrical connection pad respectively.
4. The ESD device processing method with overvoltage and overvoltage protection function according to claim 1, wherein said step of processing a fuse connecting the voltage input electrical connection pad and the voltage output electrical connection pad includes the following steps:
performing local plasma surface treatment on the top surface of the primary plastic package frame between the voltage input electric connection bonding pad and the voltage output electric connection bonding pad to process a groove;
and carrying out local copper deposition treatment on the groove to form a fuse connected between the voltage input electric connection pad and the voltage output electric connection pad.
5. The ESD device with over-voltage and over-voltage protection as claimed in claim 4, wherein the depth of the groove is 2 μm-5 μm, and the width of the groove is 10 μm-20 μm.
6. The ESD device processing method with overvoltage and overvoltage protection functions according to claim 4, wherein the copper material obtained by the local copper deposition treatment has a deposition thickness ranging from 1 μm to 3 μm and a width ranging from 10 μm to 20 μm.
7. The ESD device processing method with overvoltage and overvoltage protection function according to claim 1, wherein said secondary plastic package filling frame forms an electrical connection processing layer of the anti-static chip and the voltage output electrical connection pad, and electrically connects the anti-static chip and the voltage output electrical connection pad on the electrical connection processing layer, specifically comprising the following steps:
performing secondary injection molding on the plastic packaging material until the plastic packaging material exceeds the top surface of the anti-static chip to form an electric connection processing layer;
respectively processing a first blind hole and a second blind hole on the electric connection processing layer above the anti-static chip and the voltage output electric connection bonding pad;
and connecting electric connecting wires are electroplated between the first blind holes and the second blind holes.
8. The ESD device with overvoltage and overvoltage protection as claimed in claim 7, wherein said first blind via and said second blind via are flared blind vias.
9. The ESD device processing method with overvoltage and overvoltage protection function according to claim 8, wherein the ratio of the upper aperture to the lower aperture of the flared blind hole is greater than 0.65.
10. The ESD device process with overvoltage and overvoltage protection as claimed in claim 8, wherein the ratio of the upper diameter to the depth of said flared blind hole is in the range of 0.6-1.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209419208U (en) * | 2019-03-14 | 2019-09-20 | 西安易朴通讯技术有限公司 | Surge protective device and electronic equipment |
| CN112216666A (en) * | 2019-07-11 | 2021-01-12 | 珠海格力电器股份有限公司 | Component electrical connection method and chip package |
| CN113643990A (en) * | 2021-06-29 | 2021-11-12 | 华宇华源电子科技（深圳）有限公司 | Board level packaging method and structure for improving device strength |
| CN113687205A (en) * | 2016-09-27 | 2021-11-23 | 亚德诺半导体集团 | Electrical overstress detection device |
| CN113725094A (en) * | 2021-11-01 | 2021-11-30 | 深圳中科四合科技有限公司 | Multi-chip hybrid packaging method and multi-chip hybrid packaging structure |
-
2022
- 2022-01-27 CN CN202210099219.6A patent/CN114121900A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113687205A (en) * | 2016-09-27 | 2021-11-23 | 亚德诺半导体集团 | Electrical overstress detection device |
| CN209419208U (en) * | 2019-03-14 | 2019-09-20 | 西安易朴通讯技术有限公司 | Surge protective device and electronic equipment |
| CN112216666A (en) * | 2019-07-11 | 2021-01-12 | 珠海格力电器股份有限公司 | Component electrical connection method and chip package |
| CN113643990A (en) * | 2021-06-29 | 2021-11-12 | 华宇华源电子科技（深圳）有限公司 | Board level packaging method and structure for improving device strength |
| CN113725094A (en) * | 2021-11-01 | 2021-11-30 | 深圳中科四合科技有限公司 | Multi-chip hybrid packaging method and multi-chip hybrid packaging structure |
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